JP3199522B2 - Digital ΔΣ modulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital .DELTA..SIGMA. Modulator for producing a 1-bit quantized output.

[0002]

2. Description of the Related Art FIG. 2 shows a digital .DELTA..SIGMA. Modulator which inputs a digital signal (a plurality of bits) and outputs a 1-bit PDM (pulse density modulation) signal. In FIG.
1 and 2 are adders, 3 is a quantizer, and 4 is a changeover switch. A multi-bit positive (+) reference value (+ REF) and a negative (-) reference value (-REF) for the adder 1 are provided. ) Is switched in response to the 1-bit quantized output from the quantizer 3 (| + REF | = | -RE).
F |). In such a conventional circuit, a tone (single frequency) component is generated in an output signal when a zero signal is input.

A primary digital .DELTA..SIGMA. Modulator of the type shown in FIG. 3 in which an offset (multiple bits) is added to a digital input signal of plural bits in order to reduce tone components generated in such an output signal is known. I have.
3, 5, 6, and 7 are adders, 8 is a register, 9
Is a quantizer, 10 is a changeover switch, and is a multi-bit positive (+) reference value (+ R
EF) or a negative (-) reference value (-REF) is switched in response to a 1-bit quantized output from the quantizer 9 (| + REF | = | -REF |). The adder 7 and the register 8 constitute an integrator.

Further, as shown in FIG. 4, a digital Δ デ ジ タ ル modulator of a type in which a dither signal of a plurality of bits from a dither generating circuit 11 is input to an adder 5 instead of an offset in order to reduce a tone component is also known. .

[0005]

However, the .DELTA..SIGMA. Modulator shown in FIG. 3 requires an adder for adding the offset to the input signal, and has a DC (constant) having the same absolute value as the offset and the opposite sign. Value), the output from the adder 5 is zero,
The operation is equivalent to that of a normal ΔΣ modulator without an offset as shown in FIG. 2, and therefore, a tone is generated similarly to that of FIG. In addition, the ΔΣ modulator shown in FIG. 4 requires a dither generation circuit 11 and an adder for adding a dither signal to an input signal.
There is a problem that the output signal has the frequency component of dither.

It is an object of the present invention to provide a digital ΔΣ modulator which solves the above problems.

[0007]

To achieve the above object, the following considerations were made. That is, in the digital ΔΣ modulator as shown in FIGS. 2, 3, and 4, the cause of an increase in tone components in the output signal is that the output signal is added to the adders 2 and 7 constituting the integrator every cycle. Are (+ REF) or (-REF) whose absolute values are the same, and (+ REF)
Since the sum of (F) and (−REF) is zero, the output of the integrator is a0 ± n · (RE
F) (where n is an integer), which can only be in a limited state, and the randomness is poor. Even in a ΔΣ modulator having a multi-order integrator, the possible states of the first integrator are small as described above, so that the possible states of subsequent integrators are also limited.

Therefore, in the ΔΣ modulator of the present invention, a positive reference value (+ REF) and a negative reference value input to the adder in response to the state of the 1-bit quantized output (“1” or “0”). Each absolute value of (-REF) is made different, and (+ REF)
And (−REF) are generated at an arbitrary ratio that is not zero, so that the integrator output has at least the number of cycles of the sum of the least common multiple of the two divided by | + REF | and | −REF | The initial value a0 does not appear until then, and during that time, the state can be much more than a0 ± n · (REF). Due to this randomness, the frequency components of the output signal of the ΔΣ modulator can be dispersed.

Assuming that the difference between | + REF | and | −REF | is 1, the integrator output can take the most states. If | + REF | = | −REF | −1, it is possible to create −REF only by inverting all bits of + REF in the feedback unit.
That is, when inverting the sign of a certain number, all bits are inverted,
One is added to the LSB, but if one is not added to the LSB, a number (a certain number of signs inverted) -1 can be created.

Example 0100: 4 0011: 3 0010: 2 0001: 1 0000: 0 1111: -1 1110: -2 1101: -3 1100: -4 1011: -5 The present invention has been made based on the above. Further, in the digital Δ 、 １ modulator that performs one-bit quantization output, the absolute values of the positive and negative signals fed back to the input unit according to the quantization output are made different.

[0011]

1 is a block diagram of a first-order digital ΔΣ modulator according to an embodiment of the present invention. In FIG. 1, reference numeral 12 denotes an adder, which inputs a multi-bit input signal to one input and outputs a 1-bit signal from the quantizer 15 as a reference value (to be described later in detail) to the other 4-bit input. Input the output of “1” or “0” in parallel (M
The bit next to SB is input via the inverter 16). The adder 13 for inputting the output of the adder 12 to one input and the register 14 constitute an integrator. Quantizer 15
Selectively passes the sign bit of the output from the integrator to 1
This is to get a bit output. It is also possible to use a higher-order integrator and arbitrarily weight each integrator output before introducing it to the quantizer.

According to the above configuration, when the output of the quantizer 15 is 0 (the sign bit of the integrator output is 0 as described above and the integrator output is positive or 0), + REF
= 4 (ie, 0100) is input to the adder 12,
-R when the output of the quantizer 15 is 1 (the integrator output is negative)
EF = −5 (ie, 1011) is input to the adder 12. As described above, | + REF | = | −REF | −
A relationship of 1 has been obtained, and the integrator output can take the most states.

Table 1 shows that + REF = + in the conventional circuit of FIG.
4, -REF = -4 and + R in the circuit of the present invention shown in FIG.
The state of the integrator output and the quantizer output for each cycle when EF = + 4, −REF = −5 is shown. In each case, the initial value of the integrator is set to 0 (1 cycle =
(1024 KHz = 0.98 μs). In the circuit of the present invention, the same pattern appears every nine cycles in the quantizer output, while the integrator output takes all nine values from -5 to 3. On the other hand, in the conventional circuit, the quantizer output repeats the same pattern every two cycles, and the integrator output takes only two values of 0 and -4.

Table 2 shows the result of Fourier transform of the quantizer output of Table 1 and decomposition for each frequency component. In Table 2, 0
/ 18 = DC (direct current), 9/18 = 512 KHz, and the numerical value indicates the AC voltage ratio when the peak of the conventional example is set to 1. The frequency component was obtained from the time axis data of 18 cycles, which is the least common multiple of the repetition periods of both. In the present invention, noise is distributed over five types of frequencies. In the conventional example, however, it was shown that noise was concentrated on only one type, that is, half of the operation cycle of the ΔΣ modulator.

[0015]

[Table 1]

[0016]

[Table 2]

[0017]

As described above, according to the present invention, a digital .DELTA..SIGMA. Module having a small tone component (noise) in an output signal can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional example.

FIG. 3 is a block diagram of another conventional example.

FIG. 4 is a block diagram of still another conventional example.

[Explanation of symbols]

 12, 13 adder 14 register 15 quantizer

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 3/02

Claims (1)

(57) [Claims] 1. A digital Δ which performs 1-bit quantization output
A digital delta-sigma modulator wherein the absolute values of the positive and negative signals fed back to the input section according to the quantized output are made different.