JP3199529B2 - △ Σ modulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a modulator, and more particularly to a modulator formed on a MOS LSI and having a high S / (N + D) when the level of a converted analog signal is small (S: signal, H: noise). , D: strain component) △ ΣRelated to the modulator.

[0002]

2. Description of the Related Art Conventionally, so-called multivalued (for example, 3
In the modulator, the output signal of the integrator for inputting the analog signal to be converted is quantized by the quantizer and converted into a digital code, and the analog signal is converted by the D / A converter. Convert to The analog signal value (D) to be added to the converted analog signal (input signal) in proportion to the absolute value of the integrating means.
/ A converter output) is changed stepwise. An example in which eight types of quantization outputs are performed is shown by a solid line in FIG.

In such a .SIGMA. Modulator, when the level of the converted analog signal (input signal) decreases, the outputs of more integrating means also output smaller absolute values. Small analog signal values become more frequently added to the converted signal.

The amount of noise output from the modulator is proportional to the rate of increase of the analog value added to the converted signal with respect to the output of the integrating means. In other words, the amount of noise is proportional to the step width of the fed-back analog value = H _{1 to} H ₇ , and the quantization threshold interval for providing the analog value = the voltage range represented by each quantized signal = It is proportional to W _{1 to} W ₈ .

[0005]

Therefore, in the conventional multi-valued △ Σ modulator, the above-mentioned steps are constant irrespective of the size of the signal to be converted, so that the output noise is also irrespective of the size of the signal to be converted. It will be constant,
As the input signal level decreased, S / (N + D) decreased linearly.

In particular, in an application field where an audio signal is A / D-converted, it is more and more desired to reduce noise at the time of a small input signal.

[0007]

In order to achieve the above object, the present invention provides an integrating means for integrating a converted analog signal, and comparing an output signal of the integrating means with N (N ≧ 3) analog reference values. Quantizing means for outputting N + 1 kinds of quantized outputs; adding means for adding N + 1 kinds of analog signals based on an output signal of the quantizing means to the converted analog signal at an input side of the integrating means; The ratio of the (N + 1) types of analog signal value intervals (H) to be added to the converted analog signal to the quantization threshold interval (W) in the quantization means increases in the region where the absolute value of the output signal of the integration means is large. Means. Here, (H) may be increased while (W) is kept constant, or (W) may be reduced while keeping (H) constant. Further, both (W) and (H) may be changed.

[0008]

According to the present invention, when the level of the converted analog signal is small, the rate of increase of the analog value added to the converted analog signal with respect to the output of the integrating means is small. Therefore, the amount of noise decreases and S / (N + D) increases.

[0009]

<Embodiment 1> FIG. 2 is a block diagram of a modulator according to the first embodiment. The converted analog signal is added to the output from the adding means 1 and input to the integrating means 2. The output signal of the integrating means 2 is quantized by the quantizing means 3 and converted to a digital code by the digital signal converting means 4. Is output. The output of the quantization means 3 is also input to the addition means 1.

In the first embodiment, a D / A conversion in which the output of the quantization means 3 is directly weighted in the addition means 1 is performed,
A non-linear analog signal is added to the converted analog signal on the input side of the integrating means 2, and the digital signal converting means 4 performs equivalent weighting on the converted analog signal to output a digital code.

The integrating means 2 comprises an operational amplifier 5 and a switched capacitor circuit comprising a capacitor C and switches (indicated by S1 and S2 in the figure, the same applies hereinafter) operated by a two-phase non-overlapping clock of S1 and S2. .

The quantizer 3 has seven parallel comparators CP.
1 to CP7, each of which compares the analog reference values VT1 to VT7 whose levels are increased at equal intervals with the output of the integrating means 2 and, when each of the reference values exceeds each reference value (logic level "1"). Output).

The adding means 1 has a D / A converter consisting of seven switched capacitor (hereinafter referred to as SC) circuits connected in parallel. That is, two capacitors C1
, One inverter 6 and switches operated by clocks S1 and S2 (indicated by S1 and S2 in the figure; the same applies hereinafter) to form one SC circuit, and similarly each of two capacitors C2 to C2 C7, one inverter each, and S
1 and S2 constitute a switch, and six SC circuits are configured. A reference potential is commonly applied to the seven SC circuits, and the capacitance ratios C1: C2: C of the capacitors C1 to C7 are applied.
3: C4: C5: C6: C7 is 6/33: 5/33: 4
/ 33: 3/33: 4/33: 5/33: 6/33. The output of each of CP1 to CP7 of the quantizing means 3 is weighted by the corresponding SC circuit of the adding means 1 and
The electric charge output from the C circuit is added to the converted analog signal on the input side of the integrating means 2. The addition means 1
In the above, for the analog signal to be converted on the input side of the integrating means 2, a path for performing subtraction when the output of the integrating means 2 is positive and addition when the output of the integrating means 2 is negative is selected. I have.

The digital signal converter 4 weights each output of the quantizer 3 equivalently to the D / A conversion in the adder 1 (-33: -21: -11: -3:
3: 11: 21: 33). That is, the input pattern to the digital signal conversion means 4 (the output Q1 to Q7 of "1" or "0" from each of the comparators CP1 to CP7 of the quantization means 3) and the 7-bit output after digital conversion (digital) Table 1 shows the relationship between codes and decimal expressions.

[0015]

[Table 1]

FIG. 3 shows an example of a digital signal conversion means for performing the above-mentioned weighting and outputting the total value as a digital code. That is, this corresponds to the input pattern (Q1
To Q7) and a logic circuit formed by a combination of a ROM or a logic element for generating an output code (7 bits) corresponding to the output code (7 bits). As shown in FIG. 4, the polarity of the code representing the weight (any one of 3 to 6) set to the output Q1 to Q7 of 1 or 0 of each of the comparators CP1 to CP7 of the quantizing means 3 is represented by A logic circuit that outputs a sum of positive (when output 1) or negative (when output 0) according to the output values (1 or 0) of the outputs Q1 to Q7 may be used.

According to such a configuration, as shown in FIG. 1, the step ratio H1: H2: H of the analog signal value from the adding means 1 added (subtracted) to the converted analog signal.
3: H4: H5: H6: H7 is 1/7: 1 in the conventional example
/ 7: 1/7: 1/7: 1/7: 1/7: 1/7: In the first embodiment, 6/33: 5/33: 4 /
33: 3/33: 4/33: 5/33: 6/33. That is, the analog signal value from the adding means 1 added to the converted analog signal in each area of the outputs W1 to W8 of the integrating means 2 is 7/7, 5/7, 3 /
7, 1/7, -1/7, -3/7, -5/7, -7/7
On the other hand, in the first embodiment, 33/33, 21/3
3,11 / 33,3 / 33, -3 / 33, -11 / 3
3, -21/33 and -33/33.

The △ Σ modulators of the conventional example and the first embodiment are operated by 1024 KHz clocks (S 1, S 2), a 1 KHz sine wave is input as a converted analog signal, and the input amplitude and S / (N + D) are converted. Evaluated the relationship. In the evaluation, 65536 continuous outputs from this modulator were collected, FFT (Fast Fourier Transform) operation was performed using a personal computer, the intensity was obtained for each frequency component, and the frequency range to be considered was 0 kHz.
４4 KHz, and S / (N
+ D) was calculated. FIG. 5 shows this state. In the first embodiment indicated by the broken line, when the amplitude of the input signal is small, S / (N + D) can be improved by about 10 dB as compared with the conventional example indicated by the solid line.

<Embodiment 2> FIG. 6 is a block diagram showing Embodiment 2 of the present invention. Only the addition means 11 is different.
Is the same as That is, the addition means 11 is the same as that of the first embodiment, but is a 7-bit weighted 7-bit signal from the digital signal conversion means 4 by a linear D / A converter 11A composed of seven SC circuits having different capacities of respective capacitors. The digital code output is converted into an analog signal and added to the converted analog signal on the input side of the integrating means 2. However, since the 7-bit digital code output from the digital signal conversion means 4 has already been expressed by a power of two,
The capacitors of each SC circuit to which each of the bit outputs is input have the same power-of-two size ratio. Alternatively, all the capacitors may have the same size, and each of the SC circuits may be supplied with each reference potential having a power-of-two ratio.

<Embodiment 3> As Embodiment 3, the configuration is the same as that of Embodiment 1, but the step of increasing the analog signal value added to the converted analog signal is fixed, that is,
Step ratio H1: H2: H3: H4: H5: H6: H
7 is 1/7: 1/7: 1/7: 1/7: 1/7: 1 /
7: 1/7, and the analog reference value for comparing the output from the integration means 2 in the quantization means 3 is configured to be denser as the absolute value of the output is larger and sparser as the absolute value of the output is smaller. Analog reference value interval ratio W'1: W '
2: W'3: W'4: W'5: W'6 is 1/6: 2 /
6: 3/6: 3/6: 2/6: 1/6. That is, V
The interval ratio of T1 to VT7 was made unequal. The above situation is shown in FIG.

The modulator according to the third embodiment was operated with a clock of 1024 KHz in the same manner as in the first embodiment, and S / (N + D) in a frequency range of 0 to 4 KHz for a sine wave of 1 KHz was calculated. FIG. 5 shows such a situation. Compared to the conventional example indicated by the solid line, in the third embodiment indicated by the dashed line, when the amplitude of the input signal is small, about 5 dB S
/ (N + D) could be improved.

<Others> The digital signal converting means in the present invention may output a digital code directly expressing an analog signal value to be added to the converted analog signal, or may add the digital code to the converted analog signal. It may output a digital code for designating which of a plurality of analog signal values to be output.

[0023]

As described above, according to the present invention, the high-frequency noise component is removed by the subsequent filter, so that when the level of the converted analog signal is low, the high S
/ (N + D) can be obtained. In particular, it is possible to realize an A / D converter, an analog arithmetic circuit, or the like that has a high S / (N + D) when the input signal amplitude is small.

[0024]

[Brief description of the drawings]

FIG. 1 is a diagram showing a relationship between an analog signal value added to a converted analog signal and an output of an integrating means.

FIG. 2 is a block diagram of a first embodiment of the present invention.

FIG. 3 is a diagram showing a specific example of a digital signal conversion unit.

FIG. 4 is a diagram showing another specific example of the digital signal conversion means.

FIG. 5 is a diagram illustrating a relationship between input amplitude and S / (N + D).

FIG. 6 is a block diagram of a second embodiment of the present invention.

FIG. 7 is a diagram showing a relationship between an analog signal value added to a converted analog signal and an output of an integrating means.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Addition means 2 Integration means 3 Quantization means 4 Digital signal conversion means

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 3/04

Claims (1)

(57) [Claims] 1. An integrating means for integrating a converted analog signal, and a quantizing means for comparing an output signal of the integrating means with N (N.gtoreq.3) analog reference values and outputting N + 1 types of quantized outputs. An adding means for adding N + 1 kinds of analog signals based on an output signal of the quantizing means to the converted analog signal at an input side of the integrating means; and the converting means for the quantization threshold interval in the quantizing means. Means for increasing the ratio of the N + 1 types of analog signal value intervals to be added to the analog signal in a region where the absolute value of the output signal of the integrating means is larger.
Modulator.