JP3200952B2 - Multi-reactor type process equipment controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a process equipment used for manufacturing a semiconductor having a single wafer processing mechanism, and more particularly to a multi-reactor type having a plurality of reaction chambers and capable of simultaneously performing a process in each reaction chamber. And a process equipment control device.

[0002]

2. Description of the Related Art In recent years, VLSI
-ULSI devices have been highly integrated and miniaturized.
Accordingly, there is a demand for a process facility having a plurality of reaction chambers capable of performing advanced process processing.

[0003] A conventional process facility control method will be described below. FIG. 8 shows an example of a schematic configuration of a conventional process equipment. 8, reference numeral 81 denotes a first reaction chamber for performing a process, 82 denotes a second reaction chamber, 83 denotes a transfer chamber, 84 denotes a spare chamber, 85 denotes a double arm, 86 denotes a wafer chuck arm, 87 denotes an orientation flat stage, and 88 , 89
Is a wafer cassette.

[0004] A control method of the process equipment configured as described above will be described below. First, the sequence schedule table shown in Table 1 is created by inputting the order of the reaction chambers in which the process is to be performed, and an executable sequence is searched from the execution conditions of this table. If there is an executable sequence, an operation command is sent to the sequencer. Output to control wafer transfer and processing. For example, when the processing is performed in the first reaction chamber 81 and then input is performed to perform the processing in the second reaction chamber 82, the wafer transfer path is always set to the wafer cassette 88 or 89 → the spare chamber 84 →
The transfer chamber 83 → the first reaction chamber 81 → the transfer chamber 83 → the second reaction chamber 82 → the transfer chamber 83 → the preliminary chamber 84 → the wafer cassette 88 or 89.

[0005]

[Table 1]

[0006]

However, in the above-mentioned conventional control method, only one type of wafer transfer path can be set, and the throughput is determined by the reaction chamber having the longest processing time. Had the disadvantage of waiting for the process to finish. Also,
There is a disadvantage that the processing of the wafers in the wafer cassette 88 in the first reaction chamber 81 and the processing of the wafers in the wafer cassette 89 in the second reaction chamber 82 cannot be performed simultaneously.

An object of the present invention is to solve the above-mentioned conventional problems and to provide a multi-reactor type process equipment having means capable of coping with various process patterns.

[0008]

In order to solve the above-mentioned problems, a process equipment control apparatus according to the present invention includes a plurality of reaction chambers for sequentially performing a process on a wafer and controls the process. A central processing unit, a memory for storing data and calculation results,
In a process facility equipped with a sequencer that operates an actuator in response to an input from a sensor, the processing order can be input for each wafer and stored in a memory, and can be executed from the stored order and sequence execution condition information. Means for searching for all possible sequences and means for outputting the execution of all executable sequences to the sequencer and corresponding to various process patterns.

[0009]

According to this configuration, a schedule table is prepared which describes the sequence execution sequence from the process processing sequence input for each wafer, and the central processing unit (C) calculates the sequence table from the sequence execution conditions stored in the memory in advance. The CPU searches for all executable sequences, outputs an operation command to the sequencer, and performs sequence processing, so that various sequence patterns can be handled.

[0010]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is an electrical block diagram showing a control unit of the process equipment shown in FIG. This process equipment is equipped with a spare room 1 from wafer cassettes 19 and 20 which are wafer storage units.
The process of transporting the wafer 10 to the plurality of reaction chambers 11 to 13 via the transfer chamber 6 and the transfer chamber 14 for processing is controlled by giving commands from the control unit 1 to the sequencers 5 to 8.

The control unit 1 is a CPU and includes a writing unit 1a, a reading unit 1b, a calculating unit 1c, a determining unit 1d, and an output unit 1e. The writing unit 1a writes data to the memory 3, and is connected to the input unit 2 for performing setting operations such as the order of process processing. The writing means 1a is connected to a memory 3 for storing setting inputs from the input means 2 and various data. This memory 3
Is connected to reading means 1b for reading data. This reading means 1b is connected to a calculating means 1c for controlling the operation of the entire equipment. This operation means 1c
In the present example, the sequence control is performed based on the setting signal, and the arithmetic processing for searching for an executable sequence in response to the process processing information given during the operation is also performed.

The calculating means 1c is connected to the writing means 1a while being connected to the judging means 1d. The determining means 1d determines a step number and the like, and outputs a command signal for executing a sequence program based on the calculation result of the calculating means 1c. This judging means 1d is connected to an output means 1e for sending a command signal to the sequencers 5 to 8. The output means 1e is connected to the CRT 4 and to the transfer system sequencer 5, the first reaction chamber sequencer 6, the second reaction chamber sequencer 7, and the third reaction chamber sequencer 8, respectively.

The transfer system sequencer 5 is a sequence board for controlling the transfer of the wafer 10 between the reaction chambers 13 to 15 via the wafer cassettes 19 and 20 described later and the preparatory chamber 16 and the transfer chamber 14. Accordingly, a detection signal from the sensor 5a is guided and sends a control signal to the actuator 5b. The first reaction chamber sequencer 6 is a sequence board for performing sequence control of the processing of the wafer 10 in the first reaction chamber 11, and receives a detection signal from the sensor 6a and sends a control signal to the actuator 6b. The sequencer 7 for the second reaction chamber is a sequence board for performing sequence control of the processing of the wafer 10 in the second reaction chamber 12, and is provided with a detection signal from the sensor 7a and an actuator 7b.
To send a control signal. The third reaction chamber sequencer 8
A sequence board for sequence-controlling the processing of the wafer in the first reaction chamber;
The detection signal from a is guided, and a control signal is sent to the actuator 8b.

These sequencers 5 to 8 are provided with each sensor 5
By driving the actuators 5b to 8b in response to the detection signals output from the a to 8a, the loading and unloading of the wafer 10 is performed according to a predetermined route. This transport process is configured to be executed by a plurality of sequence programs. ing.

The process equipment shown in FIG. 2 has three reaction chambers for processing the wafer 10. Each of the first to third reaction chambers 11 to 13 has a reaction chamber gate 11.
a, 12a and 13a, each reaction chamber gate 11
a to 13 a are connected to the transfer chamber 14. The transfer chamber 14 has a double arm 1 for replacing the wafer 10.
5 are arranged. Further, a spare chamber 16 is connected to the transfer chamber 14 via a transfer chamber gate 14a.
The preliminary chamber 16 is provided with an orientation flat stage 17 for detecting the orientation flat of the wafer 10 and performing alignment. Then, in front of the preliminary chamber 16, the wafer 10
A wafer chuck arm 18 for taking out the wafer is provided. Further, two wafer cassettes 1 for accommodating the wafers 10 are provided on both sides of the wafer chuck arm 18.
9 and 20 are arranged.

In the process equipment configured as described above, when the wafers 10 are sent and received between the wafer cassette 19 or 20 and the spare chamber 16, the inside of the spare chamber 16 is kept in an atmospheric state with nitrogen gas. It is. On the other hand, when the wafers 10 are transmitted and received between the reaction chambers 11 to 13 via the preparatory chamber 16 and the transfer chamber 14, the inside of the preparatory chamber 16 is kept in a high vacuum state. In each of the reaction chambers 11 to 13, the process is performed while controlling the flow rate, the degree of vacuum, the discharge power, the temperature, and the like of the reaction gas according to preset process conditions.

When the process equipment is started after setting the sequence processing contents (Table 2) and the sequence execution conditions (Table 3), the control unit 1 automatically executes the sequences 5 to 8 for performing the sequence control by task management. Scheduling tasks, schedule control tasks, wafer tasks, etc.

[0019]

[Table 2]

[0020]

[Table 3]

Is executed. Specifically, a process in which an automatic scheduling task creates a sequence schedule table (Table 4) and a wafer task creates a wafer sequence table (Table 5) and a wafer information table (Table 6) to change over time. It receives the processing information and performs a process to minimize the throughput.

[0022]

[Table 4]

[0023]

[Table 5]

[0024]

[Table 6]

Next, the processing operation by the processing equipment will be described with reference to flowcharts.

First, when operating the process equipment, a sequence processing number, a transfer step number and a wafer stay position number are set in advance by the input means 2. In this case, when the contents of the sequence processing are input under the conditions shown in (Table 2), the processing order is written in the memory 3 so that the process processing shown in FIG. 3 is performed. In addition, although the order for performing the process processing of the wafer 10 can be arbitrarily set for each wafer, in this example, the odd-numbered wafer is the first wafer.
The order of the reaction chamber, the second reaction chamber, and the even-numbered wafers are set to be the order of the first reaction chamber and the third reaction chamber.

Next, when the process equipment is operated, an automatic scheduling task and a schedule control task are started.

The automatic scheduling task includes a process sequence number, a transport process number, and a process order stored in the memory 3 in advance.
Is read and the calculation is performed in the calculation processing 1c.

Then, the flowchart shown in FIG. 5 is executed, 1 is substituted for N (step S51), and the sequence schedule table 1 shown in (Table 4) is created (step S52), and the wafer task is started (step S52). S53).

Subsequently, in this automatic scheduling task, the step number of the activated wafer task is read from the memory 3 and the judgment means 1d judges whether or not the step number has become 2 (step S54). Here, the operation is started, the step number becomes 1, the wafer 10 is transferred to the preparatory chamber 16, and it is checked whether the wafer 10 is transferred from the preparatory chamber 16 to the transfer chamber 14.

At this time, if the step number is 2, it is determined whether or not there is another wafer 10 (step S5).
5). Here, if there is no wafer 10, the process processing ends. However, if there is a wafer 10, 1 is added to N (step S56), a sequence schedule table N is created (step S57), and the next wafer task is executed. Is activated (step S58). Then, step S5
Then, the flow of FIG. 4 is repeated.

Incidentally, the wafer task started as described above executes the flowchart shown in FIG.
A wafer sequence table shown in (Table 5) is created.

Then, this wafer task substitutes 1 for the step number and substitutes 0 for the status flag and writes it into the memory 3 (step S61).

The step number is transmitted to the schedule control task (step S62).

Subsequently, it is determined whether or not the status flag has become 1; if the status flag has become 1 (step S63),
Wait for the status flag to change to 0. Here, when the status flag becomes 0 (step S64), the step number is read from the memory, and the determination is made by the determination means 1d.

Thereafter, it is determined whether or not the step number has become N, that is, whether or not the final processing has been performed (step S65).

At this time, if the final processing has not been completed,
The process proceeds to step S62, and the process ends when the step number becomes N.

By the way, the schedule control task started together with the above-mentioned automatic scheduling task executes the processing shown in the flowchart of FIG.
First, it is determined whether or not there is one whose sequence has been completed (step S71).

At this time, if there is no sequence end, the process proceeds to step S74. If the sequence ends, 1 is added to the step number of the corresponding wafer task, and the wafer staying position table is updated (step S7).
2).

Subsequently, after setting the status flag of the corresponding wafer task to 0 (step S73), it is determined in step S74 that the step number is to be transmitted.

Here, when the step number transmitted from the wafer task is received (step S74), the schedule control task reads the step number from the memory 3 and reads the schedule table shown in (Table 4).
An executable sequence is searched from the wafer information table shown in (Table 6) and the sequence execution condition of (Table 3) (step S76).

Here, it is determined whether or not there is an executable sequence (step S77). If there is no executable sequence, the process proceeds to step S71. If there is an executable sequence, the status flag of the corresponding wafer task is set to 1 ,
Update the wafer retention position table (step S7)
8).

Thereafter, a command signal is output to the sequencer (step S79), and the flow returns to step S71 to repeat the same operation as described above.

For example, assuming that the process proceeds in the above process and the state shown in FIG. 4 is assumed, the state of the six wafers No. 1 to No. 6 transferred to the process equipment is as follows. .

Wafer No. 1. The process has been completed in the second reaction chamber 12, and is waiting for transfer to the transfer chamber 14.

Wafer No. 2. The process has been completed in the third reaction chamber 13 and is waiting for transfer to the transfer chamber 14.

Wafer No. 3. The process is completed in the first reaction chamber 11. Wafer No.4. The transfer from the preliminary chamber 16 to the transfer chamber 14 has been completed, and the transfer to the first reaction chamber 11 is awaited.

Wafer No. 5. The transfer from the wafer cassette 19 to the preliminary chamber 16 has been completed, and the transfer to the transfer chamber 14 is awaited.

Wafer No. 6. It is waiting for movement to the spare room 16. At this time, the wafer sequence table of each wafer task has changed to the state shown in (Table 7) and the wafer information table has changed to the state shown in (Table 8).

Here, each wafer task will be described. Since the step number is not 11 (the position of the wafer cassettes 19 and 20), the step number 8 is transmitted to the schedule control task to wait for the status flag to become 1.

Wafer task No. 2. Step number is 1
Since it is not 1, it transmits step number 8 to the schedule control task and waits until the status flag becomes 1.

Wafer task No.3. Step number is 1
Since it is not 1, the step number 4 is transmitted to the schedule control task, and it waits until the status flag becomes 0.

Wafer task No. 4. Step number is 1
Since it is not 1, it transmits step number 3 to the schedule control task and waits until the status flag becomes 1.

Wafer task No.5. Step number is 1
Since it is not 1, it transmits step number 2 to the schedule control task and waits until the status flag becomes 1.

Wafer task No. 6. 1 for the step number
Is assigned to the status flag, and step number 1 is transmitted to the schedule control task to wait for the status flag to become 1.

[0056]

[Table 7]

[0057]

[Table 8]

For the schedule control task, all executable sequences are searched, and an example of the search is as follows.

1. Step number 8 from wafer task 1
Is transmitted, the process (4) is started from the position of step 8 in the sequence schedule table of (Table 9), and it is read that the current staying position is the staying position of the movement destination.

2. Step number 8 from wafer task 2
Is transmitted, the process (4) is started from the position of step 8 in the sequence schedule table of (Table 7), and it is read that the current staying position is the staying position of the movement destination.

3. Step number 3 from wafer task 4
Is transmitted, the process (3) is started from the position of step 3 in the sequence schedule table of (Table 7), and the fact that the current staying position is from the destination staying position is read.

4. Step number 2 from wafer task 5
Is transmitted, the process (2) is performed from the position of step 2 in the sequence schedule table of (Table 9), and it is read that the current staying position is the staying position of the movement destination.

5. Step number 1 from wafer task 6
Is transmitted, the process (1) is read from the position of step 1 in the sequence schedule table of (Table 7), and it is read that the current staying position is the staying position of the movement destination.

6. When there is a request in step (1), the presence or absence of a wafer at the wafer holding position is searched from the wafer information table in (Table 10) based on the sequence execution condition created in advance (Table 3). It is determined that the sequence 1 of ()) cannot be executed.

7. When there is a request for step (2), the presence / absence of a wafer at the wafer holding position is searched in the wafer information table from the sequence execution conditions. When there is a wafer, there is no request for step (5).
Judge that cannot be executed.

8. When there is a request for the step (3), the presence or absence of a wafer at the wafer holding position is searched from the wafer information table based on the sequence execution condition. Since it has not been performed, it is determined that Sequence 4 cannot be executed.

9. When there is a request for step (4), the presence or absence of a wafer at the wafer holding position and the presence or absence of a wafer at the holding position (no reservation) are searched from the wafer information table based on the sequence execution conditions. It is determined that the sequences 5 and 6 cannot be executed because there is no one requesting the step (3) where n is equal. Therefore, it can be said that there is no newly startable sequence.

[0068]

[Table 9]

[0069]

[Table 10]

Next, when the process sequence 10 in the first reaction chamber 11 is completed, the sequence end is transmitted from the sequencer 6 to the schedule control task, and the status flag of the wafer sequence table of the wafer task No. 3 is set to 0, the step number is set to 5, and In the wafer information table, the processing note flag is set to 0, and the processing completion flag is set to 1.

[0071]

[Table 11]

The wafer task No. 3 transmits the step number 5 because the status flag has become 0. Since the schedule control task has the transmission of the step number 5, the process starts from the position of the step 5 in the sequence schedule table of (Table 6a) (4), and the current staying position is the staying position of the moving destination. reading,
An executable sequence is searched for in the same manner as described above.

In this case, since the step (4) of the wafer task No. 3 and the wafer task No. 4 can be performed, the simultaneous movement sequence No. of the wafer tasks No. 3 and No.
The status flag is set to 1, and the sequence is output to the sequencer 5. Hereinafter, the processing is executed in the same procedure as described above.

[0074]

[Table 12]

As described above, according to the present embodiment, the process processing with a long processing time is performed in the second reaction chamber 12 and the third reaction chamber 1.
3, the throughput can be minimized by task management, and the sequencers 5 to 8 that operate based on this sequence control execute the sequence program to execute the wafer 10 transfer. Is carried out without any loss time, and the process speed becomes high.

Further, the transfer order of the wafer 10 is changed from the wafer cassette 19 → the preliminary chamber 16 → the transfer chamber 14 → the first reaction chamber 11 →
Transfer chamber 14 → Preparatory chamber 16 → Wafer cassette 19 and wafer cassette 20 → Preparatory chamber 16 → Transfer chamber 14 → Third reaction chamber 1
3 → Transfer chamber 14 → Preparatory chamber 16 → 2 of wafer cassette 20
If the type is input, different processing can be performed simultaneously in the same manner as in the present embodiment.

[0077]

As described above, the present invention can cope with various process patterns by inputting the order of process processing for each wafer, and the control unit sends a command signal for executing the sequence program to the sequencer. In order to transfer the unprocessed wafers to the reaction chamber preferentially and control the unprocessed wafers to be unloaded and transferred to the wafer storage unit, the unprocessed reaction chambers are always unprocessed in a short time. Since the wafer is supplied and the transfer of the wafer is performed without any loss time, there is an effect that the efficiency of the process is improved.

[Brief description of the drawings]

FIG. 1 is an electrical block diagram of a control unit according to an embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of a process facility.

FIG. 3 is an explanatory diagram showing a process performed by a process facility.

FIG. 4 is an explanatory diagram showing a position of a wafer in the process equipment.

FIG. 5 is a flowchart illustrating the operation of an automatic scheduling task.

FIG. 6 is a flowchart illustrating an operation of a wafer task.

FIG. 7 is a flowchart illustrating the operation of a schedule control task.

FIG. 8 is a schematic configuration diagram of a conventional process equipment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Control part 1a Writing means 1b Reading means 1c Calculation means 1d Judgment means 1e Output means 3 Memory 4 CRT 5 Transport system sequencer 5a Transport system sensor 5b Transport system actuator 6 First reaction chamber sequencer 6a First reaction chamber Sensor 6b First reaction chamber actuator 7 Sequencer for second reaction chamber 7a Sensor for second reaction chamber 7b Actuator for second reaction chamber 8 Sequencer for third reaction chamber 8a Sensor for third reaction chamber 8b For third reaction chamber Actuator 9, 17, 87 Orientation flat stage 10 Wafer 11, 81 First reaction chamber 12, 82 Second reaction chamber 13 Third reaction chamber 14, 83 Transfer chamber 15, 85 Double arm 16, 84 Preparatory chamber 18, 86 Wafer chuck Arm 19,20,88,89 Wafer cassette

Claims (1)

(57) [Claims] A plurality of reaction chambers for sequentially performing process processing on the wafer, a central processing unit, a memory for storing data and calculation results, and a sensor for controlling the process processing. In a process facility equipped with a sequencer that operates an actuator in response to an input of a command, means for inputting the order of process processing for each wafer and storing the same in a memory; A multi-reactor type process equipment control device, comprising: means for searching for a sequence of (1), and means for outputting execution of all executable sequences to a sequencer and corresponding to various process patterns.