JP3201042B2 - Phase frequency comparison circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase frequency comparison circuit. More particularly, the present invention relates to a novel phase frequency comparison circuit configuration that can be advantageously used in GaAs MESFET integrated circuits.

[0002]

2. Description of the Related Art FIG. 9 is a diagram showing a typical configuration of a conventional phase frequency comparison circuit.

As shown in FIG. 1, this phase frequency comparison circuit is composed of three JK flip-flops 91, 92 and 93. ₂ terminal, the Q ₃ terminal to "1", Q ₁ ^* pin OR the K terminal input, has a configuration to "0" to Q ₂ ^* pin.

[0004]

When the above-mentioned conventional phase frequency comparison circuit is used, a circuit for extracting a clock component from an NRZ data string is required, for example, to configure a clock data recovery circuit. . Further, it is necessary to input the phase frequency comparison output to the loop filter via the charge pump circuit. However, it is known that it is difficult to form a charge pump circuit in an integrated circuit using GaAs MESFETs, which has been widely used in recent years.

Accordingly, an object of the present invention is to solve the above-mentioned problems of the prior art and to provide a novel phase frequency comparison circuit which can be effectively used even in an integrated circuit using GaAs MESFETs.

[0006]

According to the present invention, a first phase comparator for receiving a reference signal of a predetermined frequency generated by a voltage controlled oscillator and a data signal based on a predetermined clock signal, and the reference signal Phase shifter for shifting the phase of the phase shifter by 90 °
, A conversion unit for converting the phase comparison output of the first and second phase comparison units into a frequency comparison output, and receiving the output of the phase comparison unit and the output of the conversion unit and summing them And a superposition unit for outputting the phase-frequency signal.

[0007]

The phase frequency comparison circuit according to the present invention has a
A major feature lies in that it is configured to be easily used in an AsMESFET integrated circuit.

FIG. 1 is a diagram showing a basic configuration of a phase frequency comparison circuit according to the present invention.

As shown in FIG. 1, this circuit mainly comprises a first phase comparator 10, a superposition unit 20, a converter 30, a second phase comparator 40, and a 90-degree phase shifter 50. ing.
In the figure, VCO and VCO ^* input to this circuit represent complementary outputs of the voltage controlled oscillator, and D and D ^* represent complementary input data signals. Also, when the phases are synchronized, the frequency f _VCO of the VCO and VCO ^* matches the reference clock frequency f _{D of the} data signal.

[0010] The phase comparator 10 outputs a voltage controlled oscillator output VC.
O, VCO ^* (frequency f _VCO ) and data signals D, D
^* Receive (data rate f _D ) as it is. In addition, the phase comparator 40 determines that the VCO and VCO ^* are phase-shifted by the phase shifter 50.
VCO ₉₀ and VCO ₉₀ ^* shifted by 90 degrees are received together with data signals D and D ^* . Here, when the frequency f _VCO does not match the frequency f _D , the phase comparators 10 and 40 generate a beat signal of the frequency | f _VCO −f _D |. When they match, an output corresponding to the phase shift is generated.

FIG. 2 is a diagram for explaining the basic configuration and operation of a circuit that can be used as the phase comparator 10 or 40 in the circuit shown in FIG. In the following description, reference numerals enclosed in parentheses indicate signals in the phase comparison unit 40, and reference numerals not enclosed indicate signals in the phase comparison unit 10, respectively.

As shown in FIG. 2A, this phase comparator can be constituted by a pair of latches 11, 12 and a multiplexer 13. Voltage controlled oscillator outputs VCO, VCO ^* (VCO
₉₀ , VCO ₉₀ ^* ) are connected to the inputs of the latches 11 and 12, and the data signals D and D ^* are input to the control terminals of the latches 11 and 12. Here, the data signal D is also input to the control terminal of the multiplexer 13. Each latch 1
The outputs of 1 and 12 are both connected to the input of a multiplexer 13. The output of the multiplexer 13 is a phase comparison output P.
D, PD ^* (QPD, QPD ^* ).

The VCO (VCO ^* ) and D (D ^* ) input to the phase comparator configured as described above are shown in FIG.
The relationship is as shown in FIG. Therefore, the output of the phase comparison unit changes as follows according to the relationship between the VCO frequency f _VCO and the frequency f _{D of D.}

(1) When f _VCO is smaller than f _D ; PD
Is the pulse of the frequency (f _D -f _VCO). QPD is
Frequency (f _D −
f _VCO ). (2) When f _VCO is larger than f _D ; PD has a frequency (f
It is a pulse of _VCO -f _D). QPD is better than PD
This is a pulse with a frequency (f _VCO -f _D ) delayed by 90 degrees in phase. (3) When f _VCO and f _D are equal and the phase of the VCO is later than that of D; PD goes to the “H” level. QP
D becomes "H" level. (4) When f _VCO and f _D are equal and D has a phase behind the VCO; PD goes to “L” level. QP
D becomes "H" level.

FIG. 3 is a circuit diagram of the converter shown in FIG.
FIG. 3 is a diagram for explaining the configuration and operation of a circuit that can be used as 30.

As shown in FIG. 1, the conversion unit can be constituted by a pair of latches 31 and 32 and a pair of NANDs 33 and 34. Here, QPD and QPD ^* , which are outputs of the phase comparison unit 40, are input to the inputs of the latches 31 and 32, respectively. The control terminals of the latches 31 and 32 have a phase comparator.
PD or PD ^*, which is the output of 10, is input. Further, the output of the latch 31 is input to the NAND 33 together with PD ^* . The output of the latch 32 is input to the NAND 34 together with the PD. The outputs of the NANDs 33 and 34 are the outputs TR and TR ^{* of the} conversion unit.

The output of the converter configured as described above is
It changes as follows in accordance with the relationship between the frequency f _D of the frequency f _VCO and the data signal D of the voltage controlled oscillator output VCO.

(1) When f _VCO is smaller than f _D ; TR
Is a pulse synchronized with the PD, and TR ^* goes to the “H” level. (2) When f _VCO is larger than f _D ; TR is at the “H” level, and TR ^* is a pulse synchronized with PD. (3) When f _VCO and f _D are equal and the phase of the VCO is later than that of D; (from the state of f _VCO <f _D , f _VCO
= F _D ) TR and TR ^* are both "
H "level. (4) When f _VCO and f _D are equal and D has a phase lag behind _VCO ; (from the state of f _VCO > f _D , f _VCO
= F _D ) TR and TR ^* are both "
H "level.

That is, the outputs PD, P of the phase comparator 10 (40)
When D ^* (QPD, QPD ^* ) is input to the conversion unit 30,
If the frequency f _VCO is lower than the frequency f _D , the output TR
Pulse signals synchronized with PD ^* and PD are output as ^* and TR. If the relationship between the frequency f _VCO and the frequency f _D is other than this, the “H” level is output. That is, the conversion unit 30 converts the phase comparison output of each of the phase comparison units 10 and 40 into a frequency comparison output.

FIG. 4 is a diagram for explaining the configuration and operation of a circuit that can be used as the superposition unit 20 in the circuit shown in FIG.

As shown in FIG. 4, the circuit includes three differential amplifiers 2 each having a pair of complementary inputs and outputs.
1, 22, and 23. Here, the inverting inputs of the differential amplifiers 21 and 23 commonly receive a predetermined reference voltage. The non-inverting inputs of the differential amplifiers 21 and 23 receive the output TR or TR ^* of the converter 30. Further, the input of the differential amplifier 22 receives the complementary outputs PD and PD ^* of the phase comparator 10. On the other hand, after the inverted output of the differential amplifier 22 is added to the inverted output of the differential amplifier 21,
The output Q ^* is added to the non-inverted output of the differential amplifier 23. The non-inverted output of the differential amplifier 22 is
After being added to the inverted output of 23, it is further added to the non-inverted output of the differential amplifier 21 to become the output Q. Actually, the DC bias voltage V ₀ is further added to each of the outputs Q and Q ^* and output.

The outputs Q and Q ^* of the superimposing unit configured as described above change depending on the relationship between the frequency f _VCO and the frequency f _D. That is, FIG. 5 shows the frequency f _VCO and the frequency f _D
FIG. 6 is a diagram showing signal waveforms of outputs Q and Q ^* of this circuit, which change depending on the relationship between the output Q and the output Q ^* .

Table 1 shows that each of the amplifiers 21, 22,
Shows 23 output levels.

[0024]

[Table 1]

(1) When f _VCO is smaller than f _D ; FIG.
As shown in (a), Q is a signal in which a pulse (center value V ₀ ) synchronized with PD ^* and a DC component [−V _of ] are superimposed. Q ^* is a pulse synchronized with PD (center value V
₀ ) and a DC component [+ V _of ]. (2) When f _VCO is larger than f _D ; As shown in FIG. 5B, Q is a pulse (center value V ₀ ) synchronized with PD ^* and a DC component [+ V _of ] superimposed. Signal.
Q ^* is a signal in which a pulse (center value V ₀ ) synchronized with the PD and a DC component [−V _of ] are superimposed. (3) When f _VCO and f _D are equal and the phase of the VCO is later than that of D; (from the state of f _VCO <f _D , f _VCO
= F _D ) As shown in FIG. 5C, Q is [V
₀ -2V _of] next, Q ^* is the [V ₀ + 2V _of]. (4) When f _VCO and f _D are equal and D has a phase lag behind _VCO ; (from the state of f _VCO > f _D , f
_VCO = when approached f _D) 5 (is Q as shown in d) [V ₀ + 2V _of] next, Q ^* becomes [V ₀ -2 V _of].

In the phase frequency comparison circuit according to the present invention having the above-described configuration, by adding a loop filter immediately after the phase frequency comparison circuit, it is possible to perform phase synchronization control such that the phase and frequency of the voltage controlled oscillator match. A control signal can be generated.

Further, according to this method, desired functions can be realized without adding a circuit for extracting a clock component from a data signal, a charge pump circuit, and the like. Therefore, it can be used in a GaAs MESFET integrated circuit in which it is difficult to configure a charge pump circuit.

According to one embodiment of the present invention, in the phase frequency comparison circuit shown in FIG.
It can also be constituted by a type flip-flop. FIG.
FIG. 3 is a diagram for explaining a function of a phase comparison unit configured using a D-type flip-flop.

As shown in FIG. 10A, the outputs VCO and VCO ^* of the voltage controlled oscillator are applied to the D-type flip-flop ^.
Is input to the data input, and the data reference clock signal is set to D.
Input to control input of type flip-flop. Where D
The VCO (VCO ^* ) and the clock signal CK (CK ^* ) input to the type flip-flop have a relationship as shown in FIG. Therefore, the output DFF of the phase comparator is
It changes as follows depending on the frequency f _{VCO of the VCO} and the frequency f _CK of the clock signal CK.

(1) When f _VCO is smaller than f _CK ; DF
F is a pulse having a frequency (f _CK −f _VCO ). QDFF
Is the frequency (f _CK −f
_VCO ) pulse. (2) When f _VCO is greater than f _CK ; DFF is a pulse of frequency (f _VCO −f _CK ). QDFF is DFF
This is a pulse having a frequency (f _VCO −f _CK ) delayed by 90 degrees from the phase. (3) When f _VCO is equal to f _CK and the phase of the VCO is later than that of D; DFF goes to the “H” level. Q
DFF becomes "L" level. (4) When f _VCO and f _CK are equal and D has a phase lag behind VCO; DFF goes to “L” level. Q
DFF becomes "L" level.

Therefore, D-type flip-flops are used as the phase comparators 10 and 40 of the phase frequency comparator shown in FIG. 1, and the outputs PD, PD ^* , QPD, QPD of the phase comparators 10 and 40 are used.
Instead of PD ^* , output DF of D-type flip-flop
By using F, DFF ^* , QDFF, and QDFF ^* , this phase frequency comparison unit operates in the same manner as the case described above with reference to the configuration shown in FIG. However, this configuration requires a clock signal CK to be supplied to the D-type flip-flop.

Hereinafter, the present invention will be described in detail with reference to examples. However, the following disclosure is merely an example of the present invention.
It does not limit the technical scope of the present invention at all.

[0033]

FIG. 6 is a diagram showing a specific example of the configuration of the phase comparator shown in FIG.

As shown in the figure, each input terminal of this circuit has a pair of FETs Q ₁₁ -Q ₁₂ , Q ₂₁ receiving complementary outputs VCO, VCO ^* of the voltage controlled oscillator at their gates, respectively.
-Q ₂₂ and a pair of FETs Q ₃₁ -Q ₃₂ receiving gates of the data signals D and D ^* .

With respect to the FET pair Q ₁₁ -Q ₁₂ and Q ₂₁ -Q ₂₂ , FETs Q ₁₄ and Q ₂₄ whose current paths including the FETs Q ₁₅ and Q ₂₅ are connected to the gates are connected to the FETs Q ₁₁ and Q _21. And F
FE whose current path including ETQ ₁₆ and Q ₂₆ is connected to the gate
TQ ₁₃ and Q ₂₃ are connected to the FETs Q ₁₂ and Q ₂₂ , respectively.

Furthermore, the gates of the FETs Q _17, Q ₂₇ to the current path including the FETs Q _15, Q ₂₅ is, in the current path including the FETs Q _16, Q ₂₆ gates of the FETs Q _18, Q ₂₈ are connected respectively. One end of the FETs Q ₁₇ and Q ₂₇ to the gates of FETs Q _33, one end of the FETs Q ₁₈ and Q ₁₈ are connected to the gates of the FETs Q _34, the output terminal of the circuit, FETQ _33, Q ₃₄ and the level shift diode group It is composed of The gates of the Q ₂₉ of FETs Q ₁₉ are connected to each other.

It should be noted that only the positive-phase data signal D is
_20, to the gate of Q ₃₀ is applied as a control signal for the multiplexer. The FET pair Q ₁₉ -Q ₂₀ , Q ₃₁ -Q
_32, Q ₂₉ -Q ₃₀ and _{FETQ 15, Q 16, Q 25} , Q 26,
Q _33, Q ₃₄ has a respective current source configured by FETs Q ₃₅ to Q ₄₃ independently.

[0038] In the circuit configured as described above, the voltage controlled oscillator output VCO, FETs Q ₁₁ by VCO ^* -
When either one of Q _21, Q ₁₂ -Q ₂₂ is conductive, one of which conducts one of _{FETQ 16 -Q 26, Q 15 -Q} 25 accordingly. Further, when one of the FETs Q ₁₆ -Q ₂₆ and Q ₁₅ -Q ₂₅ becomes conductive, the FETs Q ₁₃ -Q ₁₈ -Q ₂₃ -Q ₂₈ , Q
_{One of 14} -Q ₁₇ -Q ₂₄ -Q ₂₇ conducts. Here, each FET pair Q ₁₃ -Q ₁₄ , Q ₁₇ -Q ₁₈ , Q ₂₁ -Q ₂₂ and each FET pair Q ₁₁ -Q ₁₂ , Q ₂₃ -Q ₂₄ , Q ₂₇ -Q ₂₈ are data signals D, D ^* FE
TQ ₃₃ and Q ₃₄ are alternatively turned on. That is, the voltage controlled oscillator output VCO, VCO ^* is latched data signal D, the D ^*, further, the data signal D, is output in accordance with D ^*. Therefore, complementary phase comparison outputs are obtained at the outputs PD and PD ^* .

FIG. 11 is a diagram showing a specific configuration example of the phase comparator when the D-type flip-flop shown in FIG. 10 is used.

As shown in the figure, this circuit has a two-stage configuration of a circuit A and a circuit B having the same configuration.
Circuit A inputs are voltage controlled oscillator outputs VCO, VCO
^* , And the input of the circuit B receives the output of the circuit A. The input terminal of the circuit A (B) has a pair of FETs Q ₁₁ -Q ₁₂ (Q ₂₁ -Q ₂₂ ) receiving the input signal at the gate and a pair of FETs Q ₁₉ receiving the clock signals CK, CK ^* at the gate.
−Q ₂₀ (Q ₂₉ −Q ₃₀ ). In addition, F
ET vs. Q ₁₉ -Q ₂₀ (Q ₂₉ -Q ₃₀ ) and FETs Q ₁₅ , Q
₁₆ (Q _25, Q ₂₆₎ each FETQ ₃₅ ~Q ₃₇ (Q ₃₉ ~
And a current source configured by Q _41).

Further, the gate of the FET Q ₁₄ (Q ₂₄ ) is connected to the current path including the FET Q ₁₅ (Q ₂₅ ) by the FET Q ₁₆ (Q ₂₆ ).
The gate of the FETQ ₁₃ (Q ₂₃₎ is in a current path that includes a are connected. One end of the FETQ ₁₄ (Q ₂₄₎ at one end of the _{FETQ 11 (Q 21), FETQ} 13 (Q 13) at one end is connected to one end of the FETQ ₁₂ (Q _22). Therefore, for example, when the FET Q ₁₁ (Q ₂₁ ) conducts, F
ETQ ₁₆ (Q ₂₆ ) conducts, and at this time the FET Q
₁₃ (Q ₁₃ ) also conducts, so that a complementary output is generated at the output terminal of the circuit A (B). The output terminal of the circuit A (B) is connected to the FETs Q ₁₅ , Q ₁₆ (Q ₂₅ ,
It is connected to one end of the Q _26).

The circuit configured as described above is a typical D-type flip-flop, and its function is as described above with reference to FIG. Therefore, the phase frequency comparison circuit according to the present invention can be used in place of the phase comparison section shown in FIG.

FIG. 7 shows the converter 30 in the circuit shown in FIG.
It is a figure which shows the specific example of.

As shown in FIG. 3, this circuit
Depending on the output PD and PD ^* of the phase comparator 10, the phase comparator
It comprises a pair of latches for latching 40 outputs QPD, QPD ^* , and a NAND gate for performing a NAND operation on the output of each latch and PD, PD ^* . Therefore, FIG.
, The outputs PD and PD ^* of the phase comparator 10 are received in place of the data signals D and D ^* , and the voltage-controlled oscillator output V
Instead of CO and VCO ^* , the output QPD of the phase comparator 40,
Except for receiving QPD ^* , the configuration of the latch circuit portion is common. On the other hand, corresponds to the NAND circuit of Fig. 3, this circuit has a unique configuration in _{FETQ 51 -Q 52, Q 53 -Q} 54 with the relevant portion to the output end of the two pairs.

That is, each FET pair Q ₅₁ -Q ₅₂ , Q ₅₃ -Q ₅₄
Receives the output of each latch circuit at its gate, and outputs
Are selectively enabled by the output PD, PD ^* . Thus, FET pairs Q ₅₁ -Q _52, Q ₅₃ -
From the output of Q _54, are complementary to each other conversion signal TR, TR
^* Is output.

FIG. 8 is a diagram showing a specific example of the configuration of the superposition section.

[0047] As shown in the figure, this circuit, each pair of FETs Q ₆₁ to Q 3 single differential amplifier constituted by ₆₆
And 21, 22, 23, a current source unit 81 which is constituted respectively by FETs Q ₆₇ to Q _69, resistors R ', R _0', the diode group D ₀ '
And a reference voltage generator G composed of an FET Q ₀ ′.

Here, one output of the differential amplifier 22 is coupled to one output of each of the differential amplifiers 21 and 23,
The other outputs of the differential amplifiers 21, 22, 23 are also mutually coupled. Further, each of the differential amplifiers 21, 22, and 23 is a FET Q ₆₇
It is connected to a current source 81 according to Q _69.

The FET Q which is a pair of inputs of the differential amplifier 22
₆₄ and Q _{63 have} outputs PD and P of the phase comparator 10 respectively.
D ^* is applied. Also, the FET Q of the differential amplifier 21
The gates of the FETs Q ₆₆ of the gate and the differential amplifier 23 of the ₆₁ output TR or TR conversion portion 30 ^* is applied. Further, FETs Q ₆₂ and the differential amplifier of the differential amplifier 21
The gates of the FETs Q ₆₅ of 23, a reference voltage by the reference voltage generating unit G is generated is applied. In the superposition circuit configured as described above, the signals PD, PD ^* and the signal TR,
The sum with TR ^* is output as signals Q and Q ^* .

In the reference voltage generator G of the circuit shown in FIGS. 7 and 8, as shown in the figure, the resistance values of the resistors are R ₀ and R ₁ , the anode width of the diode is D ₀ , and the gate of the FET is the gate. When the width is Q ₀ , Q ₀ ′, D ₀ ′ and R ₀ ′ are manufactured so as to satisfy the following formulas 1 and 2, respectively. A stable reference voltage can be generated.

[0051]

[Formula 1] Q ₀ ′ = nQ ₀ , D ₀ ′ = nD ₀ , R ₁ ′ = (1 / n) R ₁

[0052]

[Equation 2] _{R 0 '· I 0' =} R 0 · I 0 + R 0 I 1/2

[0053]

As described above, in the phase frequency comparison circuit according to the present invention, it is not necessary to separately provide a circuit for extracting a clock component from a data signal in a phase locked loop for a clock data circuit. Also, a charge pump circuit is not required between the charge pump circuit and the loop filter. Therefore, it can be advantageously used particularly in a GaAs MESFET integrated circuit in which a charge pump is difficult to configure.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic configuration of a phase frequency comparison circuit according to the present invention.

FIG. 2 is a circuit diagram of the circuit shown in FIG.
3 is a diagram for explaining a configuration example and operation of a circuit that can be used as 40. FIG.

FIG. 3 is a diagram for explaining a configuration and operation of a circuit that can be used as a conversion unit 30 in the circuit shown in FIG. 1;

FIG. 4 is a diagram for explaining the configuration and operation of a circuit that can be used as the superposition unit 20 in the circuit shown in FIG.

FIG. 5 is a diagram showing an output signal of the phase frequency comparison circuit shown in FIG. 1;

FIG. 6 is a diagram illustrating a specific configuration example of a circuit that can be used as a phase comparison unit.

FIG. 7 is a diagram illustrating a specific configuration example of a circuit that can be used as a conversion unit.

FIG. 8 is a diagram showing a specific configuration example of a circuit that can be used for superposition.

FIG. 9 is a diagram showing a typical configuration of a conventional phase frequency comparison circuit.

FIG. 10 is a diagram for explaining a function of a phase comparison unit configured using a D-type flip-flop.

FIG. 11 is a diagram illustrating a specific configuration example of a phase comparison unit illustrated in FIG. 10;

[Description of Signs] 10, 40: Phase comparison unit, 20: Overlapping unit, 30: Conversion unit, 50: Phase shifter, 21, 22, 23: Differential amplifier

Claims (1)

(57) [Claims] A first phase comparison section for receiving a reference signal of a predetermined frequency generated by a voltage controlled oscillator and a data signal based on a predetermined clock signal;
A phase shifter that shifts by 90 degrees, a second phase comparison unit that receives the output of the phase shifter and the data signal, and the first and second
Comprising of a converter for converting the frequency comparison output a phase comparison output of the phase comparator, and a superposition unit that outputs the sum thereof receiving the outputs and the conversion unit of the phase comparison unit, further, The conversion unit controls an output of the first phase comparison unit to a control terminal.
Receiving the output of the second phase comparison unit at the input terminal
First and second latches, the output of the first latch and the
A first NAND receiving an output of the first phase comparison unit;
2 and the output of the first phase comparator
And a second NAND, wherein the first and second NAND
Whether the output is the phase comparison output of the first and second phase comparison units
Output as frequency comparison output extracted from
Phase frequency comparator circuit, characterized in that they are.