JP3201221B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a vertical MOS (Metal Oxide Si).
licone).

[0002]

2. Description of the Related Art Conventionally, as a manufacturing method of this kind, FIG.
As shown in FIG. 5, n / n ⁺ epi (100), specific resistance of 0.6 to 2.0 (Ω · cm) and epi thickness of 10 μm are used, and boron (Boron) is used for the base region 3. Is implanted under the conditions of a dose of 7 × 10 ¹³ cm ⁻² and an acceleration voltage of 100 keV, and is diffused to have a diffusion length of 2 μm.

In addition, arsenic is implanted into the n ⁺ source region 4 at a dose of 2 × 10 ¹⁵ cm ⁻² , an acceleration voltage of 40 keV, with the source contact portion masked, and a diffusion length of 0.4.
It is diffused to be μm.

The vertical groove 14 is formed by RIE (Reactive).
Ion Etching), using a mixed gas of SF6 + CCl4, and etching at a pressure of 100 mTorr until a depth of 4 μm is reached. Further, light wet etching for removing a contaminated layer and a damaged region in the gate portion is added (see FIG. 4A).

After a gate oxide film 13 is grown thereon by 650 °, polysilicon 6 is deposited under reduced pressure CVD (Chem).
An oxide film 13 is grown on the surface of the polysilicon 6 thinly after growing 5000 ° by an ideal vapor deposition (see FIG. 4B).

Subsequently, a second polysilicon 15 for filling the vertical groove 14 is grown to a thickness of 2.0 μm to completely fill the vertical groove 14 [see FIG. 4C]. The polysilicon 15 in a region other than the groove 14 is removed [see FIG. 5A]. Here, the first
The thin oxide film 13 on the polysilicon 6 has a role of a stopper for over-etching the first polysilicon 6.

After patterning of the gate electrode 6, a PSG (phospho) having a phosphorus concentration of 8% is formed as an interlayer insulating film 7.
(Silicate Glass) film is grown at 5000 ° C. and reflowed at 100 ° C. in an atmosphere of H 2 + O 2 to improve the step coverage (see FIG. 5B).

After the contact holes are formed, DC magnetron sputtering (Direct Current Ma) is performed.
2 μm by g.
Deposit m of Al-Si-Cu8 to form source and gate electrodes [see FIG. 5 (c)]. A plasma SiN film is used as a passivation film (not shown) on the surface.

The method of manufacturing the above semiconductor device is described in "Ultra Low Ion Resistance RMOSFET" (by Daisuke Ueda et al., National Technical Repo).
rtVol. 32, no. 2, Apr. 1986).

[0010]

In recent years, cost reduction has been demanded for semiconductors as a whole, and it is important to realize the semiconductors in the same number of steps as long as the semiconductors have the same structure.

In the above-described conventional method for manufacturing a semiconductor device, a patterning step is required because a portion that is in contact with the base layer is masked when the source region is formed. Can not.

In order to solve this problem, a method of forming a source region on the entire surface of a substrate and etching silicon up to a base layer when forming a contact is also conceivable. However,
If you try to etch silicon down to the base layer, the polysilicon of the gate electrode will be etched together,
The contact to the base layer must be formed separately from the contact of the gate electrode, or the size and depth of the gate electrode must be such that they do not interfere with etching.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device which solves the above-mentioned problems and which can reduce the number of steps in manufacturing a semiconductor device having the same structure and reduce costs. It is in.

[0014]

A method of manufacturing a semiconductor device according to the present invention comprises the steps of: forming a base layer over the entire surface of a semiconductor silicon substrate; forming a source layer over the entire surface of the base layer; and a step of forming an inner wall surface and the respective gate insulating film of the surface with the grooves of the source layer to form a <br/> groove penetrating through the base layer, edge of the silicon
A step of embedding a gate electrode made of a material having a high selectivity in the trench, a step of forming an interlayer insulating film on the gate insulating film and the gate electrode, the step of forming the interlayer insulating film, the gate insulating film, and the semiconductor Forming a contact hole to the base layer and a contact hole to the gate electrode by etching a silicon substrate.

Another method of manufacturing a semiconductor device according to the present invention includes, in addition to the above-described structure, a step of implanting boron into the entire surface of the semiconductor silicon substrate after forming the contact hole.

[0016]

[0017]

[0018]

A base layer is formed on the entire surface of a substrate, a source layer is formed thereon, and a vertical groove is formed through the base layer and the source layer. A gate insulating film is formed.

A material for the gate electrode is laminated on the gate insulating film to fill the vertical groove to form a gate electrode. An interlayer insulating film is laminated on the gate insulating film and the gate electrode, and then the base layer and the base layer are etched. A contact hole to the gate electrode is formed.

This eliminates the need for a step of masking and patterning a portion in contact with the base layer when forming the source region, thereby reducing the number of patterning steps using a photomask to four.

Therefore, it is possible to reduce the number of steps in manufacturing a semiconductor device having the same structure. At the same time, the number of glass masks used in the patterning process can be reduced,
Costs can be reduced.

In this case, since aluminum or the like having a high selectivity to silicon is used for the gate electrode, even when silicon is etched to the base layer, it is not etched together with silicon. Therefore, it is not necessary to form a contact hole up to the base layer separately from the contact hole of the gate electrode, and it is not necessary to make the size and depth of the gate electrode a size that does not hinder the etching.

[0023]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIGS. 1 and 2 are cross-sectional views showing the steps of manufacturing a semiconductor device according to an embodiment of the present invention. The manufacturing process of the semiconductor device according to one embodiment of the present invention will be described with reference to FIGS.

N ⁺ substrate 1 (100) [resistivity 0.002
~0.006 (Ω · cm)] in N ^- epi 2 [specific resistance 0.
Using a wafer having a thickness of 6 to 1.0 (Ω · cm) and a thickness of 8 μm], boron is implanted into the entire surface to obtain a diffusion depth of 1.5.
A heat treatment is performed to a thickness of about 2.0 μm to form the base layer 3. After that, arsenic is implanted into the entire surface and heat treatment is performed so that the diffusion depth becomes 0.4 to 0.6 μm, thereby forming the source layer 4 (see FIG. 1A).

After the source layer 4 is formed, a vertical groove is formed by ion etching so as to have a depth reaching the N ^- epi 2 through the N ⁺ source 4 and the P base 3. A gate oxide film 5 is grown thereon, and aluminum is further stacked thereon. The laminated aluminum is buried in the vertical groove by heat treatment to form the gate electrode 6 [FIG.
(B) and FIG. 1 (c)].

After laminating the interlayer insulating film 7 on the gate oxide film 5 and the gate electrode 6, a contact hole reaching the base layer 3 and the gate electrode 6 is formed by ion etching [see FIG. 2 (a)]. . In this case, since the gate electrode 6 is made of aluminum having a high selectivity to silicon, that is, aluminum having an etching rate having a large difference from the etching rate of silicon, the gate electrode 6 can be formed even when a contact hole is formed by etching silicon. 6
Is not etched.

A wiring aluminum 8 is laminated by aluminum reflow sputtering so as to fill these contact holes, and after patterning the wiring aluminum 8, a SiN film is laminated as a passivation film 9 (see FIG. 2B).

According to the above-described manufacturing method, patterning using the photolithography technique is performed only four times, so that the manufacturing process of the semiconductor device can be shortened and the number of masks used for patterning can be reduced.

Since there is almost no step on the surface before the interlayer insulating film 7 is formed, it is not necessary to perform reflow by heat treatment after the formation of the interlayer insulating film 7. In addition, since high-temperature heat treatment such as activation of impurities and reflow of the interlayer insulating film 7 is not required after the formation of the gate electrode 6, a low-melting-point metal such as aluminum can be used as a material for the gate electrode 6. The use of aluminum for 6 makes it possible to significantly reduce the gate resistance as compared with polysilicon. In addition, as a material of the gate electrode 6, W, Ti, or the like can be used in addition to aluminum.

FIG. 3 is a cross-sectional view showing the steps of manufacturing a semiconductor device according to another embodiment of the present invention. A manufacturing process of a semiconductor device according to another embodiment of the present invention will be described with reference to FIG.

In another embodiment of the present invention, after the gate oxide film 5 is grown, polysilicon 10 is laminated, phosphorus diffusion is performed, WSi is laminated, vertical grooves are filled, and the gate electrode (poly) is etched back. A silicon (silicon) 10 and a gate electrode (WSi) 11 are formed (see FIG. 3A).

The gate oxide film 5 and the gate electrode 1
After laminating the interlayer insulating film 7 on 0 and 11, a contact hole reaching the base layer 3 and the gate electrode 11 is formed by ion etching. After that, by implanting boron into the entire surface, the P ⁺ diffusion region 12 is formed in the base layer 3, so that the contact resistance with the base layer 3 can be reduced (see FIG. 3B). At this time, boron is also implanted into the contact portion of the contact hole reaching the gate electrode 11, but is not affected by boron because the surface of the gate electrode 11 is WSi.

A wiring aluminum 8 is laminated so as to fill these contact holes, and after patterning the wiring aluminum 8, a SiN film is laminated as a passivation film 9 (see FIG. 3C). Thus, even in the above-described manufacturing method, the number of times of patterning using the photolithography technique is reduced, so that the manufacturing process of the semiconductor device can be shortened and the number of masks used for patterning can be reduced.

As described above, after forming the base layer 3 and the source layer 4 on the entire surface of the substrate, a vertical groove penetrating the base layer 3 and the source layer 4 is formed, and the surface of the source layer 4 and the surface and side of the vertical groove are formed. A gate insulating film 5 is formed on each of the wall surfaces, and the materials of the gate electrodes 6, 10, and 11 are stacked on the gate insulating film 5 to fill the vertical grooves to form the gate electrodes 6, 10, and 11, and the gate insulating film is formed. Film 5 and gate electrode 6,
By laminating the interlayer insulating film 7 on the layers 10 and 11 and forming contact holes to the base layer 3 and the gate electrodes 6 and 11 by etching, a portion to be in contact with the base layer 3 when forming the source region is masked. Therefore, the patterning step using a photomask can be reduced to four steps.

Therefore, the number of steps can be reduced in manufacturing a semiconductor device having the same structure. At the same time, the number of glass masks used in the patterning step can be reduced, so that the cost can be reduced.

In this case, since aluminum or the like having a high selectivity with respect to silicon is used for the gate electrodes 6 and 11, even when silicon is etched to the base layer 3, it is not etched together with silicon. Therefore, it is not necessary to form a contact hole up to the base layer 3 separately from the contact holes of the gate electrodes 6 and 11, and it is also necessary to make the size and the depth of the gate electrodes 6 and 11 such that they do not hinder the etching. Absent.

[0038]

As described above, according to the present invention, a groove penetrating the base layer and the source layer formed on the entire surface of the substrate is formed, and a gate insulating film is formed on the surface of the source layer, the surface of the groove, and the side wall surface, respectively. After forming the film, the gate electrode material is laminated on the gate insulating film, and the trench is buried to form the gate electrode, and after the gate insulating film and the interlayer insulating film are laminated on the gate electrode, the interlayer insulating film and the gate insulating film are formed. By forming the contact holes to the base layer and the gate electrode by etching the film, the number of steps can be reduced in manufacturing a semiconductor device having the same structure, and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of each step showing a step of manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 2 is a cross-sectional view of each step showing a step of manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 3 is a cross-sectional view of each step showing a step of manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 4 is a cross-sectional view of each step showing a step of manufacturing a semiconductor device according to a conventional example.

FIG. 5 is a cross-sectional view of each step showing a step of manufacturing a semiconductor device according to a conventional example.

[Explanation of symbols]

Reference Signs List 3 base layer 4 source layer 5 gate oxide film 6 gate electrode 7 interlayer insulating film 8 wiring aluminum 9 passivation film 10 gate electrode (polysilicon) 11 gate electrode (WSi) 12 P ⁺ diffusion region

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/78 653 H01L 29/78 652 H01L 21/768

Claims (5)

(57) [Claims] A step of forming a base layer over the entire surface of the semiconductor silicon substrate, a step of forming a source layer over the entire surface of the base layer, and forming a groove penetrating the source layer and the base layer. a step of to form the respective gate insulating film on the inner wall surface and the groove of the source layer, edge of the silicon
A step of embedding a gate electrode made of a material having a high selectivity in the trench, a step of forming an interlayer insulating film on the gate insulating film and the gate electrode, the step of forming the interlayer insulating film, the gate insulating film, and the semiconductor Forming a contact hole to said base layer and a contact hole to said gate electrode by etching a silicon substrate. 2. The method according to claim 1, wherein the gate electrode is made of aluminum and W.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the method comprises one of Ti and Ti . 3. The method according to claim 2, further comprising the step of implanting boron into the entire surface of the semiconductor silicon substrate after forming the contact hole. 4. A large etching selectivity with silicon.
The material comprising the step of laminating on the gate insulating film, wherein
4. The method of manufacturing a semiconductor device according to claim 1, wherein a material is melted by heat treatment and embedded in the groove. 5. A step of forming polycrystalline silicon on an inner wall surface of the groove, wherein the step of embedding the gate electrode in the groove includes embedding WSi on the polycrystalline silicon formed on the inner wall surface of the groove. Claims characterized in that :
The method for manufacturing a semiconductor device according to claim 1 .