JP3201223B2 - Plasma processing method and apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma processing method and apparatus, and more particularly to a plasma processing method and apparatus suitable for processing using a bias applied to a sample.

[0002]

2. Description of the Related Art FIG. 11 shows a conventional example of an RF bias.
The sample 1 is placed on a sample stage 2, and the high frequency power shown in FIG. 12 is output from the high frequency power supply for bias 3, and a sine wave voltage is applied via a capacitor 4. Into the processing chamber 5, the processing gas is exhausted while flowing in, and the coil 7 and the insulator 8
The plasma is generated by the high frequency power applied via the. Since the amount of electrons supplied from the plasma to the sample is several tens to several hundred times larger than the amount of positive ions, negative charges are accumulated on the sample 1 side of the capacitor 4. Due to this charge, a negatively shifted voltage appears on the substrate as shown in FIG. This negative voltage accelerates positive ions as an etching species, and vertically enters the sample 1 to enable vertical etching. However, with the miniaturization of the sample pattern, various problems described below have arisen due to the charge-up of positive charges at the bottoms of the grooves and holes.

[0003]

In the sample surface potential waveform shown in FIG. 13, the peak potential is almost equal to the plasma potential (V).
Since the peak of the positive voltage for accelerating the electrons in the positive cycle in which the electrons are incident on the sample becomes almost zero, the electrons are hardly accelerated and enter the substrate. Since the capacitance component on the sample surface is zero or a large value, the sample surface potential is generally substantially equal to the sample potential.

When a fine pattern is processed using such a bias application method, a local charge-up occurs in a sample. Ions are accelerated and vertically incident on the sample, so they reach the bottom of the fine pattern.On the other hand, electrons are not accelerated and are incident on the sample isotropically. No (electron shading phenomenon). Therefore, the side surface of the fine pattern is charged up negatively and the bottom surface is positively charged up.

The charge-up due to the electron shading causes various adverse effects in plasma etching. One of the most serious problems is local abnormal side etch (notch) in gate polysilicon processing.
Is the occurrence of

[0006] Charge up due to the electron shading phenomenon also occurs in the processing of metal wiring, causing damage to the gate oxide film. Positive charges generated on the bottom of the fine pattern by electron shading are collected on the floating gate connected to the metal wiring,
Damage such as dielectric breakdown occurs in the gate insulating film between the floating gate and the substrate silicon.

[0007] In addition, the charge-up due to the electron shading phenomenon is also a problem in the etching of fine holes such as trenches and contact holes, and causes abnormal shapes such as subtrench and bowing. As in the case of etching the polysilicon, the side of the hole is negatively charged and the bottom of the hole is positively charged. Due to this charge-up, the trajectory of ions serving as etching species is bent, and the ions enter the side surface of the hole or the end of the hole bottom. For this reason, the side surface of the hole and the end of the bottom surface of the hole are etched, and an irregular shape such as a bowing or a subtrench occurs.

As one method for solving this problem, Japanese Patent Application Laid-Open No. 6-61182 discloses a plasma potential (V
By applying a pulse voltage having an amplitude (approximately 20 volts) of the difference between p) and the floating potential (Vf) and providing a longer period in which the sample surface potential (Vs) becomes equal to the plasma potential (Vp), It describes that electrons are incident on a sample to neutralize charges on the surface of the sample. However, since the acceleration energy of the electrons incident on the sample is zero, there is a disadvantage that the neutralization by the electrons is not sufficiently performed at the deep groove / hole or at the bottom of the fine pattern.

The present invention solves various problems such as notch, charge-up damage, bowing, subtrench, microloading, and reduction in etching rate in the hole depth direction caused by the electron shading phenomenon.

An object of the present invention is to provide a plasma processing method and apparatus which can improve the controllability of the shape of a fine pattern and the reduction of the etch rate in a deep groove / deep hole to obtain a desired etching shape. is there.

[0011]

In a plasma processing method for converting a gas into a plasma under reduced pressure and processing a sample placed in a processing chamber using the plasma, a pulse width is set to τw,
The pulse period is T, the pulse amplitude is Vpls, and the plasma potential is
The Shall Vp, the DC component of the voltage applied to the sample and V _DC
Then , the sample is placed with a pulse bias voltage having a positive potential that satisfies 0.001 <(τw / T) <0.05 and Vp−V _DC +5 volts <Vpls .
To the mounting means via a capacitive component,
Accelerates the electron beam and makes it incident on the sample, and the fine pattern on the sample surface
This is achieved by preventing the positive charge from being charged up on the bottom surface of .

[0012]

In the present invention, there is a period in which a pulse bias voltage is applied to the sample, the surface potential (Vs) of the sample is set to a value at least 5 volts higher than the plasma potential (Vp), and electrons are accelerated and incident on the sample. As a result, the accelerated electrons can reach the bottom of the fine pattern on the sample surface, prevent charge-up of positive charges on the bottom, prevent notches, etc., and reduce the processing speed in deep grooves / holes. A decrease or the like can be prevented.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a configuration diagram showing an electrode portion to which a bias voltage is applied in the plasma processing apparatus of the present invention.
The electrode portion in this figure is provided, for example, in place of the sample stage portion of the conventional apparatus shown in FIG. In this figure, the same symbols as those in FIG. 11 indicate the same members. In this embodiment, a bias pulse power supply 3 'shown in FIG. 1 is used in place of the bias high frequency power supply 3 of the conventional plasma processing apparatus shown in FIG. The bias pulse power supply 3 'periodically outputs positive-direction pulses as shown in FIG. When this pulse is applied to the sample 1 via the capacitance component 4, a sample surface potential (Vs) as shown in FIG. As shown in this figure, at the portion of the pulse width (τw) where the potential of Vs rapidly increases, the value of Vs becomes higher than the plasma potential (Vp) +5 volts, and electrons are accelerated and incident on the sample. Here, τw is the pulse width, T is the pulse period, Vpls is the pulse amplitude, Vp is the plasma potential, and _VDC is the sample 1
Is the DC component of the voltage applied to

FIG. 3 (a) / (b) / (c) shows the change of V _DC / electron acceleration voltage / acceleration electron ratio when the pulse period T is changed while τw and Vpls are predetermined values. Show. FIG. 3 shows that the pulse amplitude (Vpls) is almost Vp (2
0 volts), and the (τw / T) dependency when the electron acceleration voltage is almost zero is also shown by the broken line graph.

When (τw / T) <0.001, _VDC is almost 0 volt, and the accelerating electron ratio is about 0.1 or smaller. The charge-neutralizing effect is greater when the acceleration electron ratio is closer to 1.0 and the electron acceleration voltage is higher. From FIG. 3 (c), when (τw / T) is about 0.001 or less, the ratio of the accelerated electrons is reduced, and the effect of electron acceleration is hardly obtained. Further, the region where V _DC > −5 volts is a region that is not practically preferable because it is difficult to obtain a vertical shape due to insufficient ion acceleration and the etching rate is low. However, when the highest priority is given to the high selection ratio and the low damage, the upper limit of _VDC need not be considered.

In the region where V _DC <Vp−Vpls + 5, since the electron acceleration voltage is 5 V or less, electrons hardly reach the bottom of the deep groove or the deep hole. For this reason, it is a region where it is difficult to improve the shape due to electron acceleration or to reduce the etching rate in deep grooves / holes. When (τw / T) increases, the electron acceleration voltage rapidly decreases as shown in FIG. The region where the accelerating voltage is 5 volts or more varies depending on the type of plasma (electron temperature, electron density, type of ions, etc.), but generally (τw / T) <0.1, preferably (τw / T).
T) <0.05. Therefore, the portion where the preferable characteristics are obtained is a portion where −5 volt> V _DC > Vp−Vpls + 5 volts 0.05> (τw / T)> 0.001. This corresponds to the portion shown by the thick line in FIG. In the case indicated by the broken line in FIG. 3A, there is no desired area.

The average electron acceleration energy during the period when the electron current flows into the sample 1 is almost proportional to Vpls−Vp + _VDC , and when this value is 5 volts or more, the charge neutralizing effect at the deep hole or the bottom of the groove appears. Thus, when the value is 10 volts or more, the above effect becomes remarkable.

When the value of Vpls-Vp + _VDC is about 200 volts or more, adverse effects such as abrasion of the resist film and an increase in damage become remarkable.

The absolute value of Vp-V _DC is almost proportional to the average energy of ion acceleration. Vpls−Vp + V _DC
Is optimized in accordance with the material of the sample, the pattern, the aspect ratio of the hole, etc. within the range of the preceding values.

In the basic pulse shown in FIG.
By optimizing ls, (τw / T), and the like, the electron acceleration voltage and the ion acceleration voltage can be set to desired values. However, as shown in FIG. The range is small. The small range of (τw / T) is limited by the small absolute value of _VDC . To improve this, alternating current with a shorter cycle than the pulse cycle,
A pulse train having a large (τw / T) may be superimposed in a short cycle, and the minimum value of the absolute value of _VDC may be set by the superimposed wave.

FIG. 4 shows an example in which an AC having an amplitude Vrf and a pulse having an amplitude Vpls are superimposed. V _{DC at} this time
The − (τw / T) characteristic is as shown in FIG.
By setting Vrf> 5 + Vp volts, (τ
Even in a region where w / T) is small, V _DC <−5 volts, and desired characteristics can be obtained. Note that the minimum value of (τw / T) in the preferable region shown by the thick line in FIG. 4B corresponds to an acceleration electron ratio of about 0.1 or more (see FIG. 3C).

Another method for setting the minimum value of the absolute value of _VDC is shown in FIGS. FIG. 5A shows the amplitude Vrf.
This is an example in which a pulse is superimposed near the maximum peak of the alternating current (100 kHz-100 MHz) every n cycles of the alternating current.

FIG. 5B shows an alternating current (100 kHz-10
This is an example in which the amplitude of 0 MHz is changed at regular intervals. FIG. 6 shows details in the vicinity of the sharp increase in the amplitude. FIG. 6A shows the output voltage of the pulse bias power supply 3 ′, and FIG.
Shows the surface potential pressure (Vs) of the sample 1, (c) shows the outline of the electron current and ion current at each time, and (d) shows the outline of the electron acceleration voltage.

At the portion of the maximum voltage where the amplitude increases sharply, the sample surface potential (Vs) becomes Vp + 5 volts or more, and electrons are accelerated and enter the sample. Therefore, the accelerated electrons can reach the bottom of the fine pattern on the sample surface,
It is possible to prevent the charge up of the positive charges on the bottom surface, thereby preventing the occurrence of notches and the like, and to prevent the processing speed from decreasing in deep grooves / holes. In the case where the absolute value of _VDC is limited by superimposing an AC or a pulse train, as shown in FIGS. 6B and 6D,
As a value of Vs, with a period of Vp + 5 volts or more,
There is a period near Vp below Vp + 5 volts.

By the way, the above-described pulse bias method has a drawback that the average of the ion acceleration voltage fluctuates in one cycle as shown in FIGS. 6 (b) and 7 (b). FIG. 8 shows an example in which the voltage of the sample stage is clamped to improve this.

A high-speed diode 10 and a capacitor 11 for holding a set voltage are used.
1 is connected to a clamp power supply to clamp a decrease in the average value of the ion acceleration voltage to a predetermined voltage. When the basic pulse shown in FIG.
Vclamp is Vclamp = V _DC −v (v is 0
-10 volts). In this case, as shown in FIG. 8B, the capacitance component (C
Since the capacitance component (Cs) on the sample surface is much larger than that of (0), the change in the sample surface potential (Vs) due to ion incidence can be significantly reduced by clamping the voltage on the sample stage. When the waveform shown in FIG. 5B whose amplitude changes periodically is used, the clamp voltage Vcla is used.
mp, Vclamp = V _DC -Vrf-v (v is 0
8 to 10 volts) as shown in FIG.
The same effect as in (b) is obtained.

If a capacitance component (Ce: for example, the capacitance of the electrostatic attraction film) exists between the sample 1 and the sample stage 2 and the value is much smaller than Cs, the value is shown in FIG. In addition, the method of clamping the sample stage is less effective. In this case, as shown in FIG. 9, an electrode which is in direct contact with the sample 1 is provided, a capacitor 12 for holding a set voltage is connected to the electrode via a high-speed diode 10, and furthermore, via an inductance Lcl for filter. If the power supply is connected to a clamp power supply, the same effect as in FIG. 8 can be obtained.

[0028] In the conventional plasma, 0.01μs <τw <10μs preferably, 0.01μs <τw <0.5μs 0.001 < (τw / T) <0.1 , preferably 0.001 <( τw / T) <0.05 Vp + 10 volts <Vpls− 5 volts > V _DC > Vp−Vpls + 5 volts Vp is about 10 to 20 volts In this embodiment, the case where plasma is generated by inductively coupled high frequency has been described. Can be commonly applied to, for example, microwave plasma, plasma by high frequency and DC magnetic field, and ECR plasma, regardless of the plasma generation method.

The output waveform of the bias pulse power supply 3 'is not limited to the waveform shown in FIG.
The surface potential (V) of the sample is also shown in FIGS. 4 and 5 in which the alternating current is superimposed, the alternating current is varied, or a plurality of pulses shown in FIG.
The present invention can be similarly applied if the sum (τw) in one cycle of the electron acceleration period and its cycle (T) satisfy the above-mentioned conditions when s) becomes higher than the plasma potential (Vp) by 5 V or more.

According to the present embodiment, the sample is provided with a pulse bias power supply for accelerating electrons of 5 V or more, and the DC component V _{DC and} (τw / T) of the voltage applied to the sample are calculated as follows: −5 volts> V _DC > Vp−Vpls + 5 volts 0.001 <(τw / T) <0.1, the electrons are accelerated at a potential of 5 volts or more to neutralize the charge-up of positive charges on the bottom of the fine pattern, Notch generation, micro loading,
It is possible to prevent a decrease in the etch rate in the deep groove / hole, and to set the ion acceleration voltage to a predetermined value or more, thereby preventing a decrease in the etch rate and a decrease in the directionality of ions. As a result, the charge neutralization at the groove bottom / hole bottom by the accelerated electrons is efficiently performed, and the shape controllability of the fine pattern and the deep groove /
The etch rate in deep holes can be reduced.

[0031]

According to the present invention, a bias voltage having a portion where the positive potential sharply increases at predetermined intervals is applied to the sample mounting means, and a potential difference exceeding at least 5 volts near the sharp increase of the voltage is applied. By accelerating the electrons in the plasma to impinge on the sample and neutralizing at least a part of the surface charge of the sample, the charges are efficiently neutralized at the groove bottom / hole bottom by the accelerated electrons. Since the shape controllability of the fine pattern and the decrease in the etch rate in the deep groove / deep hole are improved, it is possible to improve the controllability of the shape of the fine pattern and the decrease in the etch rate in the deep groove / deep hole. effective.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of an electrode unit used in a plasma processing apparatus of the present invention.

2 is a diagram showing an output waveform of a bias pulse power supply of the apparatus of FIG. 1 and a bias voltage waveform applied to a sample.

FIG. 3 shows the relationship between V _DC / electron acceleration voltage / acceleration electron ratio (τw /
T) is a diagram showing dependence.

FIG. 4 is a diagram showing output waveforms of another embodiment of the bias pulse power supply of the apparatus of FIG. 1;

FIG. 5 is a diagram showing output waveforms of another embodiment of the bias pulse power supply of the apparatus of FIG. 1;

6 is an operation explanatory diagram when the output waveform of the bias pulse power supply of FIG. 5B is used.

FIG. 7 is an operation explanatory diagram when the output waveform of the bias pulse power supply of FIG. 5B is used.

8 is a circuit configuration diagram showing a clamp circuit of the device of FIG.

FIG. 9 is a circuit diagram showing a clamp circuit of the device of FIG. 1;

FIG. 10 is a circuit configuration diagram showing a clamp circuit of the device of FIG. 1;

FIG. 11 is a view showing a conventional plasma processing apparatus.

FIG. 12 is a diagram showing the diameter of the output of the bias high-frequency power supply in FIG. 11;

FIG. 13 is a diagram showing a bias voltage waveform applied to the sample in FIG. 11;

[Explanation of symbols]

1 ... sample, 2 ... sample stage, 3 ... high frequency power supply for bias,
3 ': pulse power supply for bias, 4: capacitance element, 5: processing chamber, 6: high frequency power supply for plasma generation, 7: coil, 8 ...
Insulator, 10 high-speed diode, 11 capacitor for holding set voltage.

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-6-61182 (JP, A) JP-A-2-301141 (JP, A) JP-A-4-357829 (JP, A) JP-A-1- 100923 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/3065 C23F 4/00 H05H 1/46

Claims (2)

(57) [Claims] 1. A plasma processing method for converting a gas into a plasma under reduced pressure and processing a sample placed in a processing chamber using the plasma, wherein the pulse width is τw, the pulse period is T, and the pulse amplitude is Vpl.
s, the plasma potential is Vp, and the voltage applied to the sample is
When the DC component is V _DC , the sample is loaded with a pulse bias voltage of a positive potential that satisfies 0.001 <(τw / T) <0.05 and Vp−V _DC +5 V <Vpls.
Applying via a capacitance component to the mounting means for mounting , the electrons in the plasma are accelerated and incident on the sample, and the sample table
Of positive charge at the bottom of
A plasma processing method characterized in that the plasma processing is prevented . 2. A sample mounting means, a processing chamber containing the sample mounting means, a means for supplying gas into the processing chamber, a means for exhausting the processing chamber, and a plasma in the processing chamber. Means for generating a pulse via;
And a means for applying a pulse voltage.
The pulse bias voltage is τw in pulse width and pulse period.
Is T, the pulse amplitude is Vpls, and the plasma potential is
When Vp and the DC component of the voltage applied to the sample are V _DC , 0.001 <(τw / T) <0.05 and Vp−V _DC +5 V <Vpls are satisfied. Into the sample
A plasma processing apparatus characterized in that the potential is set to a positive potential having an acceleration period .