JP3201368B2 - Semiconductor integrated circuit and test method therefor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and a test method therefor, and more particularly to a method for recording a test result of a semiconductor integrated circuit such as a so-called one-chip microcomputer.

[0002]

2. Description of the Related Art A semiconductor integrated circuit has a relatively high reject rate due to various causes in the manufacturing process as compared with other products. Also, the locations where defective products occur are relatively often the same on different wafers. Therefore, it is useful to test the semiconductor integrated circuit and manage the test result in accordance with the position on the wafer from the viewpoint of improving the yield.

FIG. 5 shows a process of testing and assembling a semiconductor integrated circuit conventionally applied. As shown
When a plurality of circuits are formed on one wafer, first, a physical function test of the wafer, that is, whether each semiconductor integrated circuit on the wafer operates normally, is tested. It is stored in the storage device (step S31).

[0004] When it is confirmed by this test that the wafer operates normally, the wafer is scribed and cut into chips (step S32), and further assembled into a product for each chip by packaging (step S33). ). Then, a test is performed to determine whether the electrical characteristics and product specifications are satisfied for each chip in another test device, and the result is stored in an external storage device of the test device (step S34).

In such a conventional method for testing a semiconductor integrated circuit, it is possible to acquire the occurrence of a defect in the test at the wafer stage in step S31 in association with the position on the wafer. However, steps S32 and S33
After that, when assembled into products for each chip, it becomes impossible to recognize where each chip was cut from the wafer. For this reason, it is virtually impossible to manage the defect found in the product test stage of step S34 in association with the position of the chip on the wafer.

Therefore, in order to solve such a problem,
Japanese Patent Application Laid-Open Nos. 60-53043 and 5-347 disclose a semiconductor integrated circuit equipped with a memory in which test results and data relating to the position of a chip in a wafer are written.
No. 350, for example.

[0007]

However, in the semiconductor integrated circuit described in the above publication, a memory irrelevant to the original function has to be mounted, which is disadvantageous in terms of chip area.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and a test of each scribed chip can be performed without mounting a memory unnecessary for its original function on a semiconductor integrated circuit. It is an object of the present invention to enable a result to be managed in accordance with a position of a wafer.

In order to achieve the above object, a semiconductor integrated circuit according to a first aspect of the present invention has a function of writing and erasing information.
A semiconductor integrated circuit equipped with a processing device for performing processing using a program or data written in a nonvolatile memory capable of being deleted , wherein the nonvolatile memory writes information from outside via an external connection terminal The processing device is configured to write product management information including a wafer used for manufacturing the semiconductor integrated circuit in a test stage, a position on the wafer, and a test result.
The programs or data necessary for
A small amount of the product management information written during the test phase
At least part of the data before writing to the nonvolatile memory.
It is characterized by being embedded . Semiconductor integration
In the circuit, the processing unit is required to perform processing.
The program or data is stored on the wafer and the position on the wafer
Erase product management information other than the non-volatile memory
May be written.

In the above semiconductor integrated circuit, product management information is also written in a non-volatile memory in which a program or data used for processing by the processing device is written. For this reason, the test results of each scribed chip can be managed in correspondence with the wafer and the position on the wafer without mounting a memory unnecessary for the semiconductor integrated circuit to realize the original function. Becomes

In order to achieve the above object, a method for testing a semiconductor integrated circuit according to a second aspect of the present invention comprises a nonvolatile memory capable of writing information from outside via an external connection terminal, A method for testing a semiconductor integrated circuit including a processing device for performing processing using a program or data written in a memory, wherein the wafer used for manufacturing the semiconductor integrated circuit is scribed before the wafer is scribed. A wafer test result writing step of writing the test result in the step, and information on the wafer and the position on the wafer to the nonvolatile memory via the external connection terminal, and in a product stage after scribing the wafer. A product test result writing step of writing a test result to the nonvolatile memory via the external connection terminal A program step of writing a program or data used by the processing device to perform processing to the non-volatile memory via the external connection terminal; and a program or data used by the processing device to perform processing. And a program step of writing to the nonvolatile memory via an external connection terminal.

In the above-described method for testing a semiconductor integrated circuit, a test result of the semiconductor integrated circuit, a wafer and a position on the wafer are stored in the nonvolatile memory before the processing device writes a program or data for processing to the nonvolatile memory. Is written. That is, the non-volatile memory for writing the test results and the like can be shared with the memory for realizing the original function of the semiconductor integrated circuit. In addition, by writing the test result and the position on the wafer and the wafer in the nonvolatile memory, even after the semiconductor integrated circuit is scribed from the wafer and separated into chips, each chip is associated with the wafer and the position on the wafer. It becomes possible to manage.

In the method for testing a semiconductor integrated circuit, the nonvolatile memory may be capable of erasing information. In this case, the program step erases at least a part of the information written in the non-volatile memory in the wafer test result writing step and the product test result writing step, and then the processing device performs processing. The program or data to be used for writing to the nonvolatile memory can be written to the nonvolatile memory.

In this case, after information such as test results that become unnecessary after product shipment is erased from the nonvolatile memory,
A program or data for the processing device to perform processing is written therein. That is, the area for writing the test result and the area for writing the program or data for realizing the original function can be shared. Therefore, the capacity of the nonvolatile memory can be small.

In this case, the wafer test result writing step stores the test result at the wafer stage and information on the wafer and its position on the wafer in storage means other than the memory mounted on the semiconductor integrated circuit. Including a writing step, the product test result writing step, the test result at the product stage, in association with the information on the wafer and the position on the wafer,
The method may include a step of writing data in a storage unit other than the memory mounted on the semiconductor integrated circuit. in this case,
The program step may be to write a program or data used for processing by the processing apparatus to the nonvolatile memory without erasing at least a wafer and a position on the wafer.

[0016]

Embodiments of the present invention will be described below with reference to the accompanying drawings. In this embodiment, a case where the present invention is applied to a one-chip microcomputer as a semiconductor integrated circuit will be described.

FIG. 1 is a block diagram showing a circuit configuration of a one-chip microcomputer applied to this embodiment. As shown in the figure, this one-chip microcomputer 1 is used by being incorporated in a mechanical device to be controlled, and has a CPU (Central Processing Unit).
t) 11, ROM (Read Only Memory) 12, EE
PROM (Electric Erasable Programmable Read Only)
Memory) 13 and RAM (Random Access Memory) 1
4 and a peripheral function 15.

The CPU 11 has a ROM 12 or an EEPROM.
This is a processing device that executes a program stored in the OM 13.

The ROM 12 is a nonvolatile memory formed of a mask ROM and in which data cannot be written or erased, and stores a boot program executed first by the CPU 11 when the power is turned on, fixed data, and the like. are doing.

The EEPROM 13 is a nonvolatile memory capable of electrically writing and erasing data. For example, according to an input from the external connection terminal 16, information is written in 1-bit units, and information is stored in 1-byte units. Can be erased. The EEPROM 13 has one chip
In the test of the microcomputer 1 (wafer stage and product stage described later), a wafer, a position on the wafer, and a test result are written as product management information. In the case of a product after the test is completed, a control program for controlling a built-in mechanical device is written in the EEPROM 13.

The RAM 14 is a volatile memory in which data is erased when power supply is stopped.
U11 is used as a work area when executing a program stored in ROM12 or EEPROM13.

The peripheral function 15 is composed of various functions necessary for controlling a mechanical device in which the one-chip microcomputer 1 is incorporated, and includes, for example, a timer and an external communication interface device.

Next, a test apparatus for testing the one-chip microcomputer 1 applied to this embodiment will be described with reference to FIGS. 2 (a) and 2 (b). The one-chip microcomputer 1 is tested at the wafer stage before scribing and at each product after scribing and assembling, and a dedicated test device is applied to each of them.

As shown in FIG. 2A, the wafer test apparatus 2 performs a physical function test in a state where a plurality of one-chip microcomputers 1 are formed on the wafer 10 without scribing, and It is tested whether the one-chip microcomputer 1 operates normally. The wafer test apparatus 2 writes the test results in the external storage device 21 and also writes the test results in the EEPROM 13 of each chip on the wafer 10.
Write also to. At this time, the wafer test apparatus 2 stores information for identifying the position of the wafer 10 and each chip on the wafer 10 in the EEPROM 13 of each chip.
Write to. If the wafer test apparatus 2 determines that the operation is normal, the wafer test apparatus 2 is transferred to a scribing step and further to an assembly step such as packaging.

As shown in FIG. 2B, the product test apparatus 3 is scribed from the wafer 10 determined to operate normally in the wafer test apparatus 2, and the electrical characteristics of the one-chip microcomputer 1 assembled. Inspect
In addition, test whether the specified specifications according to the product specification are satisfied.

Hereinafter, the process of testing and assembling the one-chip microcomputer 1 applied to the present embodiment, and further, ending the test and writing the operation control program, will be described. The process of assembling the device and using it for operation control will be described.

First, a one-chip microcomputer 1
Will be described with reference to the flowchart of FIG. First, the wafer test apparatus 2 has one chip
A test of a physical function of the wafer 10 on which a plurality of circuits of the microcomputer 1 are formed, that is, a test of whether each one-chip microcomputer 1 on the wafer 10 operates normally. Then, the wafer test device 2
Is the test result at the stage of the wafer 10 (test result 1)
Is stored in the external storage device 21 (step S11).

Further, the wafer test apparatus 2 can copy all or a part of the test result 1 stored in the external storage
The data is written into each EEPROM 13 of the one-chip microcomputer 1 on the wafer 10 via the external connection terminal 16. At this time, the wafer test apparatus 2 executes the EEPROM of each one-chip microcomputer 1 on the wafer 10.
Information about the wafer 10 and the position of the chip on the wafer 10 is also written to the OM 13 via the external connection terminal 16 (step S12).

Then, the wafer 10 for which it is confirmed that the wafer test apparatus 2 operates normally is sent to the next step. Next, the wafer 10 is scribed and cut into chips (step S13), and is further packaged or the like to be assembled into a product (one-chip microcomputer 1) for each chip (step S1).
4).

The product test apparatus 3 tests each of the assembled one-chip microcomputers 1 to determine whether the electrical characteristics and the specifications according to the product specifications are satisfied, and performs a test at the chip stage. The result (test result 2) is stored in the external storage device 31 (step S1).
5).

Further, the product test apparatus 3 stores all or a part of the test results 2 stored in the external storage
EEPROM 13 of chip microcomputer 1
Via the external connection terminal 16 (step S1).
6). Then, the one-chip microcomputer 1 in which all the test and assembly processes are completed and both the test result 1 and the test result 2 are normal is sent to the next process of writing the operation control program.

Next, the one-chip microcomputer 1
The process of writing the operation control program after the test is completed will be described. This process may be performed before the one-chip microcomputer 1 is shipped as a product, or may be performed at a product shipping destination.

In this process, a writing device (not shown)
The operation control by the CPU 11 is stored in the area of the EEPROM 13 via the external connection terminal 16 where the test result 1 and the test result 2 are not written and the area to which control is transferred next from the boot program stored in the ROM 12. Write a program for The one-chip microcomputer 1 in which the operation control program has been written into the EEPROM 13 is sent to the next step.

Next, the one-chip microcomputer 1
The following describes a process in which is incorporated into a mechanical device and used for operation control.

One-chip microcomputer 1 in which an operation control program is written in EEPROM 13
Is mounted on an electronic circuit board of a mechanical device to be operation-controlled. Then, when the power is turned on, the mechanical device completed through other manufacturing processes becomes the CPU 13 in the EEPROM 13.
By executing the program, the operation is performed while the operation is controlled.

As described above, in the one-chip microcomputer 1 applied to this embodiment, the CP
The wafer, the position on the wafer, and the test result are written in the EEPROM 13 for writing a program used by the U11 for operation control of the mechanical device. For this reason, even if the one-chip microcomputer 1 does not mount a memory element unnecessary for realizing the original function on the chip, the test result of each chip is made to correspond to the wafer and the position on the wafer. Management.

In the one-chip microcomputer 1 applied to this embodiment, the product management information such as the test result is stored in the EEPROM 13 without erasing it.
The operation control program by the PU 11 is stored in the EEPROM 13
Writing to another area. Therefore, for example, it is also possible to perform product management in which an initial defect found after product shipment is associated with a wafer and a position on the wafer.

The present invention is not limited to the above embodiment,
Various modifications and applications are possible. Hereinafter, modifications of the above-described embodiment applicable to the present invention will be described.

In the above embodiment, the EEPROM 13 is mounted on the one-chip microcomputer 1. Instead, a flash EEPROM capable of erasing data in units of several kilobytes to hundreds of tens of kilobytes is mounted. May be. Flash EEPROM is a normal EEPROM
Since the data writing time is shorter than that of the OM, the time for writing the test result or writing the operation control program by the CPU 11 can be reduced.

However, since the unit of data erasure is large, the test / assembly process in this case is performed according to the procedure shown in the flowchart of FIG. In this flowchart, the processes from steps S21 to S24 are the same as those described in the above embodiment. Next, in the process of step S25, first, the product test apparatus 3 reads out the information written in the EEPROM 13 of the one-chip microcomputer 1 in the test at the wafer stage and stores it in the external storage device 31 (step S25a). . Further, by testing the one-chip microcomputer 1,
The test result is stored in the external storage device 31 (Step S25b).

After that, the product test apparatus 3
The information written in M13 is temporarily erased, and the test results (both wafer stage and product stage) stored in the external storage device 31 in steps S25a and S25b are subjected to EE.
Writing to the PROM 13 (step S26). Thus, the test / assembly process is completed.

In the above-described embodiment, the EEPROM 13 capable of electrically writing and erasing data is used as a nonvolatile memory for writing the test results and writing the operation control program by the CPU 11. . However, as a nonvolatile memory applied to the present invention, an EPROM that erases data by irradiating ultraviolet rays may be used. In this case, the test process may be performed in substantially the same flow as that using the flash EEPROM shown in FIG. An EPROM that can be written only by adding invalid information to unnecessary data.
It is also possible to use

In the above embodiment, the one-chip microcomputer 1 is used as a semiconductor integrated circuit,
An operation control program by the PU 11 is stored in an EEPROM.
13 had been written. However, the present invention may be applied to a semiconductor integrated circuit used as a processor of a personal computer or the like. In this case, for example, a boot program may be written into a non-volatile memory after a test is completed. In addition, the EEPROM 13
Instead of writing a program to a non-volatile memory like this, fixed data may be written.

In the above embodiment, a program for operation control by the CPU 11 is written in another area of the EEPROM 13 while leaving the test results written in the EEPROM 13 by the wafer test apparatus 2 and the product test apparatus 3. On the other hand, a program for operation control by the CPU 11 may be written after erasing the test result written in the EEPROM 13. In this case, the capacity of the EEPROM 13 may be small. The test results themselves are stored in the external storage devices 21 and 23.
To be stored, for example, EEPROM
In 13, other data may be erased leaving only the information for identifying the wafer and the position on the wafer, and then a program for operation control by the CPU 11 may be written.

[0045]

As described above, according to the present invention,
The test result of each scribed chip can be managed in accordance with the position of the wafer without mounting a memory unnecessary for its original function on the semiconductor integrated circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration of a one-chip microcomputer applied to an embodiment of the present invention.

FIGS. 2A and 2B are diagrams showing a test apparatus for testing the one-chip microcomputer of FIG. 1, wherein FIG. 2A shows a test apparatus used in a wafer stage, and FIG. Show.

FIG. 3 is a flowchart showing a test process of a one-chip microcomputer applied to the embodiment of the present invention.

FIG. 4 is a flowchart showing a process of testing and assembling a one-chip microcomputer equipped with a flash EEPROM applied as a modification of the embodiment of the present invention;

FIG. 5 is a flowchart showing a process of testing and assembling a semiconductor integrated circuit which has been conventionally applied.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1-chip microcomputer 10 Wafer 11 CPU 12 ROM 13 EEPROM 14 RAM 15 Peripheral function 16 External connection terminal 2 Wafer test device 21 External storage device 3 Product test device 31 External storage device

Claims (5)

(57) [Claims] 1. A semiconductor integrated circuit equipped with a processing device for performing processing using a program or data written in a nonvolatile memory capable of writing and erasing information , wherein the nonvolatile memory has an external connection. It is configured to be able to write information from the outside via the terminal, the test stage
The product management information including the wafer used for manufacturing the semiconductor integrated circuit on the floor, the position on the wafer, and the test result is written, and the program or the program necessary for the processing device to perform the processing is written.
Is the product that was written during the test phase
After deleting at least a part of the management information,
A semiconductor integrated circuit which is written in a memory . 2. A processing unit required for the processing device to perform processing.
The program or data consists of the wafer and its location on the wafer.
After erasing external product management information,
The information has been written.
Semiconductor integrated circuit. 3. A semiconductor mounted with a non-volatile memory to which information can be externally written via an external connection terminal, and a processing device for performing processing using a program or data written in the non-volatile memory. A method for testing an integrated circuit, comprising: before scribing a wafer used for manufacturing the semiconductor integrated circuit, a test result at the wafer stage, and information on the wafer and a position on the wafer, wherein the external connection is performed. Writing a wafer test result to the nonvolatile memory via a terminal; and writing a product test result to the nonvolatile memory via the external connection terminal, the test result at a product stage after scribing the wafer. And a program or data used by the processing device to perform processing. Test method for a semiconductor integrated circuit, characterized in that via a terminal and a program step of writing into the nonvolatile memory. 4. The non-volatile memory is capable of erasing information, and the program step is performed by writing to the non-volatile memory in the wafer test result writing step and the product test result writing step. 4. The method according to claim 3 , wherein at least a part of the stored information is erased, and then a program or data used for performing the processing by the processing device is written to the nonvolatile memory. . 5. The wafer test result writing step includes a step of writing a test result at a wafer stage and information on a wafer and a position on the wafer to storage means other than a memory mounted on the semiconductor integrated circuit. The step of writing a product test result includes a step of writing a test result in a product stage to storage means other than a memory mounted on the semiconductor integrated circuit, in association with information on the wafer and information on a position on the wafer. the program step is claim 4, wherein the writing without erasing position at least a wafer and on the wafer, the program or data the processing device used for processing in the non-volatile memory 3. The test method for a semiconductor integrated circuit according to 1.