JP3201463B2 - Apparatus and method for designing semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog semiconductor integrated circuit designing apparatus and a designing method using a master slice method.

[0002]

2. Description of the Related Art Conventionally, a so-called master slice method has been adopted for layout design of a semiconductor integrated circuit in order to shorten the development and manufacturing period of the semiconductor integrated circuit. A master slice (hereinafter, referred to as “master”) refers to a semiconductor wafer in which a resistor, a transistor, a capacitor, and the like having a predetermined element value are formed in advance. In the master slice method, elements formed on a master are allocated to respective elements (hereinafter, referred to as “target elements”) in an electric circuit to be laid out in a semiconductor integrated circuit, and the elements on the allocated master are allocated. This is a method of designing a semiconductor integrated circuit by performing wiring based on a connection relationship between target elements. When assigning an element on the master to a target element, a combination of the element values of the element on the master assigned to one target element is assigned so as to become the element value of the target element. Further, a region where a group of resistance elements is formed on the master is used as a wiring region even if the resistance element is assigned to a target element.

When a wiring path is not found when wiring is performed using such a master, the wiring is left as unwired. When unwiring occurs, a process is performed to change an assigned element on the wiring path to another element at a position that does not interfere with the wiring so that the unwired portion can be wired. FIG. 19 is an explanatory diagram illustrating an example of a change in element assignment due to the occurrence of a non-wiring. FIG. 19A shows a part of a master to which elements are assigned. FIG. 19B shows a part of the master of FIG. 19A in which the assignment of elements has been changed due to the occurrence of unwiring.

In FIG. 19A, a pad 1101 is a terminal for connecting a wiring inside a semiconductor chip to the outside. The resistance element 1102, the resistance element 1103, and the resistance element 1104 are allocated resistance elements on the master. The resistance element 1105 is an unassigned resistance element. The transistor element 1106 and the transistor element 1107 are assigned transistor elements.

Here, when it is attempted to connect the pad 1101 and the transistor 1106 by wiring, FIG.
The resistor 1102 and the resistor 1103 in FIG.
01, the pad 1101
To the transistor 1106 from the metal wiring layer.

For this reason, as shown in FIG. 19B, the resistance elements 1102 and 1103 allocated on the semiconductor chip are changed to the resistance elements 1108 and 1109, respectively, so that the wiring elements are changed. The region 1110 can be used, and the wiring region 1110 can be used rather than using the resistance element 1105 as a wiring region.
Wiring is performed inside. In FIG. 19B, the resistance element 1108 and the resistance element 1109 are the same as those in FIG.
This is the changed resistance element when the assignment of the resistance elements 1102 and 1103 is changed. The wiring region 1110 includes the resistor 1102 and the resistor 1103.
Is a wiring area obtained by changing the allocation of the wiring.

[0007]

However, FIG.
In the case shown in (a), since the resistive elements 1108 and 1109 happened to be unassigned, the assignment of the resistive elements 1102 and 1103 could be changed. Actually, even if an attempt is made to change the assignment of elements, an unassigned element is not always easily found. Even if an element whose assignment can be changed is found, it is generally very difficult to find a wiring path to the element after the assignment is changed. In addition, the wiring from the pads is often an important wiring such as a power supply main line or power supply wiring, and these wirings have many restrictions in wiring compared to general wiring for connecting the terminals of the element. Therefore, there is a problem that it is more difficult to find a wiring route. The power supply main line is a main line for introducing a power supply voltage supplied from the outside onto the semiconductor substrate, and the power supply wiring is a wiring for connecting a terminal of an element to which the power supply voltage is to be supplied to the power supply main line. is there. In such a case, for example, in order to give priority to an important wiring which has not been wired, a method of redoing a wiring which is an obstacle of an important wiring can be considered, but complicated processing and many man-hours are required. As a result, there is a problem that the development and manufacturing period of the semiconductor integrated circuit is lengthened.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a semiconductor integrated circuit designing apparatus and a designing method capable of performing wiring design with few unwiring.

[0009]

SUMMARY OF THE INVENTION In view of the above problems, a semiconductor integrated circuit designing apparatus according to the present invention is a semiconductor integrated circuit designing apparatus for designing a semiconductor integrated circuit using a master slice. Allocating means for allocating elements formed on the master slice to each element in the electric circuit to be designed, and power supply wiring for supplying power to allocated elements to which power supply voltage is to be supplied. The power supply wiring means, which is routed avoiding the other assigned elements, and leaves the wiring unconnected if the wiring path is not found, and detects the unwired power supply wiring after the power supply wiring is completed by the power supply wiring means Unwiring detecting means for allocating the detected power wiring, allocating prohibiting means for adding allocating prohibition information to an allocated element which is a cause of the unwiring, and an allocation prohibiting information. And an assignment changing means for changing the assignment of the assigned element to which the assignment changing information has been added to another unassigned element to which the assignment prohibition information has not been added. Perform wiring.

In the above-mentioned semiconductor integrated circuit designing apparatus,
The allocating means allocates the elements formed on the master slice to each element in the electric circuit to be designed into the semiconductor integrated circuit. The power supply wiring means routes the power supply wiring for supplying power to the allocated element to which the power supply voltage is to be supplied, avoiding the other allocated elements. Leave it as it is. The unwired detecting means detects the unwired power wiring after the power wiring by the power wiring means is completed. The allocation prohibition unit adds the allocation prohibition information to the allocated element which is the cause of the undetected power supply wiring.
The allocation changing means changes the allocation of the allocated element to which the allocation prohibition information is added to another unallocated element to which the allocation prohibition information is not added. In this case, the power supply wiring means performs power supply wiring again after the assignment change by the assignment change means.

Prior to performing the general wiring, the power supply wiring that could not be wired is detected, and the assignment of the allocated element that is the cause of the non-wiring is changed. Since it is removed, compared to the case where the assignment of the assigned element is changed after the completion of the entire wiring process,
There is an effect that the wiring path of the power supply wiring can be easily and reliably secured. Further, even when the power supply wiring can be bypassed around the assigned element that becomes a failure, by adding the assignment prohibition information to the assigned element,
This has the effect that a wiring path can be secured so that the wiring length of the power supply wiring is shorter.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a hardware configuration of a semiconductor integrated circuit designing apparatus 100 according to one embodiment of the present invention. The semiconductor integrated circuit design apparatus 100 includes a CAD (Computer Aided Des) realized by a workstation or the like.
i) device, display 101, input unit 10
2. It includes a CPU 103 and a storage unit 104.

The display 101 is realized by a cathode ray tube (CRT), a liquid crystal display (LCD), or the like. The input unit 102 is realized by a keyboard or a tablet. The CPU 103 is an arithmetic processing device that controls the entire semiconductor integrated circuit design device 100. Storage unit 10
4 is realized by a RAM, a hard disk, or the like. FIG. 2 is a block diagram showing a functional configuration of a semiconductor integrated circuit designing apparatus 100 according to one embodiment of the present invention.

The semiconductor integrated circuit designing apparatus 100 includes an element allocating unit 110, a priority information adding unit 111, an allocation limiting unit 11
2, a control unit 113 and a wiring unit 114 are provided. Element allocating section 110, priority information adding section 111, allocation limiting section 11
2. Both the control unit 113 and the wiring unit 114 are realized by the CPU 103 executing a program stored in the storage unit 104.

The element allocating section 110 allocates an element on the master to each target element under the control of the control section 113. At this time, if there is an element on the master to which assignment restriction information indicating prohibition of assignment to the target element is added, the element is not assigned to the target element. Further, when the allocation restriction information is added to the allocated element, the allocation of the allocated element is changed to another unallocated element, and the element to which the allocation restriction information is added is unallocated. Return to

The priority information adding unit 111, under the control of the control unit 113, preferentially uses a wiring area among the wiring areas preset on the master, which has a small number of assigned elements that cause a wiring failure. Is generated and added to each wiring area. Specifically, in the master used in the present embodiment, a wiring area for providing a fixed wiring path for the power supply wiring and the general wiring is manually set in advance when the master is generated. The wiring area is set at a predetermined width on the area where the group of resistance elements is arranged. Even when the resistance element in the wiring area is assigned to the target element, the wiring can pass over the element. For each such wiring area, the priority information adding unit 111 checks the number of elements in the wiring area and the number of allocated elements among them. Next, the priority information adding unit 111 calculates an allocation ratio of the elements in each wiring area from the checked number of elements and the number of allocated elements. The priority information adding unit 111 generates priority information indicating a priority when each wiring area is used as a wiring area based on the calculated allocation ratio, and adds the priority information to each wiring area. . Specifically, the priority information is represented by a numerical value converted to an integer by multiplying the calculated allocation ratio by a certain number, and the smaller the numerical value, the higher the priority of the wiring area. .

Under the control of the control unit 113, the allocation limiting unit 112 determines whether or not there is any unwiring from the pad and the possibility of a short circuit between the power supply ground potentials due to the terminals of the elements not connected to the power supply after the completion of power supply wiring by the wiring unit 114 Is determined. If it is determined that there is unwired data, allocation restriction information is added to the allocated elements that cause unwired data.
Here, the assigned element that causes the non-wiring from the pad is the assigned element that exists immediately in the region where the width of the pad is extended.

When it is determined that there is a possibility of a short circuit between the power supply ground potentials, the allocation restricting unit 112 adds the allocation restriction information to the element causing the short circuit. Specifically, the presence or absence of a possibility of a short circuit between the power supply ground potentials due to the terminals of the elements not connected to the power supply is determined for the following four points. (1) A group of resistance elements on the master are provided with wirings (hereinafter, referred to as wirings) for collectively supplying a substrate potential to those resistance elements.
It is called “substrate potential supply wiring”. ) Is set in advance. The assignment limiting unit 112 selects one of the group of resistance elements.
When at least one of the target elements is allocated, a region obtained by enlarging the substrate potential supply wiring by the width of the wiring pitch is defined as an allocation prohibition region. It is determined that there is a possibility of a short circuit. In this case, the allocation restricting unit 112 adds the allocation restriction information to the element having the terminal in the allocation prohibition area.

(2) Some resistance elements on the master have their resistance values changed by trimming and others do not. When the power supply wiring not connected to the terminal is located in a region obtained by enlarging the terminal region of the untrimmed allocated resistance element by the width of the wiring pitch, the allocation restricting unit 112 It is determined that there is a possibility of a short circuit. That is, there is a possibility that the general wiring connected to the terminal and the power supply wiring are short-circuited. In this case, the allocation restriction unit 112 adds the allocation restriction information to the allocated resistance element.

(3) For the trimmed resistor element, the power supply wiring that is not connected to the terminal of the trimmed resistance element is connected to the area of the trimmed resistance element that is effective as a resistance after the trimming by the width of the wiring pitch. In some cases, it is determined that there is a possibility of a short circuit between the power supply ground potentials. The allocation restriction unit 112 adds allocation restriction information to the trimmed allocated resistance element.

(4) The allocation restricting unit 112 is provided when the terminal of the element is in an allocation prohibition area in which the area for the power wiring from the pad to pass is enlarged by the wiring pitch in the arrangement direction of the resistance elements on the master. , Add the assignment restriction information to the element. The control unit 113 includes an element allocation unit 110,
The priority information adding unit 111, the assignment limiting unit 112, and the wiring unit 114 are controlled to execute the semiconductor integrated circuit designing method of the present invention according to the processing procedure described later.

The wiring section 114 refers to the priority information added to each wiring area, and uses the wiring area having the highest priority of the priority information. Power supply wiring, complementary power supply wiring, and general wiring are performed by a method or the like. The wiring unit 114 leaves the wiring for which a wiring route cannot be found as it is unwired. If the power supply wiring is unwired or if there is a possibility of a short circuit between the power supply wiring and the general wiring, the assignment restricting unit 112 removes the cause of the unwired or shorted element. The allocation restriction information is added, and the element allocation is changed by the element allocation unit 110 based on the added allocation restriction information. Thereafter, the priority information adding unit 111
As a result, the priority information added to each wiring area is updated. Each time the priority information is updated by the priority information adding unit 111, the wiring unit 114 repeatedly performs power supply wiring according to the updated priority information.

FIG. 3 is a flowchart showing a procedure for designing a semiconductor integrated circuit by the semiconductor integrated circuit designing apparatus 100 of the present invention. If there is an element to which the allocation restriction information is added, the element allocating unit 110 removes the element from the allocation, allocates the element on the master to the target element, ie, the transistor element and the resistance element (step S30).
1) Store element allocation information indicating which element on the master is allocated to which target element.

Next, the priority information adding unit 111 calculates, for each wiring area, an allocation ratio of elements existing in each wiring area, and generates priority information for each wiring area based on the calculated allocation ratio. Then, the generated priority information is added to the corresponding wiring area (step S302). The wiring unit 114 refers to the priority information added to each wiring area, and uses the wiring area with the smallest value of the priority information, that is, the wiring area with the highest priority. And the arrangement of the power supply main lines and the power supply wiring are stored as wiring information (step S303).

The allocation restricting unit 112 determines whether there is a possibility of a short-circuit between the power supply wiring wired in step S303 and an unwired or power supply ground potential (step S304). As a result of the determination, if there is a possibility of a short circuit between the power supply wiring and the unwired or power supply ground potential, the allocation limiting unit 112 determines whether a failure for wiring the unwired data on the master or a short circuit between the power supply ground potentials is caused. The element assignment restriction information is added to the element (Step S305), and the process returns to Step S301.

As a result of the judgment, if there is no possibility of short circuit between the power supply wiring and the non-wiring and the power supply ground potential,
The element assignment unit 110 assigns an element to the capacitance element (Step S306). Further, the wiring unit 114
The complementary power supply wiring is performed with reference to the element allocation information allocated in the steps S301 and S306 (step S307).

Hereinafter, the complementary power supply wiring will be described. In general, a master is configured by combining a plurality of basic element constituent units (hereinafter, referred to as units) each having a predetermined set of elements, and not all of these units are necessarily used. Some units are not used. Step S30 for such a master
By repeating the processing from 1 to step S305, if the number of resistance elements to be allocated to the target element in a certain unit becomes insufficient, the resistance elements in the unused units may be allocated for replenishment. is there. When a resistor element in an unused unit is used for replenishing another unit, the substrate potential of the unused unit needs to be the same as the substrate potential of the unit to be refilled. In order to adjust the substrate potential, a power supply line is newly provided to an unused unit, and a power supply voltage is supplied. If necessary,
The main power line is extended. The complementary power supply wiring refers to the extension of the power supply main line and the power supply wiring in this case.

Next, the wiring section 114 performs general wiring for connecting elements (step S308). By repeating the steps from step S301 to step S305 as described above, the occurrence of short circuit between the power supply wiring and the power supply ground potential is suppressed, and then the steps S306, S307, and S308 are performed. A layout design of a semiconductor integrated circuit can be performed.

FIG. 4 is an explanatory view schematically showing an example of the arrangement of elements formed on a master. As described above, the actual master is generally the master 4
01, a plurality of units in which elements are formed in advance as shown in FIG. 1, and the configuration and arrangement of the elements on each unit and the total number of elements on the master are determined according to the electrical circuit expected for each unit. Has been customized.

In the element allocation area 402 of the master 401, resistance elements 1 to 12, resistance elements 25 to 36, transistor elements 13 to 24, capacitance elements 37 to 40, and pads 41 to 72 are formed. In the element allocation area 402, the elements formed on the master 401 are allocated to respective target elements of the same type in an electric circuit to be realized using the master 401 according to their element values, and each allocated element is A power supply main line for supplying a power supply voltage to the elements, a power supply wiring, and general wirings for connecting the allocated elements in accordance with an electric circuit are provided.
The pads 41 to 72 are terminals for connecting a circuit in the master 401 and an external circuit.

FIG. 5 is a circuit diagram showing an example of an electric circuit to be realized in a semiconductor integrated circuit using a master. The amplifier circuit 501 includes a power supply terminal 502, an input signal terminal 503, a ground potential terminal 504, an output signal terminal 505, a reference potential input terminal 506, resistance elements 507 to 510, and transistor elements 511 to 514.

The transistor element 511 has a collector connected to the power supply terminal 502 via the resistance element 507, a base connected to the input signal terminal 503, and an emitter connected to the collector of the transistor element 513. Transistor element 5
12 indicates that the collector is the output signal terminal 505 and the resistance element 50
8, the base is connected to the reference potential input terminal 506 via the resistor 510, and the emitter is connected to the collector of the transistor 513.

The transistor element 513 has a collector connected to the emitter of the transistor element 511 and an emitter of the transistor element 512, a base connected to the base of the transistor element 514, and an emitter connected to the ground potential terminal 504.
Connected to. The transistor element 514 has a collector connected to the power supply terminal 502 via the resistance element 509, a short circuit between the collector and the base, a base connected to the base of the transistor element 513, and an emitter connected to the ground potential terminal 504.

FIG. 6 is a flowchart showing an example of a more detailed processing procedure of the priority information generation step of step S302. The priority information adding unit 111 reads the element assignment information assigned in the step S301 (step S601). The priority information adding unit 111 determines whether or not priority information has been generated in all of the wiring regions on the master (step S602), and as a result of the determination, priority information has not been generated yet. If there is no wiring area, the process ends.

If the result of determination is that there is a wiring area for which priority information has not yet been generated, the priority information adding unit 111 counts the number of elements in the wiring area (step S60).
3) Then, among the elements counted in the wiring area, the number of elements already assigned to the target element is counted (step S604). The priority information adding unit 111
The number of elements obtained in the step S603 and the step S603
The allocation ratio of the elements in the wiring area is calculated from the number of allocated elements obtained in the step 604. Further, a predetermined operation is performed on the allocation ratio of the calculation result to obtain priority information of the wiring area, and the priority information is added to the wiring area (step S605), and the process returns to step S602.

FIG. 7 is an explanatory diagram showing an example of the arrangement of elements on a unit 700 which is a target of power supply wiring based on priority information. In practice, in the present embodiment, the assignment between the resistive element 706 and the resistive element 707 is changed by the addition of the assignment restriction information by the assignment restriction unit 112. It is assumed that wiring from the pad 701 to the transistor element 710 is simply performed based on only the priority information without changing the element allocation.

In the unit 700, a wiring area 702 and a wiring area 703 are set in the element allocation area of the unit 700. Wiring area 702 and wiring area 70
Reference numeral 3 denotes a wiring area that has been manually set in advance, and only a resistance element is formed in each of the areas. In the unit 700, for example, the pad 7
01 is assigned to the ground potential terminal 504 which is the target element in FIG.
14, the resistor 706, the resistor 707, and the resistor 708 are assigned to the resistor 509. Therefore, in the unit 700, it is necessary to connect the pad 701 and the emitter terminal of the transistor element 710 with the power supply wiring.

A resistance element 708 and a resistance element 709 are formed in the wiring area 702.
08 has been assigned. The allocation ratio of elements in the wiring region 702 is 1/2. A resistance element 704 and a resistance element 705 are formed in the wiring region 703.
Both the resistance element 704 and the resistance element 705 are unassigned. Therefore, the element allocation ratio of the wiring area 703 is 0.

As a result, the value of the priority information added to each wiring area by the priority information adding unit 111 is smaller in the wiring area 703 than in the wiring area 702.
The wiring area 703 is preferentially used as the wiring area. If power supply wiring is performed based only on this priority information, power supply wiring as shown in FIG. 8 below is possible. FIG. 8 is an explanatory diagram showing an example of a power supply wiring design based on only the priority information for the element arrangement shown in FIG.

The second metal wiring layer 801 from the pad 701
Are connected to the first metal wiring layer 802 by through holes 805, and the first metal wiring layer 802 is
06, it is connected to the second metal wiring layer 803. The second metal wiring layer 803 is connected to the first metal wiring layer 804 through a through hole 807, and the first metal wiring layer 804 is connected to, for example, an emitter terminal of the transistor element 710. As a result, the pad 701 is connected to the transistor element 710 through the wiring region 703, and for example, the pad 701 is connected to the emitter terminal of the transistor element 710.
Supplies a ground potential.

In the example shown in FIGS. 7 and 8, the pad 7
01 through the wiring area 702 to the transistor element 7
10, it is possible to wire the wiring area 702.
Is used as a power supply wiring, the power supply wiring may interfere with the general wiring for the assigned resistance element 708 in the wiring area 702, and the general wiring may be unwired. Therefore, by using the wiring area 703 having a smaller element allocation ratio without using the wiring area 702 as the power supply wiring, it is possible to reduce the occurrence of unwired general wiring. Play.

FIG. 9 is a flowchart showing an example of a more detailed processing procedure of the assignment restriction information adding step of step S305. The allocation restriction unit 112 determines in step S301
Of the element allocation performed in the process of step S303
The wiring information of the power supply wiring performed in the step is read (step S901).

The allocation restricting unit 112 searches for unwired data from the pad based on the read element allocation data and wiring data (step S902), and determines whether there is any unwired data from the pad (step S903). ). If there is no unwiring from the pad, the process proceeds to step S905. If there is a non-wiring from the pad, the allocation restricting unit 112 adds the allocation restriction information to the allocated element that has become an obstacle to the wiring from the pad, and returns to the processing of step S902 (step S904). The assignment limiting unit 112
This process is repeated until there is no unwired.

Further, the allocation restricting unit 112 searches the power supply wiring from the pad for an element having a possibility of short-circuit of the general wiring, and adds the allocation restriction information to the element of the search result (step S905). ). Next, the assignment limiting unit 1
Reference numeral 12 adds allocation restriction information to the substrate potential supply wiring for the group of resistance elements including the allocated elements, to the element that is likely to short-circuit the general wiring (step S906).

Further, the allocation restricting unit 112 searches the power supply wiring for a resistance element having a possibility of short-circuiting the general wiring, and adds the allocation restriction information to the searched resistance element (step S907). . FIG. 10 is an explanatory diagram illustrating an example of the arrangement of elements on the unit 1001 that is a target of power supply wiring.

In the wiring area 1002 of the unit 1001, the pad 1003 is connected to the ground potential terminal 504, and the resistance elements 1004 and 1005 are connected to the resistance element 508.
The resistance element 1006 and the resistance element 1007 are assigned to the resistance element 507,
9 denotes a transistor element 511 and a transistor element 10
08 is the transistor element 512 and the transistor element 1
It is assumed that 010 is assigned to the transistor element 513.

As shown in FIG. 5, the transistor element 5
Since the emitter terminal of the transistor 13 is connected to the ground potential terminal 504, the power supply wiring by the metal wiring layer must be performed from the pad 1003 to the emitter terminal of the transistor element 1010 in the step S303.
003, a resistance element 1004, a resistance element 1005,
Since the resistance elements 1006 and 1007 have already been assigned to the resistance elements 507 and 508, wiring from the pad 1003 cannot be performed. For this reason, the non-wiring from the pad 1003 occurs.

As a result, it is determined that unwiring has occurred in the step S304, and element allocation restriction information is added to the resistive element 1005 and the resistive element 1006 in the vicinity of the pad 1003 in the step S305. Next, in a state where the element allocation restriction information is added to the resistance elements 1005 and 1006, steps S301, S302, and S303 are performed.
Is repeated. Thereby, the resistance element 1005
In addition, the assignment of elements to the resistance element 1006 is changed, and the resistance element 1005 and the resistance element 1006 are unassigned elements.

FIG. 11 is an explanatory diagram showing an example of the power supply wiring after the assignment of the elements to the resistance elements 508 and 507 in FIG. 10 has been changed. As a result of performing the step S301 in a state where the element allocation restriction information is added to the resistance elements 1005 and 1006, FIG.
1, the resistance element 1101 and the resistance element 10
04 is assigned to the resistor 508, and the resistor 1007 and the resistor 1102 are assigned to the resistor 507. As described above, by adding the allocation restriction information to the resistance elements 1005 and 1006 below the pad 1003,
Power supply wiring from the pad 1003 becomes possible.

In FIG. 11, first metal wiring layer 1106 connects resistance element 1101 and resistance element 1007 to power supply terminal 50.
Pad (not shown) assigned to 2 (or power supply main line)
Connected to The second metal wiring layer 1103 and the first metal wiring layer 1105 are connected via a through hole 1104, and the pad 1003 and the transistor element 101 are connected.
0 is connected to the emitter terminal.

FIG. 12 is a flowchart showing an example of a more detailed processing procedure of the step S905. FIG. 13 is an explanatory diagram showing elements to which the assignment restriction information is added in the processing of step S905. In FIG. 13, the area surrounded by the broken line is the assignment prohibition area 1
303. The allocation limiting unit 112 determines in step S901
From the element allocation information and the wiring information of the power supply wiring read in the above, the possibility of a short circuit between the power supply wiring from the pad and the other wiring and the like is not examined, that is, unprocessed. Search for a pad (Step S
1201), it is checked whether there is any unprocessed pad as a result of the search (step S1202). If there is no search result, that is, if there is no unprocessed pad, the process ends.

If there is an unprocessed pad, an area occupied by the power supply wiring from that pad is obtained, and the obtained power supply wiring area is enlarged by the width of the wiring pitch in the arrangement direction of the resistance elements, and an allocation prohibited area is set. (Step S120
3). For example, if the pad 1301 shown in FIG.
In this case, an area occupied by the power supply wiring 1302 from the pad 1301 is determined, and an allocation prohibition area 1303 is set by expanding the area by the wiring pitch width W0 in the arrangement direction of the resistance elements.

Further, the allocation restricting unit 112 sets an allocation prohibition area, for example, based on the element allocation information, for example,
A search is made for an element having a terminal in the assignment prohibition area 1303 and no assignment restriction information added thereto (step S).
1204). As a result of the search, it is checked whether or not there is a corresponding element (step S1205). If there is, the assignment restriction information is added to the element (step S1206), and the process returns to step S1204. If there is no corresponding element in step S1205, step S1201
Return to the processing of.

FIG. 14 is a flowchart showing an example of a more detailed processing procedure of step S906. FIG. 15 is an explanatory diagram showing the elements to which the allocation restriction information is added in the processing of step S906. The allocation restricting unit 112 is a substrate potential supply wiring that supplies a substrate potential to a group of resistance elements including the allocated resistance elements based on the element allocation information read in the step S901, and A search is made for an unprocessed substrate potential supply wiring that has not been checked for the possibility of a short circuit with another wiring or the like (step S1401). It is assumed that, for example, a substrate potential supply wiring 1502 shown in FIG. 15 is obtained as a search result in step S1401. The substrate potential supply wiring 1502 is a terminal for supplying a substrate potential to a group of resistors 1500 including the assigned resistor 1501.

As a result of the search, the allocation restricting unit 112 checks whether or not there is an unprocessed substrate potential supply wiring (step S1402). If there is, the area occupied by the substrate potential supply wiring is determined. An allocation prohibited area is set by enlarging the allocated area by the width of the wiring pitch (step S140)
3). If there is no unprocessed substrate potential supply wiring, the process ends. More specifically, in step S1403, the area occupied by the substrate potential supply wiring 1502 is obtained, and the obtained area is enlarged by the width of the wiring pitch.
503 is set for the substrate potential supply wiring 1502.

Based on the element allocation information, the allocation restricting unit 112 searches for an element in which a terminal is present in a set allocation prohibition area, for example, an allocation prohibition area 1503, and to which no allocation restriction information is added. Step S140
4). Next, as a result of the search, it is checked whether or not there is a corresponding element (step S1405). If there is, the assignment restriction information is added to the element (step S140).
6) Return to the processing of step S1404, otherwise return to the processing of step S1401. As a result of the search in step S1404, for example, the terminal 15
An element (not shown) having “04” is obtained, and assignment restriction information is added to the element.

FIG. 16 is a flowchart showing an example of a more detailed processing procedure of the step S907. FIG. 18 is an explanatory diagram showing an untrimmed resistance element to which the allocation restriction information is added in the process of step S907. FIG. 17 is an explanatory diagram showing the trimmed resistive elements to which the allocation restriction information is added in the process of step S907.

The allocation restricting unit 112 searches the wiring information read in step S901 for the area of the power supply wiring wired in step S303 (step S16).
01). As a result of the search, the possibility of a short circuit with the terminal of the resistance element has not been checked yet, that is, it is checked whether or not there is an unprocessed power supply wiring (step S1602). The resistive element is enlarged by the width (step S1603), and a part or all of the resistive element existing in the enlarged power supply wiring region is searched (step S1603)
1604).

The allocation limiting unit 112 checks whether a search result has been obtained, that is, whether or not there is an unprocessed resistance element partially or wholly present in the enlarged power supply wiring area (step S1605). If there is an unprocessed resistance element to be processed, it is further checked whether or not the element has been trimmed (step S1606). Step S160
In step S6, if the resistance element in the search result has been trimmed, the effective resistance region giving the effective resistance value of the resistance element is enlarged by the width of the wiring pitch (step S16).
07), expanded effective resistance region and step S1601
It is checked whether or not there is a portion that overlaps with the power supply wiring area as the search result (step S1608). If there is an overlapping portion, allocation restriction information is added to the resistance element (step S1609). If they do not overlap, the process returns to step S1604.

For example, the region of the power supply wiring 1701 shown in FIG. 17 overlaps the region of the resistance element 1700. Therefore, the region of the resistance element 1700 is
Region overlaps with the region further enlarged by the width of the wiring pitch. If the resistance element 1700 is obtained as a search result in step S1604, the allocation restricting unit 11
2 checks whether the resistance element 1700 has been trimmed. Since the resistance element 1700 has been trimmed, the allocation restricting unit 112 further sets the resistance terminals 1703 and 1704 of the trimmed resistance element 1700.
The effective resistance region 1702 excluding the above is obtained, the obtained effective resistance region 1702 is expanded by the width of the wiring pitch W0 to obtain the power supply wiring avoidance region 1705, and the obtained power supply wiring avoidance region 1705 is set to the resistance element 1700. I do. The allocation restricting unit 112 checks whether or not the power wiring avoiding area 1705 and the power wiring 1701 overlap. Since the power wiring avoiding area 1705 and the power wiring 1701 overlap, the allocation restricting unit 112 adds the allocation restriction information to the resistance element 1700.

In step S1606, if the resistance element in the search result is not trimmed, the area occupied by the terminal of the resistance element is expanded by the width of the wiring pitch (step S1610). It is checked whether or not the wiring area overlaps (Step S)
1611). If they overlap, the process returns to step S1609, and if they do not overlap, step S160
The process returns to step 4.

For example, the resistance element 1802 shown in FIG.
Overlap with the power supply wiring 1801 and are not trimmed. For this resistance element 1802, the allocation limiting unit 112 sets a power supply wiring avoidance area 1804 in which the area of the resistance terminal 1803 is enlarged by the wiring pitch width W0. The allocation restricting unit 112 checks whether or not the power wiring avoiding area 1804 and the power wiring 1801 overlap. Since the power wiring avoiding area 1804 and the power wiring 1801 overlap, the allocation restricting unit 112 adds the allocation restriction information to the resistance element 1802.

As described above, according to the present embodiment, the semiconductor integrated circuit designing apparatus 100 first assigns elements to the resistance elements and the transistor elements, and then, based on the priority information, Since the power supply wiring is performed by preferentially using the area with less elements, it is possible to prevent the power supply wiring from becoming an obstacle to the wiring with respect to the general wiring connecting the terminals of the element. This has the effect of reducing the occurrence of unwiring.

Further, by assigning the allocation restriction information to the elements that may cause a trouble in the power supply wiring, and then re-allocating the elements, the unwiring of the power supply wiring can be prevented, and the power supply wiring is not connected. There is an effect that a short circuit between the wiring to the terminal of the element and the power supply wiring can be prevented. In the present embodiment, only the power supply wiring uses the wiring area based on the priority information and redistributes the elements based on the element allocation restriction information. May perform the same processing.

[0065]

According to the present invention, there is provided an apparatus for designing a semiconductor integrated circuit, comprising:
An allocating means for allocating an element formed on a master slice to each element in an electric circuit to be designed into a semiconductor integrated circuit, and a power supply for supplying power to an allocated element to which a power supply voltage is to be supplied. The power supply wiring is routed avoiding the other allocated elements, and if the wiring route is not found, the power supply wiring means is left unwired. Unwired detection means for detecting wiring, allocation prohibition means for adding allocation prohibition information to an allocated element which is a cause of non-wiring for a detected power supply wiring, and assigned element to which allocation prohibition information is added And an assignment changing means for changing the assignment to another unassigned element to which the assignment prohibition information is not added. Again perform the power wiring.

Therefore, according to the semiconductor integrated circuit designing apparatus of the present invention, after the power supply wiring is completed, before the general wiring is performed, the unwired power supply wiring is detected, and the assigned element which is the cause of the unwiring is detected. By changing the assignment, the cause of the unwiring of the power supply wiring is removed preferentially, so that the wiring path of the power supply wiring is easily and reliably secured compared to the case where the assignment of the allocated elements is changed after the completion of the entire wiring process. It has the effect that it can be done. Further, even in the case where the power supply wiring can be bypassed around the assigned element that becomes a failure, the wiring path is secured so that the wiring length of the power supply wiring is shortened by adding the assignment prohibition information to the assigned element. It has the effect of being able to do so.

According to another aspect of the present invention, there is provided a semiconductor integrated circuit designing apparatus, further comprising:
Of the power supply wiring wired by the power supply wiring means,
A short-circuit detecting means for detecting a power supply wiring that may be short-circuited with another wiring; and for the power supply wiring detected by the short-circuit detection means, an assigned element whose wiring to a terminal may cause a short circuit with the power supply wiring. Element detecting means for detecting, the allocation prohibiting means adding allocation prohibition information to the allocated element detected by the element detecting means.

Therefore, according to another semiconductor integrated circuit designing apparatus of the present invention, a power supply wiring which may be short-circuited with another wiring is detected, which may cause a short circuit between the power supply wiring and another wiring. Since the element assignment is changed, the possibility of a short circuit with the power supply wiring can be eliminated from the general wiring performed at the power supply wiring stage. This has the effect of reducing the occurrence of.

Still another semiconductor integrated circuit designing apparatus according to the present invention is a semiconductor integrated circuit designing apparatus for designing a semiconductor integrated circuit by using a master slice. Allocating means for allocating the elements formed on the master slice to each element, and preferentially assigning a wiring area having a smaller number of allocated elements to each wiring area preset on the master slice. Priority addition means for adding a priority indicating use, and wiring means for performing wiring by using the wiring area according to the priority added to each wiring area.

Therefore, according to still another semiconductor integrated circuit designing apparatus of the present invention, the wiring means preferentially uses the wiring area to which the number of allocated elements is smaller, so that wiring failure is originally caused. In this case, wiring can be performed in a region where the number of wirings is small, and the effect of reducing the occurrence of non-wiring can be achieved. In addition, it is possible to reduce extra steps such as a change in assignment to an assigned element that has caused a wiring failure, to efficiently perform wiring, and to design a layout of a desired semiconductor integrated circuit in a shorter time. It works.

According to still another aspect of the present invention, in the above-mentioned semiconductor integrated circuit designing apparatus, the priority adding means includes the number of elements formed in each wiring area, Calculating means for calculating a ratio of the number of elements allocated by the allocating means in the wiring area, and the priority adding means adds a priority to each wiring area based on the calculated ratio.

Therefore, according to still another semiconductor integrated circuit designing apparatus of the present invention, the priority added based on the ratio of the number of elements formed in the wiring area to the number of allocated elements. By wiring according to the degree, the same effect as described above can be obtained. According to the semiconductor integrated circuit designing method of the present invention, the same effects as those of the corresponding semiconductor integrated circuit designing apparatus can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a hardware configuration of a semiconductor integrated circuit design device 100 according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a functional configuration of a semiconductor integrated circuit designing apparatus 100 according to one embodiment of the present invention.

FIG. 3 is a flowchart showing a procedure for designing a semiconductor integrated circuit by the semiconductor integrated circuit designing apparatus 100 of the present invention.

FIG. 4 is an explanatory diagram showing an example of an arrangement of elements formed on a master.

FIG. 5 is a circuit diagram showing an example of an electric circuit to be realized in a semiconductor integrated circuit using a master.

FIG. 6 is a flowchart illustrating an example of a more detailed processing procedure of a priority information generation step of step S302.

FIG. 7 is an explanatory diagram showing an example of an arrangement of elements on a unit 700 which is a target of power supply wiring based on priority information.

FIG. 8 is an explanatory diagram showing an example of a power supply wiring design based on only priority information for the element arrangement shown in FIG. 7;

FIG. 9 is a flowchart illustrating an example of a more detailed processing procedure of an assignment restriction information adding step in step S305.

FIG. 10 is a diagram showing a unit 100 to which power supply wiring is applied.
FIG. 2 is an explanatory diagram showing an example of the arrangement of elements on the first device.

FIG. 11 shows the resistance element 508 and the resistance element 50 shown in FIG.
FIG. 11 is an explanatory diagram showing an example of a power supply wiring after changing the assignment of elements to 7;

FIG. 12 is a flowchart illustrating an example of a more detailed processing procedure of step S905.

FIG. 13 is an explanatory diagram showing elements to which assignment restriction information is added in the processing of step S905.

FIG. 14 is a flowchart illustrating an example of a more detailed processing procedure of step S906.

FIG. 15 is an explanatory diagram showing elements to which allocation restriction information is added in the processing of step S906.

FIG. 16 is a flowchart illustrating an example of a more detailed processing procedure of step S907.

FIG. 17 is an explanatory diagram showing a trimmed resistive element to which allocation restriction information is added in the process of step S907.

FIG. 18 is an explanatory diagram showing untrimmed resistance elements to which assignment restriction information is added in the process of step S907.

FIG. 19 is an explanatory diagram showing an example of a conventional change in element allocation due to the occurrence of unwiring.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 semiconductor integrated circuit design device 111 priority information adding unit 112 assignment limiting unit 113 control unit 114 wiring unit

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Yuko Mitsuyasu 1-1, Komachi, Takatsuki-shi, Osaka Matsushita Electronics Corporation (56) References JP-A-1-140640 (JP, A) JP-A JP-A-4-120666 (JP, A) JP-A-10-50844 (JP, A) JP-A-10-65008 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21 / 82 H01L 27/092 H01L 27/118 G06F 17/50 658

Claims (8)

(57) [Claims] 1. A semiconductor integrated circuit designing apparatus for designing a semiconductor integrated circuit by using a master slice, wherein each device in an electric circuit to be designed into the semiconductor integrated circuit is formed on the master slice. Allocating means for allocating an element, and power supply wiring for supplying power to an allocated element to which a power supply voltage is to be supplied, avoiding other allocated elements, and the wiring path cannot be found. A power supply wiring means that is left unwired; an unwired detection means that detects an unwired power supply wiring after the power supply wiring is completed by the power supply wiring means; Means for adding allocation prohibition information to the allocated elements, and the allocation of allocated elements to which the allocation prohibition information has been added. Not a allocation changing means for changing to another unassigned element, the power wiring unit after reallocation assignment changing means, the apparatus for designing a semiconductor integrated circuit which is characterized in that the power line again. 2. The semiconductor integrated circuit designing apparatus, further comprising:
A short-circuit detecting means for detecting a power supply wiring which may be short-circuited with another wiring; and for the power supply wiring detected by the short-circuit detecting means, an assigned element whose wiring to a terminal may cause a short circuit with the power supply wiring. 2. The semiconductor integrated circuit designing apparatus according to claim 1, further comprising: an element detecting unit for detecting, wherein the allocation prohibiting unit adds the allocation prohibition information to the allocated element detected by the element detecting unit. 3. A semiconductor integrated circuit designing apparatus for designing a semiconductor integrated circuit using a master slice, wherein each of the elements in an electric circuit to be designed into the semiconductor integrated circuit is formed on the master slice. Allocating means for allocating elements that are assigned, and adding priority to each wiring area set in advance on the master slice, the priority indicating the preferential use of the wiring area with a smaller number of allocated elements And a wiring means for performing wiring by using the wiring area according to the priority added to each wiring area. 4. The device for designing a semiconductor integrated circuit, wherein the priority adding means includes: a number of elements formed in each wiring area; and a number of elements assigned by the allocating means in the wiring area. 4. A calculating means for calculating a ratio with a number, wherein the priority adding means adds a priority to each wiring area based on the calculated ratio.
An apparatus for designing a semiconductor integrated circuit according to the above. 5. A semiconductor integrated circuit designing method for designing a semiconductor integrated circuit using a master slice, wherein each element in an electric circuit to be designed in the semiconductor integrated circuit is formed on the master slice. The allocation step of allocating the elements that are present, and the power supply wiring for supplying power to the allocated elements to which the power supply voltage is to be supplied, avoiding the other allocated elements, and the wiring path cannot be found. In the power supply wiring process, which is left unconnected, the power supply wiring process is completed, and after the power supply wiring is completed, the unwired power detection process detects the unwired power supply wiring. The assignment prohibition step of adding the assignment prohibition information to the already assigned elements, and the assignment of the assigned element to which the assignment prohibition information has been added. And allocation changing step of changing to another unassigned element, after allocation assignment change changing step, a method of designing a semiconductor integrated circuit, comprising a rewiring step of performing power line again. 6. The method of designing a semiconductor integrated circuit, further comprising, after the power supply wiring in the power supply wiring step and before the start of the assignment prohibition step, the other of the power supply wirings in the power supply wiring step A short-circuit detection step of detecting a power supply wiring that may be short-circuited; and, for the power supply wiring detected in the short-circuit detection step, an element detection of detecting an assigned element whose wiring to a terminal may cause a short circuit with the power supply wiring. 6. The method for designing a semiconductor integrated circuit according to claim 5, further comprising the step of: allocating the allocation prohibition information to the allocated element detected in the element detecting step. 7. A semiconductor integrated circuit designing method for designing a semiconductor integrated circuit using a master slice, wherein each element in an electric circuit to be designed in the semiconductor integrated circuit is formed on the master slice. An assignment step of allocating elements that have been assigned, and a priority addition for each wiring area preset on the master slice, the priority indicating the preferential use of a wiring area with a smaller number of allocated elements. A method for designing a semiconductor integrated circuit, comprising: a step; and a wiring step of performing wiring by using a wiring area according to a priority added to each wiring area. 8. The method for designing a semiconductor integrated circuit, wherein the priority adding step includes: determining a number of elements formed in each wiring area; 8. The semiconductor integrated circuit according to claim 7, further comprising a calculating step of calculating a ratio with the number, wherein in the priority adding step, a priority is added to each wiring region based on the calculated ratio. Design method.