JP3202215B2 - Storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device, and more particularly to request control between a system control device and a storage device, and in particular, to transfer N bytes M times (N × M) from a system control device. This is related to busy control of the L interleave operation.

[Conventional technology]

Conventionally, in this type of storage device, N bytes of data are sent from a system controller M times in a time series during a write operation, and N bytes of data are sent to a system controller in a time series during a read operation. Since the data is sent M times, the cycle time of the bank having different N × M write / read operations is M clock times (M ^T
Abbreviated).

[Problems to be solved by the invention]

Conventional storage device described above, the N × M write or a read operation different banks, since reception time of the next request is in fixed ^{M T, N × M N ×} M read after write operation operation, or in the case of N × M write operation after N × M read operation, the next request is disadvantage that not accepted below M ^T.

[Means for solving the problem]

The storage device according to the present invention is capable of writing / writing data from a system controller.
In a storage device that performs an interleave operation of block transfer in response to a read request request, a plurality of banks, one write unit and one read unit provided in the plurality of banks, and one of the plurality of banks Identification means for identifying whether a previous request for one of the plurality of banks is a write instruction or a read instruction, and identifying whether a subsequent request is a write instruction or a read instruction for another of the plurality of banks. The previous request is a write command and the subsequent request is a read command, or
Continue if the previous request is a read command and the subsequent request is a write command,
Operation is prohibited if the previous request is a write instruction and the subsequent request is a write instruction, or if the previous request is a read instruction and the subsequent request is a read instruction. Busy control means.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings. In this embodiment, N bytes are transferred twice and interleaved twice.

1 and 2, when a request 13, a command 14, and an address 12 are transferred from the system control device, the main control circuit 4 identifies a bank, and requests the bank request.
Generates 19A or 19B.

In the case of the read operation, the address of the memory matrix circuit 9A or 9B is specified via the address control circuit 3, 7A or 7B, and at the same time, the timing control circuit 8A or 8B is activated by the bank request 19A or 19B, and the timing signal 23A
Alternatively, when 23B is sent to the memory matrix circuit 9A or 9B, the read data 21A or 21B is read from this circuit 9A or 9B, and sent to the system control device via the read data control circuit 6A or 6B or 2.

At this time, N-byte data 11 is transmitted to the system control device twice in a time series. In the case of a write operation, N-byte data 10 sent twice in a time series from the system controller by the same control passes through the write data control circuit 1, 5A or 5B and is stored in the memory in a time series. Written in the matrix circuit 9A or 9B.

FIG. 2 shows only a portion of the busy control circuit in the main control circuit 4 which controls the cycle time between different banks.

FIG. 3 is a timing chart showing the operation of FIG. For example, as shown in FIG. 3, when the first request 13 is a write command for bank 0 and the request 13 for the next clock cycle is a write command for bank 1,
Since data in N-byte units is sent in time series,
Since the second data of the previous request and the first data of the subsequent request overlap, a malfunction occurs.

Therefore, such a sequence operation is prohibited by setting the busy error signal 4C0 to logic “1”.

Therefore, as shown in FIG. 3, the first request 13 is a write command of the bank 0 and the request 13 of the second clock.
Is a write command for bank 1, a busy error signal
4C0 becomes logic "0" and continues operation.

When the first request 13 is a write command of bank 0 and the request 13 of the next clock cycle is a read command of bank 1 as shown in FIG. 4, the following operation is performed.
In the write operation to bank 0 in response to the preceding write request 13, N-byte write data 10
Is transmitted to the write data control circuit 1 twice in time series at every clock, and the N-byte write data 16 transferred twice is written to the memory matrix circuit 9A via the write data control circuit 5A.

In a read operation from the bank 1 in response to the subsequent read request 13, the N-byte read data is transmitted twice in time series for each clock in one request per clock.
9B, and sent to the read data control circuit 6B.
The transfer N-byte read data 17B is transferred to the system controller via the read data control circuit 2.

As described above, since the first and second times of the preceding write operation are both in the bank 0 and the first and second times of the subsequent read operation are in the bank 1, the write data and the read data operate completely independently. Therefore, there is no conflict and no malfunction occurs. At this time, the busy error signals 4C0 to 4C3 are logical
Since it is '0', the operation continues.

In the present embodiment, the case of N bytes twice transfer 2 interleave is described. In the case of a write command of bank 0, a request for bank 0 is issued for one clock, and an operation of transferring N-byte write data twice is performed. This is an operation in which one bank is transferred twice.

In the read command of bank 0, N-byte read data is read twice from bank 0, and in the read command of bank 1, N-byte read data is read twice from bank 1.

The case where the previous request is a write command of bank 0 and the subsequent request is a write command of bank 1 is referred to as “A case”, and the previous request is a write command of bank 0 and the subsequent request is The case of the read command of bank 1 is referred to as “B case”.

The “A case” is a case where data conflicts in the write data control circuit 1 or the read data control circuit 2 and a busy error signal occurs, and the “B case” does not conflict in these circuits and a busy error signal occurs. There is no case.

The following description will be given on the assumption that FIG. 2 shows only the part controlling the cycle time between different banks as described above, and the part controlling the cycle time between the same banks is not shown. , Before and after the read command, the second read data of the preceding request and the first read data of the subsequent request compete in the read data control circuit 2, so that a busy error signal is generated.
Case ".

FIG. 2 does not show the case of the preceding read command of bank 0 and the succeeding read command of bank 0. In the case where the preceding request is a write command for bank 1 and the subsequent request is a read command for bank 0, the cycle time between different banks is controlled. From FIG. 2, the busy error signals 4C0, 4C1, 4C2, and
4C3 is all logical '0', which is “B case”. As described above, in the B case, the preceding is the write command of bank 0, the latter is the read command of bank 1, the previous is the write command of bank 1,
The latter describes the read command of bank 0, but it is clear that the B case is the case where the preceding two cases are the read command and the latter are the write command.

〔The invention's effect〕

As described above, according to the present invention, in a storage device that performs an interleave operation of block transfer, a write command and a read command are identified by identifying whether a previous request and a subsequent request of a different bank are a write command or a read command. In the case of an instruction or a combination of a read instruction and a write instruction, the cycle time can be shortened.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a circuit diagram showing details of a main control circuit shown in FIG. 1, and FIGS. 3 and 4 are storage devices shown in FIG. 6 is a timing chart showing the operation of FIG. 1,5A, 5B… write data control circuit, 2, 6A, 6B… read data control circuit, 3, 7A, 7B… address control circuit, 4… main control circuit, 8A, 8B… timing control Circuit, 9A, 9B… Memory matrix circuit, 10, 16, 20A, 20B… Write data, 11, 17A, 17B, 21A, 21B… Read data, 12, 18, 22A, 22
B: Address, 23A, 23B ... Timing signal, 24, 25 ...
... control signal, 13 ... request, 14 ... command, 5 ...
… Reply, 19A, 19B …… Bark request, 400,401…
... Decoders, 420 to 423 ... Registers.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 12/06 540 G06F 12/06 550

Claims (1)

(57) [Claims] 1. A storage device for performing an interleave operation of block transfer in response to a write / read request request from a system control device, comprising: a plurality of banks; and one writing means provided in the plurality of banks. And 1
Read means for identifying whether a previous request to one of the plurality of banks is a write instruction or a read instruction, and wherein a subsequent request is a write instruction or a read instruction to another of the plurality of banks. Identification means for identifying whether the command is a command, and wherein the previous request is a write command and the subsequent request is a read command, or the previous request is a read command and the subsequent request is If the command is a write command, the operation is continued, and the previous request is a write command and the subsequent request is a write command, or the previous request is a read command and the And a busy control unit for prohibiting the operation when the request is a read command.