JP3202369B2 - Read-only memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a read-only memory, and more particularly, to a read-only memory requiring high-speed reading.

[0002]

2. Description of the Related Art A conventional read-only memory of this type is:
As shown in FIG. 4, one memory cell 1 is selected by selecting a specific word line 101 by the X decoder 2 corresponding to a memory cell array including a plurality of memory cells 1, ON / OF of the memory cell 1
The information of F is read by the sense amplifier 7 via the Y selector 6.

[0003]

In the above-mentioned conventional read-only memory, when one memory cell 1 is selected and the ON / OFF information of the memory cell 1 is read by the sense amplifier 7, a word is read. When the line 101 is selected, the word line 101 is usually formed of polysilicon, and the parasitic resistance 20 and the parasitic capacitance 21 are interposed therebetween. Therefore, the word line 101 depends on the time constant of the parasitic resistance 20 and the parasitic capacitance 21. There is a problem that a time delay occurs, and the parasitic capacitance 22 also exists in the bit line 102. Therefore, in order to select the bit line 102 and read the information of the memory cell 1 by the sense amplifier 7, There is a problem that it takes time to charge up the parasitic capacitance 22 of the line 102.

For this purpose, the ON / OFF of the memory cell 1 is required.
It is difficult to reduce the time (access time) required for reading the information by the sense amplifier 7. Conventionally, in order to shorten the access time, it has been considered to change the time constant of the word line 101. However, it is not easy to change the physical constant. And X decoder 2
Are arranged in large numbers. Similarly, the bit line 102 is also divided into a plurality of Y selectors 6 and other means.

Therefore, in order to shorten the access time, word lines and bit lines are divided and a large number of X decoders and Y decoders are arranged, resulting in an increase in the chip area of the read-only memory. There are drawbacks.

[0006]

According to a first aspect of the present invention, there is provided a read-only memory which activates a memory array comprising a large number of read-only memory cells and a corresponding word line of the memory array corresponding to an input X address. And a Y selector for electrically connecting a corresponding bit line of the memory array to a sense amplifier in accordance with the input Y address, and a plurality of Y addresses corresponding to one X address. in sequentially read read only memory information of the memory cell selected by the X address and the Y address by switching a predetermined period the memory cell prior to activating the pre Symbol word line when it detects a change in the X address Is characterized by having means for precharging the bit line.

[0007]

[0008]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. As shown in FIG. 1, in the present embodiment, a plurality of memory cells 1 forming a memory cell array correspond to a plurality of word lines 101 and a plurality of bit lines 102.
, An X decoder 2, a pulse generation circuit 3, a bias circuit 4, and a plurality of NMOS transistors 5 arranged corresponding to each bit line 102.

In FIG. 1, an address signal _Am is input to an X decoder 2 and a pulse generation circuit 3. In the pulse generating circuit 3, by detecting a change in the address signal A _m, the pulse signal phi _p is output. This pulse signal φ _p is input to the gate of the NMOS transistor 5 arranged on each bit line 102. Each of these NMOS
The source of the transistor 5 is connected to the corresponding bit line 1
02 is connected to the drain is connected to the output terminal of the bias circuit 4 is set to a bias voltage V _p.

2 (a), 2 (b), 2 (c), 2 (d),
(E), (f) and (g) are timing charts showing the operation in the present embodiment, where the address signal _Am , the address signal _An , the level on the word line 101, and the pulse signal φ are respectively shown. _{p represents} the level of the bit line 102 when the ON cell is selected, the level of the bit line 102 when the OFF cell is selected, and the signal waveform of the sense amplifier 7.

[0012] As evidenced by Figures 1 and 2, in response to a change in the address signal A _m, the pulse signal phi _p becomes between "H" level for a predetermined time T _p, NMOS transistor 5 is ON State, whereby each bit line 1
02 is precharged respectively to the potential of the bias voltage V _p. Then, the pulse signal V _p in the later T _p becomes "L" level, respectively NMOS transistor 5 of the state of OFF by this. The aforementioned fixed time T
The _p, X decoder 2 selected by the address signal A _m
, That is, the switching time of the word line 101, the memory cell 1 selected by the word line 101 is determined after the time T _p , so that the memory cell 1 does not reach the bias voltage V _p. a plurality of bit lines 102 which are precharged by the oN / OFF memory cell 1 selected by the word line 101, a state that holds the attenuation or bias voltage V _p to the ground potential level.

Therefore, the information of the plurality of memory cells 1 is simultaneously supplied to the plurality of bit lines 102 with the bias voltage V
_p, in order to be taken out as the amplified to the ground potential level data, by switching only the Y selector 6 connected to the bit lines 102 by the address signal A _n,
It is possible to easily and quickly access information in a plurality of memory cells 1. In addition, since the plurality of NMOS transistors 5 corresponding to each bit line 102 share a gate signal with each other, the read-only semiconductor memory can be realized with a smaller occupied area. Further, by setting the size of the NMOS transistor 5 to be small, it is possible to realize a smaller area.

FIG. 3 is a block diagram showing a second embodiment of the present invention. As shown in FIG. 3, this embodiment, corresponding to the plurality of word lines 101 and a plurality of bit lines 102, a plurality of memory cells 1 forming the memory cell array, address signal A ₄ to A _n X decoder 2 corresponding to
And NMO corresponding to the four bit lines 102, respectively.
Y selector 6-1 including S transistor 17 and four NMOS transistors 19, and NMOS transistors 18 and 4 corresponding to four bit lines 102, respectively.
Selector 6-2 including two NMOS transistors 19
, A Y decoder 9 corresponding to the address signals A ₀ and A ₁ , inverters 8, 13 and 14, an address transition detection circuit (hereinafter referred to as an ATD circuit) 10, a NAND
Circuits 11 and 12 and four bit lines 102 each
NMOS transistors 15 arranged corresponding to
And four NMOS transistors 16 and an NMOS transistor 1 provided corresponding to each Y selector 6.
7 and 18. Note that four NMs
The drain of the OS transistor 15 and four NMOS transistors 16 are both connected to the voltage V _p.

In FIG. 3, an address signal A ₃ is transmitted from the AT
Is input to the D circuit 10, detects and signals output changes in address signals A ₃ in ATD circuit 10,
Input to NAND circuits 11 and 12. These N
In the AND circuit 11 and 12 are logical product taken by decoding an inverted signal respectively by the inverter 8 of the address signals A ₃ and the address signal A _3, the output is inverted in inverter 13 and 14, respectively, signals The signals are output as φ _p2 and a signal φ _p1 , and input to the gates of the four NMOS transistors 16 and the gates of the four NMOS transistors 15, respectively. Thus, the bit line 102 to which the four NMOS transistors 15 and the four NMOS transistors 16 are connected is selected by the address signal A _{3 and} the inverted signal of the address signal A ₃ , respectively.

[0016] Therefore, by the address signal A ₃ is switched, by either of the NMOS transistor 15 or 16, to the bit line 102 is precharged to a bias voltage V _p, as mentioned above, the digit lines 102 information of the memory cell is amplified, via an address signal a ₀ and a ₁ in the Y-decoder 9, by switching the Y-selector 6-1 and 6-2, and facilitates the information of the memory cell 1 of 4 addresses min Speed Can be accessed. Thus, it is apparent that the chip area of the read-only memory is reduced.

[0017]

As described above, according to the present invention, a pulse signal acting as a gate signal is generated in response to a change in a specific address signal input, and a pulse corresponding to a memory cell array is generated via the gate signal. By fixing each bit line to a predetermined bias potential, the speed of reading information from the corresponding memory cell can be improved, and further, the chip area can be reduced. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a timing chart showing an operation in the first embodiment.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a block diagram showing a conventional example.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 memory cell 2 X decoder 3 pulse generator 4 bias circuit 5, 15 to 19 NMOS transistor 6, 6-1, 6-2 Y selector 7 sense amplifier 8, 13, 14 inverter 9 Y decoder 10 ATD circuit 11, 12 NAND Circuit 20 Parasitic resistance 21 Parasitic capacitance 22 Bit line capacitance

Claims (1)

(57) [Claims] 1. A memory array comprising a large number of read-only memory cells, an X decoder for activating a corresponding word line in the memory array in response to an input X address, and a memory in response to an input Y address. A Y-selector for electrically connecting a corresponding bit line of the memory array to a sense amplifier, and switching a plurality of Y-addresses corresponding to one X-address by selecting the X-address and the Y-address. in sequentially read read only memory information of the memory cell, and characterized in that it comprises means for pre-charging the bit lines for a predetermined period the memory cell prior to activating the pre Symbol word line when it detects a change in the X address Read-only memory.