JP3203048B2 - Semiconductor device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a structure of a MOS transistor and an isolation region between adjacent transistors and a method of manufacturing the structure.

[0002]

2. Description of the Related Art The miniaturization of LSIs requires 10 ⁸ to 10
Proceeding until 10 ⁹ elements are formed, M
The gate length of the OS transistor is scaled to 0.6 to 0.3 μm. Accordingly, in the isolation using LOCOS as an isolation method between adjacent transistors, bird's beak cannot be suppressed, so that the isolation width cannot be reduced. A trench isolation method for isolating a transistor is used.

FIG. 7 shows a conventional MOS using trench isolation.
FIG. 8 is a diagram of the transistor viewed obliquely from above, and FIG. 8 is a diagram (cross-sectional view taken along the plane bb ′ in FIG. 7) when a contact hole portion is crossed in the gate width direction of the transistor.
FIG. 9 is a view when a gate portion is crossed in the gate width direction of the transistor (a cross-sectional view taken along the line cc 'in FIG. 7). Further, FIG. Figure when crossing the hall (d in FIG. 7)
-D 'plane).

In these figures, reference numeral 1 denotes a semiconductor substrate (hereinafter, referred to as a substrate) made of a P-type single crystal; 2, a trench portion for separating an element formation region formed on the substrate 1; 4 is an insulating film buried in the trench portion 2, 5 is a source / drain portion of this transistor, 6 is a gate oxide film, 7 is a side wall, and 8 is a gate polysilicon. And 9 is an interlayer film (omitted in FIG. 7), 10 is a contact hole, 1
Reference numeral 1 denotes Al for wiring (omitted in FIGS. 7 and 9).

Next, a conventional manufacturing method will be described with reference to FIG. First, As ⁺ and B are formed on a P-type semiconductor substrate 1.
^After the island layer 3 is formed by performing ion implantation of ⁺ , P ^{+ and the} like, photolithography and patterning of the trench are performed, and the substrate 1 is directly etched to form the trench isolation portion 2 (FIG. 11A )).

Thereafter, the trench 2 is made of SiO 2, Si
3 Fill with an insulating film 4 such as N4, form a gate insulating film 6, cover with gate polysilicon, photoengraving of the gate,
After patterning and etching to form the gate electrode 8, ion implantation is performed to form the source / drain portion 5. Thereafter, an insulating film is provided on the entire surface, and sidewalls 7 are formed on both side walls of the gate electrode 8 by etch back (FIG. 11B).

Thereafter, an interlayer insulating film 9 is covered over the entire surface, photolithography, patterning, and etching of the contact are performed to form a contact hole 10, and a metal such as Al, W or the like is entirely filled so as to fill the contact hole 10. Then, photolithography, patterning, and etching of the wiring are performed to form the wiring 11 (FIG. 11C).

[0008]

As described above, in the conventional manufacturing method, since the edge of the trench is rectangular,
There has been a problem that there is a large amount of leakage current due to the edge of the trench.

Further, with the miniaturization of MOS transistors, there has been a problem that the contact hole area on the source / drain portion of the MOS transistor is reduced, the contact contact resistance is increased, and a circuit delay is caused.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a semiconductor device capable of suppressing a leak current at an edge portion of a trench and reducing a contact resistance, and a method of manufacturing the same. The purpose is to:

[0011]

The semiconductor device according to the present invention has a smooth structure in which the edges of the trench portion and the source / drain portions have a curvature.

In a method of manufacturing a semiconductor device according to the present invention, a mountain-shaped structure is formed by providing a curvature at an edge of a trench portion on a surface of a semiconductor substrate and a portion to be an active layer on the surface of the semiconductor substrate. It was done.

Further, the method of manufacturing a semiconductor device according to the present invention includes a step of forming a groove in a trench isolation portion of a semiconductor substrate, a step of forming a silicon nitride film substantially at the center of a transistor formation portion on the semiconductor substrate, forming a field oxide film having a curvature where to be the active layer of the edge and the surface of the semiconductor substrate on the semiconductor substrate surface of the groove is performed, a field oxide, silicon nitride film and the fee
Removing the silicon oxide film and forming the semiconductor substrate on the semiconductor substrate.
Filling the trench with an insulating film for trench isolation , forming a gate insulating film and a gate electrode, performing ion implantation using the gate electrode as a mask, forming source and drain portions, and forming an interlayer film. And photolithography and etching for the contact hole, and a step of forming a contact portion with a metal for wiring on the source and drain portions having a curvature on the surface of the semiconductor substrate.

Further, the method for manufacturing a semiconductor device according to the present invention further comprises the step of substantially forming the transistor forming portion on the semiconductor substrate.
A step of forming a silicon nitride film at the center , a step of performing field oxidation to form a field oxide film having a curvature where an active layer is to be formed on the surface of the semiconductor substrate, and removing the silicon nitride film and the field oxide film. Forming a groove in a trench isolation portion of the semiconductor substrate by etching, embedding the groove with a trench isolation insulating film, forming a gate insulating film and a gate electrode, and ionizing the gate electrode using the gate electrode as a mask. Do the injection,
Forming a source / drain portion, forming an interlayer film, performing photolithography and etching for a contact hole, and forming a source having a curvature on a semiconductor substrate surface;
Forming a contact portion with a metal for wiring in the drain portion.

[0015]

According to the present invention, since the trench isolation edge has a smooth structure having a curvature, the leakage current on the substrate surface of the trench can be reduced. Further, since the source and drain portions also have a structure having a curvature, the contact area of the contact on the substrate surface can be made larger than the contact hole area, and the contact resistance can be reduced. In addition, the sub-threshold swing (S.FACTOR) becomes smaller.

Further, according to the present invention, as described above, a curvature is provided at the edge of the trench portion on the surface of the semiconductor substrate and where the active layer is to be formed on the surface of the semiconductor substrate to form a mountain-shaped structure. Therefore, an element which can reduce the leak current at the edge of the trench and the contact resistance can be obtained.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing the structure of a semiconductor device according to an embodiment of the present invention, that is, the structure of a MOS transistor and an element isolation portion, viewed obliquely from above, and FIG. FIG. 3 is a diagram (cross-sectional view taken along the line bb ′ in FIG. 1), and FIG. 3 is a diagram (cross-sectional view taken along the line cc ′ in FIG. 1) when the gate portion is crossed in the gate width direction. FIG. 3 is a diagram when the gate portion and the contact hole portion are crossed in the gate length direction (a cross-sectional view taken along the dd 'plane in FIG. 1).

In these figures, 1 is a semiconductor substrate made of a P-type single crystal, 2 is a trench portion for separating an element formation region formed on the substrate 1, and 3 is a P-type formed on the substrate 1.
4 is an insulating film buried in the trench portion 2, 5 is a source / drain portion of this transistor, 6 is a gate oxide film, 7 is a sidewall, 8 is a gate polysilicon, and 9 is an interlayer. A film (omitted in FIG. 1), 10 is a contact hole, 11 is Al for wiring
(Omitted in FIGS. 1 and 3).

The MOS transistor of this embodiment is characterized in that the edge on the semiconductor surface of the trench 2 in the element isolation portion has a curvature, and the source / drain portion 5 has a structure having a curvature in the gate width direction. is there.

A curvature is provided at the edge of the trench,
An example of a method of manufacturing a transistor having a source / drain portion also having a curvature and an element isolation portion will be described with reference to FIG.
In FIG. 5, the same reference numerals as those in FIGS. 1 to 4 denote the same or corresponding parts, 12 denotes a silicon nitride film, and 13 denotes a field oxide film.

First, As +, P +,
The island portion 3 is formed by ion implantation of B + or the like. After that, photolithography and patterning of the separation portion are performed, and the Si substrate is etched to dig a rectangular groove. After that, a silicon nitride film is provided on the entire surface, and the transistor on the Si substrate 1 is formed by photolithography and patterning.
The silicon nitride film 12 is left almost at the center of the region to be formed (FIG. 5A).

Thereafter, field oxidation is performed to form a field oxide film 13 with a curvature around the trench portion 2 and in the active layer serving as the source and drain portions, and then the silicon nitride film 12 is removed (FIG. 5B). .

After the field oxide film is removed by etching, the trench isolation portion 2 is made of, for example, SiO 2
, Si3 N4, BPSG, etc., are buried with an insulating film for trench isolation (FIG. 5C). Note that this step is not required when the field oxide film is used as an insulating film for trench isolation.

Thereafter, a gate insulating film 6 is formed, a gate polysilicon is covered, photolithography, gate patterning and etching are performed to form a gate 8 (FIG. 5D).
).

Thereafter, ions such as As ⁺ , P ⁺ , B ⁺ are implanted to form an N ⁻ source / drain portion 5, a sidewall is formed on the gate 8, and the N ⁺ source is again implanted by ion implantation. After the formation of the drain portion, an interlayer insulating film 9 is covered, a contact hole 10 is opened, and Al,
The contact is made with W or the like, and the wiring 11 is formed. Thereby, the element shown in FIG. 1 is obtained.

FIG. 6 shows another example of a method of manufacturing a transistor and an element isolation portion in which a curvature is provided at an edge portion of a trench and a curvature is also provided in a source / drain portion.
In the drawings, the same reference numerals as those in FIGS. 1 to 4 and 5 denote the same or corresponding parts.

Hereinafter, the manufacturing method will be described. First,
After ion implantation of As +, P +, B +, etc. on the Si substrate 1 to form the island portion 3, a silicon nitride film is provided on the entire surface, and photolithography and etching are used to form the Si base.
The silicon nitride film 12 is patterned substantially at the center of the region where the transistor is formed on the plate 1 (FIG. 6A).

Next, field oxidation is performed to form a field oxide film 13 with a curvature in the active layer serving as the source and drain portions (FIG. 6B).

Thereafter, the silicon nitride film 12 and the field oxide film 13 are removed by etching, and thereafter, photolithography and patterning for forming a trench isolation portion are performed, and the Si substrate is directly etched to dig a rectangular groove, thereby separating the trench. The part 2 is formed. Then, the trench isolation part 2
Is buried with an insulating film for trench isolation such as SiO2, Si3 N4, BPSG or the like (FIG. 6C).

Thereafter, a gate insulating film 6 is formed, a gate polysilicon is covered, photolithography, gate patterning and etching are performed to form a gate 8 (FIG. 6D).
).

[0031] Then, As ^+, P ^+, ion implantation is performed such B ^+, N ^- source, after creating a drain portion 5, the side wall is formed in the gate 8, again, N ⁺ source ion implantation After the formation of the drain portion, an interlayer insulating film 9 is covered, a contact hole 10 is opened, and Al,
The contact is made with W or the like, and the wiring 11 is formed. Thus, the device having the structure shown in FIG. 1 is completed.

According to the present embodiment as described above, the edge of the trench isolation portion on the surface of the semiconductor substrate has a curvature, so that the leakage current at the edge portion of the trench can be reduced.

Further, since the source and drain portions are also formed to have a curvature, the contact portion on the source and drain portions can have a contact area larger than the cross-sectional area of the contact hole, thereby reducing the contact resistance. Thus, an element which can sufficiently cope with miniaturization of a transistor can be obtained. In addition, since the source and drain sections have curvature, sub-threshold swing (S.FACTOR)
Can be reduced, and the performance of the element can be improved.

[0034]

As described above, according to the present invention, the edge portion of the semiconductor substrate surface of the trench isolation portion and the source
Since the drain portion has a mountain-shaped structure with a curvature, it is possible to reduce the leak current at the edge of the trench, to increase the contact area on the source and drain portions, and to reduce the contact resistance. Can,
Further, since the source / drain portion has a mountain-shaped structure, the sub-threshold swing (S.FACTOR) can be reduced, and there is an effect that a high-performance MOS transistor and an element having isolation can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram of a structure of a semiconductor device according to an embodiment of the present invention as viewed obliquely from above.

FIG. 2 is a cross-sectional view of the semiconductor device of FIG. 1 taken along the line bb '.

FIG. 3 is a cross-sectional view of the semiconductor device of FIG. 1 taken along the line cc ′.

FIG. 4 is a cross-sectional view of the semiconductor device of FIG. 1 taken along a dd ′ plane.

FIG. 5 is a diagram showing a method of manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 6 is a view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 7 is a diagram of a structure of a conventional semiconductor device viewed obliquely from above.

8 is a cross-sectional view of the semiconductor device of FIG. 7 taken along the line bb '.

9 is a cross-sectional view of the semiconductor device of FIG. 7 taken along the line cc '.

10 is a cross-sectional view of the semiconductor device of FIG. 7 taken along the line dd '.

FIG. 11 is a view illustrating a conventional method of manufacturing a semiconductor device.

DESCRIPTION OF THE REFERENCE NUMERALS 1 semiconductor substrate 2 element isolation trench 3 island 4 trench filling insulating film 5 source / drain part 6 gate insulating film 7 sidewall 8 gate polysilicon 9 interlayer insulating film 10 contact hole 11 Al wiring 12 silicon nitride Film 13 Field oxide film

Continuation of front page (56) References JP-A-2-260660 (JP, A) JP-A-3-167838 (JP, A) JP-A-3-132073 (JP, A) JP-A-4-99385 (JP) , A)

Claims (4)

(57) [Claims] 1. A semiconductor device having a MOS transistor composed of a gate polysilicon provided on a semiconductor substrate via a gate insulating film, a source and a drain, and a trench isolation structure for isolating adjacent MOS transistors. In the above, the edge of the trench isolation portion on the surface of the semiconductor substrate and the portion to be the active layer on the surface of the semiconductor substrate have a smooth shape having a curvature, and the active layer and the wiring for the portion having the curvature on the surface of the semiconductor substrate have A semiconductor device, wherein the metals are connected. 2. A semiconductor device having a MOS transistor comprising a gate polysilicon provided on a semiconductor substrate via a gate insulating film, a source and a drain, and a trench isolation structure for separating adjacent MOS transistors. Forming a mountain-shaped structure by providing a curvature at an edge of the trench portion on the surface of the semiconductor substrate and at a portion to be an active layer on the surface of the semiconductor substrate; and forming an interlayer film and forming a contact hole. Photoengraving for
After etching, a part with a curvature on the semiconductor substrate surface
Forming a contact portion with a wiring metal on the active layer of the semiconductor device. 3. A semiconductor device having a MOS transistor composed of a gate polysilicon provided on a semiconductor substrate via a gate insulating film, a source and a drain, and a trench isolation structure for isolating adjacent MOS transistors. Forming a groove in a trench isolation portion of a semiconductor substrate by etching; forming a silicon nitride film substantially at the center of a transistor formation portion on the semiconductor substrate; and performing field oxidation to form the semiconductor substrate in the groove. Forming a field oxide film having a curvature on an edge on the surface and an active layer on the surface of the semiconductor substrate; and removing the silicon nitride film and the field oxide film .
That step and, above the semiconductor substrate in a groove formed trench isolation insulating film
Burying in a step of forming a gate insulating film and the gate electrode, ion implantation of the gate electrode as a mask, source, and forming a drain portion, an interlayer film, the pictures for the contact hole Plate making,
After etching, a part with a curvature on the surface of the semiconductor substrate
Method for producing a minute source, a semiconductor device characterized by comprising a step of forming a contact portion of a metal wiring to the drain unit. 4. A semiconductor device having a MOS transistor composed of a gate polysilicon provided on a semiconductor substrate via a gate insulating film, a source and a drain, and a trench isolation structure for isolating adjacent MOS transistors. Forming a silicon nitride film substantially at the center of a transistor forming portion on a semiconductor substrate; and performing field oxidation to form a field oxide film having a curvature where the active layer should be on the surface of the semiconductor substrate. A step of removing the silicon nitride film and the field oxide film; a step of forming a groove in a trench isolation portion of the semiconductor substrate by etching; a step of filling the groove with a trench isolation insulating film; And a step of forming a gate electrode, and ion implantation using the gate electrode as a mask. There, a step of forming a source, a drain portion, an interlayer film, photolithography for the contact hole,
After etching, a part with a curvature on the semiconductor substrate surface
Method for producing a minute source, a semiconductor device characterized by comprising a step of forming a contact portion of a metal wiring to the drain unit.