JP3203715B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP3203715B2 JP3203715B2 JP32599191A JP32599191A JP3203715B2 JP 3203715 B2 JP3203715 B2 JP 3203715B2 JP 32599191 A JP32599191 A JP 32599191A JP 32599191 A JP32599191 A JP 32599191A JP 3203715 B2 JP3203715 B2 JP 3203715B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- amorphous
- amorphous semiconductor
- layer
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 117
- 238000000034 method Methods 0.000 title claims description 40
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 239000000758 substrate Substances 0.000 claims description 19
- 239000010408 film Substances 0.000 claims description 11
- 239000010409 thin film Substances 0.000 claims description 11
- 238000005224 laser annealing Methods 0.000 claims description 8
- 238000010276 construction Methods 0.000 claims 1
- 239000012535 impurity Substances 0.000 description 18
- 238000009792 diffusion process Methods 0.000 description 14
- 238000002425 crystallisation Methods 0.000 description 9
- 230000008025 crystallization Effects 0.000 description 7
- 230000007547 defect Effects 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 6
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Recrystallisation Techniques (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体基板上に形成さ
れる半導体集積回路や、絶縁基板上に形成される液晶表
示装置などに用いられる、半導体装置の製造方法に関す
る。The present invention relates to a method for manufacturing a semiconductor device used for a semiconductor integrated circuit formed on a semiconductor substrate, a liquid crystal display device formed on an insulating substrate, and the like.
【0002】[0002]
【従来の技術】従来の技術における半導体装置の製造方
法を、図2を用いて説明する。まず、図2(a)に示す
ように、半導体基板201上に絶縁薄膜202を積層
し、フォトエッチングにより前記絶縁薄膜202を開孔
した後、前記絶縁薄膜202の開孔部203より不純物
イオン204をイオン打ち込み法により導入し、前記半
導体基板201中に非晶質の不純物拡散層を形成した
後、熱処理を行なうことにより、前記導入された不純物
イオン204の活性化及び結晶化された不純物拡散層2
05の形成を行う。その後、図2(b)に示すように、
前記開孔部203を覆うように第1の半導体層206を
積層、パターニングを行なう。その後、第2の絶縁膜2
07を積層し、前記開孔部203の形成に用いられたの
と同様な方法で、前記第2の絶縁膜207に開孔部20
8を形成し、全面に第2の半導体層209を積層し、パ
ターニングを施し図2(c)となし、半導体装置が完成
する。2. Description of the Related Art A conventional method for manufacturing a semiconductor device will be described with reference to FIG. First, as shown in FIG. 2A, an insulating thin film 202 is laminated on a semiconductor substrate 201, and the insulating thin film 202 is opened by photoetching. Is implanted by ion implantation, an amorphous impurity diffusion layer is formed in the semiconductor substrate 201, and then heat treatment is performed to activate and crystallize the impurity diffusion layer 204. 2
05 is formed. Then, as shown in FIG.
A first semiconductor layer 206 is laminated so as to cover the opening 203 and is patterned. Then, the second insulating film 2
07 is stacked on the second insulating film 207 in the same manner as that used for forming the opening 203.
8 is formed, a second semiconductor layer 209 is stacked on the entire surface, and is patterned to obtain the structure shown in FIG. 2C, thereby completing the semiconductor device.
【0003】[0003]
【発明が解決しようとする課題】近年、半導体集積回路
の発達にともなって、半導体集積回路に用いられる半導
体装置の高集積化及び低消費電力化に対する要望が強ま
ってきている。In recent years, with the development of semiconductor integrated circuits, there has been a growing demand for higher integration and lower power consumption of semiconductor devices used in semiconductor integrated circuits.
【0004】しかしながら、前述の従来の技術では、い
くつかの問題点が指摘されている。その内の一つは、半
導体層を接続するときの電圧降下である。先の従来の技
術により半導体層を接続した場合、接続される半導体層
の接続面は、半導体原子の周期条件が乱れた部分であ
り、数多くの格子欠陥が存在する。この数多くの格子欠
陥を含む半導体層をそれぞれ接続した場合、前述の格子
欠陥がトラップ準位を形成し、それによって抵抗が負荷
されるため、電圧を印加した場合キャリアーがこれにト
ラップされ電圧降下が起る。この電圧降下を小さくする
ことが、半導体装置の低消費電力化及び高性能化にとっ
て重要な課題である。また、半導体層を接続する方法と
して、金属を配線層として用いる方法も検討されている
が、この場合、プロセスの複雑化や微細化の困難さが指
摘されている。また接続する半導体層の間に高融点金属
や半導体との化合物を挿入する方法も考えられている
が、この場合にもプロセスの複雑さが問題となってい
る。[0004] However, in the above-mentioned conventional technology, some problems are pointed out. One of them is a voltage drop when connecting the semiconductor layers. When the semiconductor layers are connected by the above conventional technique, the connection surface of the semiconductor layer to be connected is a portion where the periodic condition of the semiconductor atoms is disturbed, and there are many lattice defects. When the semiconductor layers including many lattice defects are connected to each other, the above-described lattice defects form trap levels, thereby loading the resistance. Therefore, when a voltage is applied, carriers are trapped by this, and a voltage drop occurs. Happens. Reducing the voltage drop is an important issue for reducing the power consumption and improving the performance of the semiconductor device. As a method for connecting the semiconductor layers, a method using a metal as the wiring layer has been studied. In this case, however, it has been pointed out that the process is complicated and difficult to miniaturize. A method of inserting a compound having a high melting point metal or a semiconductor between semiconductor layers to be connected has also been considered, but also in this case, the complexity of the process is a problem.
【0005】本発明は、このような従来の技術における
問題点を解決するもので、その目的とするところは、微
細化及び高集積化、高性能化が可能な半導体装置の製造
方法を提供するところにある。The present invention has been made to solve the above-mentioned problems in the prior art, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of miniaturization, high integration, and high performance. There.
【0006】[0006]
【課題を解決するための手段】本発明は、絶縁基板上あ
るいは絶縁薄膜上に、第1の非晶質半導体層を形成する
工程と、前記第1の非晶質半導体層上に絶縁膜を形成
し、コンタクトホールを開孔する工程と、前記絶縁膜上
に第2の非晶質半導体層を形成し、前記コンタクトホー
ルを介して前記第1の非晶質半導体層と前記第2の非晶
質半導体層とを接続する工程と、レーザーアニール法ま
たはRTA法により前記第1の非晶質半導体層及びこれ
に接続した前記第2の非晶質半導体層の結晶化を行う工
程とを有することを特徴とする。さらに、前記第1の非
晶質半導体層を第1導電型で形成し、前記第2の非晶質
半導体層を第2導電型で形成することを特徴とする。さ
らに、前記第1の非晶質半導体層と前記第2の非晶質半
導体層を同一導電型で形成することを特徴とする。According to the present invention, there is provided a process for forming a first amorphous semiconductor layer on an insulating substrate or an insulating thin film, and forming an insulating film on the first amorphous semiconductor layer. Forming and opening a contact hole; forming a second amorphous semiconductor layer on the insulating film; and forming the first amorphous semiconductor layer and the second non-conductive layer through the contact hole. Connecting the first amorphous semiconductor layer and the second amorphous semiconductor layer connected to the first amorphous semiconductor layer by a laser annealing method or an RTA method. It is characterized by the following. Further, the first amorphous semiconductor layer is formed with a first conductivity type, and the second amorphous semiconductor layer is formed with a second conductivity type. Further, the first amorphous semiconductor layer and the second amorphous semiconductor layer are formed with the same conductivity type.
【0007】また、絶縁基板上あるいは絶縁薄膜上に、
第1の非晶質半導体層を形成する工程と、前記第1の非
晶質半導体層上に絶縁膜を形成し、コンタクトホールを
開孔する工程と、前記絶縁膜上に第2の非晶質半導体層
を形成し、前記コンタクトホールを介して前記第1の非
晶質半導体層と前記第2の非晶質半導体層とを接続する
工程と、前記第1の非晶質半導体層及びこれに接続した
前記第2の非晶質半導体層の結晶化を行う工程とを有す
ることを特徴とする。さらに、前記第1の非晶質半導体
層を第1導電型で形成し、前記第2の非晶質半導体層を
第2導電型で形成することを特徴とする。さらに、前記
第1の非晶質半導体層と前記第2の非晶質半導体層を同
一導電型で形成することを特徴とする。On an insulating substrate or an insulating thin film,
A step of forming a first amorphous semiconductor layer, a step of forming an insulating film on the first amorphous semiconductor layer and opening a contact hole, and a step of forming a second amorphous film on the insulating film. Forming a semiconductor layer and connecting the first amorphous semiconductor layer and the second amorphous semiconductor layer through the contact hole; And crystallization of the second amorphous semiconductor layer connected to the semiconductor device. Further, the method is characterized in that the first amorphous semiconductor layer is formed of a first conductivity type, and the second amorphous semiconductor layer is formed of a second conductivity type. Further, the first amorphous semiconductor layer and the second amorphous semiconductor layer are formed with the same conductivity type.
【0008】[0008]
【作用】本発明の半導体装置の製造方法によれば、半導
体基板中の非晶質の不純物拡散層と非晶質半導体層、ま
たは絶縁基板上あるいは絶縁薄膜上の第1の非晶質半導
体層と第2の非晶質半導体層とを、非晶質の状態で接続
させた後、同時に結晶化させることにより、結晶欠陥の
少ない半導体接合が形成できる。半導体層の結晶化の方
法としてレーザーアニール法やRTA法を用いることに
より、短時間で結晶化が可能であり、かつ不純物の拡散
も小さく抑えることができるため、微細化が可能であ
る。また、レーザーアニール法やRTA法で結晶化を行
うと、非晶質半導体層は1度溶融してから結晶化するた
め、接合部分での接合欠陥がより少なくなる。従って、
半導体基板中の非晶質の半導体層あるいは第1の非晶質
半導体層が第1導電型で、これに接続する非晶質半導体
層が第2導電型である場合、良好なPN接合が形成で
き、また両方が同じ導電型である場合は、接合端面での
トラップが少なく、良好なコンタクト特性を有する接合
を形成することができる。これによって半導体装置の低
消費電力化及び高性能化が実現できる。According to the method of manufacturing a semiconductor device of the present invention, an amorphous impurity diffusion layer and an amorphous semiconductor layer in a semiconductor substrate, or a first amorphous semiconductor layer on an insulating substrate or an insulating thin film. By connecting the second amorphous semiconductor layer to the second amorphous semiconductor layer in an amorphous state and then simultaneously crystallization, a semiconductor junction with few crystal defects can be formed. By using a laser annealing method or an RTA method as a method for crystallizing a semiconductor layer, crystallization can be performed in a short time and diffusion of impurities can be suppressed to be small, so that miniaturization is possible. In addition, when crystallization is performed by a laser annealing method or an RTA method, the amorphous semiconductor layer is melted once and then crystallized, so that bonding defects at a bonding portion are further reduced. Therefore,
When the amorphous semiconductor layer or the first amorphous semiconductor layer in the semiconductor substrate is of the first conductivity type and the connected amorphous semiconductor layer is of the second conductivity type, a good PN junction is formed. When both are of the same conductivity type, a trap having few contact points at the joint end face and having good contact characteristics can be formed. Thus, lower power consumption and higher performance of the semiconductor device can be realized.
【0009】[0009]
【実施例】本発明の半導体装置の製造方法の実施例の1
つを、製造工程ごとの素子断面図により詳しく説明して
ゆく。まず、図1(a)に示すように、半導体基板10
1上に第1の絶縁薄膜102を形成し、フォトエッチン
グ法により開孔部103を形成した後、前記開孔部10
3より、不純物イオン104を導入し、不純物拡散層1
05を形成する。前記絶縁薄膜102は、熱酸化法や熱
窒化法、あるいは常圧CVD法や減圧CVD法、プラズ
マCVD法、ECRプラズマCVD法、スパッタ法等に
より形成された二酸化珪素膜や窒化珪素膜、あるいはこ
れらの組合せにより形成される。また、前記不純物イオ
ン104の導入には、イオン注入法やイオンドーピング
法等の、イオン打ち込み法などが用いられる。また、前
記半導体基板101中に形成した非晶質の不純物拡散層
105の導電型は、前記導入した不純物イオンによって
決定される。ついで、図1(b)に示すように、全面に
第1の非晶質半導体層106を積層、パターニングし
て、前記半導体基板101中の非晶質の不純物拡散層1
05と前記第1の非晶質半導体層106とを、前記開孔
部103に於て接続する。前記第1の非晶質半導体層1
06は、減圧CVD法やプラズマCVD法あるいはEC
RプラズマCVD法などによって形成される。また、前
記第1の非晶質半導体層106は、多結晶半導体層で形
成した後、イオンを導入して非晶質化したものでも構わ
ない。また、前記非晶質の半導体層106の導電型は、
前記半導体基板101中の非晶質の不純物拡散層105
と同じ導電型でも良いし、逆導電型でも良い。その後、
第2の絶縁薄膜107を積層し、再びフォトエッチング
法を用いて開孔部108を形成した後、第2の非晶質半
導体層109を積層し、前記開孔部108に於て、前記
第1の非晶質半導体層106と接続する。この状態が図
1(c)である。前記第2の非晶質半導体層は、前記第
1の非晶質半導体層と同様にして形成される。その後、
図1(d)に示すように、全面にレーザービーム110
を照射し、前記半導体基板101中の非晶質の不純物拡
散層105と前記第1の非晶質半導体層106及び前記
第2の非晶質半導体層110の結晶化を、すべて同時に
行い、所望の半導体装置が完成する。結晶化の手段とし
て、本実施例で説明したレーザーアニール法の他に、熱
アニール法やランプアニール法などがあるが、短時間で
結晶化が可能であり、そのため不純物の拡散が少ない等
の理由により、レーザーアニール法あるいはRTA法を
用いるのが望ましい。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 of a method for manufacturing a semiconductor device according to the present invention.
One will be described in detail with reference to element cross-sectional views for each manufacturing process. First, as shown in FIG.
1, a first insulating thin film 102 is formed, and an opening 103 is formed by a photo-etching method.
3, the impurity ions 104 are introduced and the impurity diffusion layer 1 is introduced.
05 is formed. The insulating thin film 102 is formed of a silicon dioxide film or a silicon nitride film formed by a thermal oxidation method, a thermal nitridation method, a normal pressure CVD method, a low pressure CVD method, a plasma CVD method, an ECR plasma CVD method, a sputtering method, or the like. Are formed by a combination of For the introduction of the impurity ions 104, an ion implantation method such as an ion implantation method or an ion doping method is used. The conductivity type of the amorphous impurity diffusion layer 105 formed in the semiconductor substrate 101 is determined by the introduced impurity ions. Next, as shown in FIG. 1B, a first amorphous semiconductor layer 106 is laminated and patterned on the entire surface to form an amorphous impurity diffusion layer 1 in the semiconductor substrate 101.
05 and the first amorphous semiconductor layer 106 are connected at the opening 103. The first amorphous semiconductor layer 1
06 is a low pressure CVD method, a plasma CVD method or an EC method.
It is formed by an R plasma CVD method or the like. Further, the first amorphous semiconductor layer 106 may be formed of a polycrystalline semiconductor layer and then made amorphous by introducing ions. The conductivity type of the amorphous semiconductor layer 106 is as follows:
Amorphous impurity diffusion layer 105 in the semiconductor substrate 101
Or the opposite conductivity type. afterwards,
After the second insulating thin film 107 is stacked and the opening 108 is formed again by using the photoetching method, the second amorphous semiconductor layer 109 is stacked, and the second amorphous semiconductor layer 109 is stacked at the opening 108. One amorphous semiconductor layer 106 is connected. This state is shown in FIG. The second amorphous semiconductor layer is formed in the same manner as the first amorphous semiconductor layer. afterwards,
As shown in FIG. 1D, a laser beam 110
And crystallization of the amorphous impurity diffusion layer 105, the first amorphous semiconductor layer 106, and the second amorphous semiconductor layer 110 in the semiconductor substrate 101 are all performed simultaneously. Is completed. As a means of crystallization, in addition to the laser annealing method described in this embodiment, there are a thermal annealing method and a lamp annealing method, and the like. Therefore, it is desirable to use a laser annealing method or an RTA method.
【0010】本実施例に於いて、基板中の非晶質の不純
物拡散層と第1の非晶質半導体層との接続、それから第
1の非晶質半導体層と第2の非晶質半導体層との接続の
両方について、それぞれ説明したが、もちろんどちらか
一方の接続だけでも良いし、逆にもっと多層の接続に於
いても適用できることは自明である。In this embodiment, a connection between an amorphous impurity diffusion layer in a substrate and a first amorphous semiconductor layer, and then a first amorphous semiconductor layer and a second amorphous semiconductor Although both connections with layers have been described, it is obvious that only one of the connections may be used, and conversely, the present invention can be applied to a multilayer connection.
【0011】[0011]
【発明の効果】本発明の半導体装置の製造方法によれ
ば、半導体基板中の不純物拡散層と第1の半導体層、ま
たは、第1の半導体層と第2の半導体層の全てを、非晶
質の状態で接続し、その後一括して結晶化を行うことに
より、それぞれの接続部での接合欠陥を減少させること
ができる。この結晶化の方法としてレーザーアニール法
を用いた場合には、非晶質の半導体層は1度溶融してか
ら結晶化するため、接続部での接合欠陥を更に減少させ
ることができる。この様にして第1導電型の非晶質半導
体層と第2導電型の非晶質半導体層を接続した場合に
は、その接続部に於いて、理想的なPN接合が形成でき
る。また、同じ導電型の非晶質半導体層同士を接続した
場合には、トラップ準位が小さくコンタクト抵抗の小さ
い接合ができる。すなはち、半導体装置の接続部分での
電圧降下を小さくすることができ、半導体装置の低消費
電力化及び高性能化が実現できる。また、結晶化の方法
としてレーザーアニール法あるいはRTA法を用いた場
合、照射時間が極短時間であるため、同一基板上に形成
されている半導体装置に含まれた不純物の拡散を抑える
ことができ、半導体装置の微細化が可能になる。従っ
て、本発明の半導体装置の製造方法を用いることによ
り、半導体装置の微細化及び低消費電力化、高性能化が
可能になる。According to the method of manufacturing a semiconductor device of the present invention, the impurity diffusion layer and the first semiconductor layer, or the first semiconductor layer and the second semiconductor layer in the semiconductor substrate can all be made amorphous. By performing connection in a quality state and then performing crystallization collectively, it is possible to reduce bonding defects at each connection portion. When a laser annealing method is used as the crystallization method, the amorphous semiconductor layer is melted once and then crystallized, so that the junction defects at the connection portion can be further reduced. When the first conductive type amorphous semiconductor layer and the second conductive type amorphous semiconductor layer are connected in this manner, an ideal PN junction can be formed at the connection portion. Further, when amorphous semiconductor layers of the same conductivity type are connected to each other, a junction having a small trap level and a small contact resistance can be formed. That is, a voltage drop at a connection portion of the semiconductor device can be reduced, and low power consumption and high performance of the semiconductor device can be realized. When a laser annealing method or an RTA method is used as a crystallization method, the irradiation time is extremely short, so that diffusion of impurities contained in a semiconductor device formed over the same substrate can be suppressed. In addition, miniaturization of a semiconductor device becomes possible. Therefore, by using the method for manufacturing a semiconductor device of the present invention, miniaturization, low power consumption, and high performance of the semiconductor device can be achieved.
【図1】 本発明の実施例により説明した半導体装置の
製造方法に於ける、製造工程ごとの素子断面図。FIG. 1 is a sectional view of an element for each manufacturing step in a method for manufacturing a semiconductor device described according to an embodiment of the present invention.
【図2】 従来の技術の半導体装置の製造方法に於け
る、製造工程ごとの素子断面図。FIG. 2 is a sectional view of an element in each manufacturing process in a conventional semiconductor device manufacturing method.
101,201・・・半導体基板 102,202・・・第1の絶縁薄膜 103,108,203,208・・・開孔部 104,204・・・不純物イオン 105,205・・・非晶質の不純物拡散層 106,206・・・第1の非晶質半導体層 107,207・・・第2の絶縁薄膜 109,209・・・第2の非晶質半導体層 110・・・レーザービーム 205・・・結晶化した不純物拡散層 206・・・第1の半導体層 209・・・第2の半導体層 101, 201 ... semiconductor substrate 102, 202 ... first insulating thin film 103, 108, 203, 208 ... aperture 104, 204 ... impurity ions 105, 205 ... amorphous Impurity diffusion layers 106, 206: first amorphous semiconductor layer 107, 207: second insulating thin film 109, 209: second amorphous semiconductor layer 110: laser beam 205 ..Crystalized impurity diffusion layer 206 ... first semiconductor layer 209 ... second semiconductor layer
Claims (3)
の非晶質半導体層を形成する工程と、前記第1の非晶質Forming the first amorphous semiconductor layer, and the first amorphous
半導体層上に絶縁膜を形成し、コンタクトホールを開孔Form an insulating film on the semiconductor layer and open a contact hole
する工程と、前記絶縁膜上に第2の非晶質半導体層を形And forming a second amorphous semiconductor layer on the insulating film.
成し、前記コンタクトホールを介して前記第1の非晶質Forming the first amorphous layer through the contact hole.
半導体層と前記第2の非晶質半導体層とを接続する工程A step of connecting a semiconductor layer and the second amorphous semiconductor layer
と、レーザーアニール法またはRTA法により前記第1And the first by laser annealing or RTA.
の非晶質半導体層及びこれに接続した前記第2の非晶質Amorphous semiconductor layer and the second amorphous layer connected thereto
半導体層の結晶化を行う工程とを有することを特徴とすCrystallizing the semiconductor layer.
る半導体装置の製造方法。Semiconductor device manufacturing method.
で形成し、前記第2の非晶質半導体層を第2導電型で形And forming the second amorphous semiconductor layer in the second conductivity type.
成することを特徴とする請求項1記載の半導体装置の製2. The manufacturing of a semiconductor device according to claim 1, wherein
造方法。Construction method.
非晶質半導体層を同一導電型で形成することを特徴とすCharacterized in that the amorphous semiconductor layer is formed with the same conductivity type.
る請求項1記載の半導体装置の製造方法。A method for manufacturing a semiconductor device according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32599191A JP3203715B2 (en) | 1991-12-10 | 1991-12-10 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32599191A JP3203715B2 (en) | 1991-12-10 | 1991-12-10 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05160024A JPH05160024A (en) | 1993-06-25 |
| JP3203715B2 true JP3203715B2 (en) | 2001-08-27 |
Family
ID=18182882
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32599191A Expired - Lifetime JP3203715B2 (en) | 1991-12-10 | 1991-12-10 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3203715B2 (en) |
-
1991
- 1991-12-10 JP JP32599191A patent/JP3203715B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05160024A (en) | 1993-06-25 |
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