JP3203733B2 - MOSIC and its manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOSIC (integrated circuit) and a method of manufacturing the same, and more particularly to an MOIC comprising a ring-shaped or arc-shaped gate electrode MOSFET.
The present invention relates to an SIC and a method for manufacturing the SIC.

[0002]

2. Description of the Related Art FIGS. 6 and 7 are sectional views of a first half and a second half of a process for explaining a conventional method of manufacturing a MOSFET (field effect transistor) which is one of MOSICs.

FIGS. 6 and 7 show an MO showing the manufacturing process.
The SFET has a structure in which the gate and the channel are orthogonal. In manufacturing a conventional MOSFET in which a gate and a channel are orthogonal to each other, first, as shown in FIG.
A gate oxide film (SiO ₂ ) 2 is formed thereon by thermal oxidation, and a polysilicon (poly-Si) film 3 serving as a gate electrode and a SiO ₂ film 4 are sequentially formed on the gate oxide film 2 by a CVD method. Then, as shown in FIG. 6B, SiO 2 is formed by RIE (reactive ion etching).
₂ film 4 and poly-Si film 3 are sequentially patterned to form a SiO ₂ film pattern 4a and a gate electrode 3a.
To form

Next, after depositing SiO ₂ on the entire surface by the CVD method, etch back is performed by anisotropic etching, and as shown in FIG. 6C, the SiO ₂ side wall 6 is formed on the side wall of the gate electrode 3a. To form

Next, as shown in FIG. 7A, polysilicon (poly-Si) is deposited on the entire surface to form a second layer electrode, and a second poly-Si film 8 is formed.
Thereafter, as shown in FIG. 7B, the second poly-Si
Unnecessary portions of the film 8 are removed by patterning by RIE to form second layer electrodes 8a and 8b. FIG. 8 is a perspective view of a main part of FIG.

[0006]

SUMMARY OF THE INVENTION
Layer electrode (poly-Si) 8a, in the patterning step to 8b, the SiO ₂ sidewalls 6 on the surfaces of, when the poly-Si etching residual film 9 as shown in FIG. 8 are present, the source electrode by the remaining film A short circuit occurs between the drain electrodes. Therefore, it is necessary to prevent the poly-Si film from being left on the side wall surface, and several hundred percent over-etching is required to sufficiently remove the poly-Si film. However, this over-etching must be stopped before the residual resist film on the flat portion disappears.

As described above, the side wall surface is made of poly.
The process margin is small because no residual film of -Si is generated and the resist film in the flat portion is not lost.

Accordingly, the present invention provides a method of forming a pol
It is an object of the present invention to provide a MOSIC that can operate even when y-Si is left and has an improved degree of integration, and a method for manufacturing the same.

[0009]

SUMMARY OF THE INVENTION The above-mentioned problem is solved by silicon.
Substrate and a predetermined thickness provided on the silicon substrate.
A ring-shaped gate oxide film and a gate oxide
Ring-shaped gate electrode made of first polysilicon film
And the insulation provided on top of this ring-shaped gate electrode
Film and a side wall of the ring-shaped gate electrode including the insulating film.
The insulating film sidewall and the insulating film sidewall
Of the ring-shaped gate electrode separated by
A first electrode bonded to the silicon substrate on the side, and an insulating film
Ring-shaped gate electrode separated by
A second electrode bonded to the silicon substrate outside the pole.
First, the first electrode is a drain electrode or a source electrode,
The second electrode is a source electrode or a drain electrode, and the first electrode
And the second electrode is formed on the insulating film and the insulating film sidewall.
Therefore, the silicon having a ring-shaped gate
A second polysilicon film was formed on the entire surface of the substrate.
After the etch back, the second poly after the etch back
Third polysilicon patterned on a silicon film
The problem is solved by a first MOSIC, which is made of a film .

[0010] The second MOSIC according to the present invention is a silicon MOSIC.
Substrate and a predetermined thickness provided on the silicon substrate.
A plurality of arc-shaped gate oxide films and a gate oxide
Arc-shaped gate electrode made of a first polysilicon film
And an insulating film provided on the arc-shaped gate electrode;
Insulation provided on the side wall of the arc-shaped gate electrode including this insulating film
The edge film sidewall and the insulating film sidewall
Silicon base inside the arcuate gate electrode
A plurality of first electrodes joined to the plate and an insulating film side wall;
Outside the arc-shaped gate electrode separated by
A second electrode joined to the recon substrate, and the first electrode
The pole is a source electrode and the second electrode is a drain electrode.
The first electrode and the second electrode are an insulating film and an insulating film size.
With an arc-shaped gate electrode separated by a
A second polysilicon film is formed on the entire surface of the silicon substrate.
After being formed, it is etched back.
Third poly patterned on the second polysilicon film
It is made of a silicon film.

[0011] Production method of MOSIC according to the present invention, a gate oxide film on a silicon substrate, the first polysilicon film 及
Sequentially forming a fine insulating film, the step of forming the insulating film and the first port <br/> Rishirikon insulating film film patterning the ring or arcuate gate electrode composed of the first polysilicon film When a step of forming a sidewall insulating film sidewall of the first polysilicon film including the insulating film, the gate
Gates other than gate electrode and insulating film sidewall
Step of exposing the silicon substrate surface by removing the oxide film
If, after forming the second polysilicon film on the entire surface of the silicon substrate, a step of etching back the polysilicon film, further etching back the second polysilicon film
The polysilicon film of the third and Patanigu after been formed a third polysilicon film on the entire surface of the silicon substrate
To and forming a source electrode and a drain electrode Te is characterized in.

[0012]

According to the first MOSIC of the present invention , the first MOSIC is provided.
Inside and outside of a ring-shaped gate electrode composed of a silicon film
First and second electrodes joined to the silicon substrate on the side
The first electrode and the second electrode are formed by insulating film sidewalls.
Ring-shaped first policy separated by
The entire surface of a silicon substrate with a recon film (gate electrode)
After the second polysilicon film is formed,
On the second polysilicon film after this etch back.
Made of a third polysilicon film patterned
It is. Therefore, there is a slope beside the insulating film sidewall.
It is possible to adopt a structure that leaves the second polysilicon film
Therefore, the source and drain electrodes of the MOSIC can be
When forming and patterning a single polysilicon film
In comparison with the above, the margin of the etching conditions for the self-aligned contact of these electrodes can be made wider . In addition, MOSIC utilizing self-aligned contacts
In addition to increasing the integration of
Wiring patterns can be flattened due to miniaturization.
Wear.

Further , according to the second MOSIC of the present invention ,
For example, when combining a plurality of FETs, the first MOSIC
Since the structure can be applied, if only inside the arcuate gate electrode
No external source / drain electrodes are self-aligned
Widening the margin of contact etching conditions
Can be. According to the MOSIC manufacturing method of the present invention,
The source and drain electrodes are formed as a single polysilicon film
Self-alignment compared to patterning and patterning
Widening the margin of contact etching conditions
Can be. Moreover, utilizing self-aligned contacts
Not only can increase the degree of integration of MOSIC,
Wiring pattern flattening due to miniaturization of MOSIC
Can be planned .

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a view showing one embodiment of a MOSFET (MOSIC) having a ring-shaped gate electrode according to the present invention. FIG. 1A is a top view, and FIG.
FIG. 2 is a sectional view taken along line A1-A2 of FIG.

As shown in FIGS. 1A and 1B,
This embodiment has a cylindrical drain electrode 18a, a ring-shaped (hollow cylindrical) source electrode 18b and a polysilicon gate electrode 13a as its main components, and is formed on both sides of the polysilicon gate electrode 13a and the SiO ₂ film pattern 14a thereon. A SiO ₂ sidewall 16 is provided on the wall, and a source region and a source electrode 18b of the silicon substrate 11 and a drain region and a drain electrode 18a of the silicon substrate 11 are respectively self-aligned on side surfaces of the SiO ₂ sidewall 16. Polysilicon (po
ly-Si) film 17a.

The MOSFET configured as shown in FIG.
Is poly-Si on the side surface of the SiO ₂ side wall 16.
Is not a problem even if the remaining film is present, and the margin of the etching condition can be widened.

FIGS. 2 and 3 are a first half process sectional view (including a perspective view) and a second half process sectional view, respectively, for explaining the method of manufacturing the MOSFET having the ring-shaped gate electrode according to the present invention shown in FIG. Is shown.

First, the MOSFET according to the present invention will be described with reference to FIG.
As shown in FIG. 2A and FIG.
After a silicon substrate 11 is subjected to ordinary thermal oxidation to form a gate oxide film 12 made of SiO ₂ having a thickness of 7 nm, polysilicon (poly-Si) having a thickness of 20 nm is formed by a CVD (chemical vapor deposition) method. 20 nm thick Si
O ₂ is deposited, and the inner diameter is about 0.35 by lithography.
After forming a ring-shaped (arc) -shaped resist pattern (not shown) having an outer diameter of about 0.80 μm and an opening 20, SiO ₂ and poly-Si are sequentially etched by RIE into a ring shape, _{A two-} layer pattern 14a and a polysilicon gate electrode 13a are formed, and then the resist pattern is removed. The etching gas used in the RIE is Freon (CF ₄ ) to which hydrogen is added when etching SiO ₂ , while Freon to which oxygen is added is used when etching poly-Si. Can be.

Next, as shown in FIG.
(Including the side wall surface of the silicon gate electrode)
More SiO_TwoIs deposited to a thickness of 15 nm and then freon
Etchback by RIE using a system gas
iO_TwoTo remove 20 nm_TwoSide wall 16
It is formed on the outer peripheral surface and inner peripheral surface of the ring gate. This RI
E during the etch-back by poly-Si gate
Pole 13a and SiO _TwoSiO under sidewall 16_Two
(Gate insulating film 12a)
Gate oxide film 12 is substantially removed.

Next, about 1% of dilute hydrofluoric acid (HF) is used for natural acid.
After the oxide film is removed, as shown in FIG.
Polysilicon (poly-Si) is deposited by
iO _TwoA 25 nm thick policy is formed above the film pattern 14a.
A recon film 17 is formed.

Next, the polysilicon film 17 is anisotropically etched from above (etch back by RIE).
To remove a thickness of about 35 nm (FIG. 3
(B)).

Next, polysilicon is deposited by CVD method.
lithography techniques and RI
The drain electrode (poly-S
i) 18a and a source electrode (poly-S
i) Form on 18b.

In the etching back of the polysilicon film 17 described with reference to FIG. 3B, the polysilicon film 17a remains on the side surface of the SiO ₂ side wall 16, but in this embodiment, the gate electrode has an arc shape. Therefore, no short circuit occurs in each of the source (S) / drain (D) regions.

FIG. 4 is a top view for explaining a pattern of another embodiment of a MOSFET having an arc-shaped gate electrode according to the present invention, and FIG. 5 is an equivalent circuit diagram of the pattern.

First, in FIG. 4, four FETs, ie, (1) to (4) are formed in parallel, and the source (S)
The electrodes serve as common electrodes for the FETs (1) to (4). Each of the FETs (1) to (4) has a gate electrode (G1), a drain electrode (D1), and a gate electrode (G2). ), Drain electrode (D2), gate electrode (G
3), drain electrode (D3), and gate electrode (G
4) a drain electrode (D4), the drain electrode (D1 to D4) and the source electrode (S) are each in self-aligned contact, and the gate electrode (G1 to G
4) is a normal contact.

FIG. 5 shows a case where the above-mentioned S is common.
One FET is an equivalent circuit formed in parallel.

Although the pattern shown in FIG. 4 has four FETs surrounding the source (S), the number of FETs is not limited, and a plurality of FETs such as three, five,. Alternatively, the present invention can be realized with two FETs and a dummy pattern.

[0029]

As described above , the first M of the present invention is used.
According to the OSIC, the phosphorus made of the first polysilicon film is used.
To the silicon substrate inside and outside the gate electrode
A first electrode and a second electrode.
The two electrodes are separated by an insulating film sidewall.
Ring-shaped first polysilicon film (gate electrode)
A second polysilicon film is formed on the entire surface of the silicon substrate
After formed and etched back, after this etch back
Of the third patterned on the second polysilicon film
It is made of a polysilicon film. With this configuration
A second port having a slope beside the insulating film sidewall.
Since it is possible to adopt a structure that leaves the silicon film, MO
The source and drain electrodes of the SIC are
Compared to the case of forming and patterning a capacitor film,
Ru can be widened the margin of etching conditions for self-aligned contacts et electrodes. Moreover, not only can the integration degree of the MOSIC be increased by utilizing the self-aligned contact, but also with the miniaturization of the MOSIC.
The wiring pattern can be flattened. Also book
According to the second MOSIC of the invention, a plurality of FETs are combined.
Since the structure of the first MOSIC can be applied when
Not only inside the arc-shaped gate electrode but also outside the source electrode /
Drain electrode is also self-aligned contact etching
The condition margin can be widened. MO of the present invention
According to the SIC manufacturing method, the first polysilicon film
Ring-shaped gate electrode and a ring-shaped or arc-shaped gate
At least on the side wall of the polysilicon film of the gate electrode
On the entire surface of a silicon substrate having an insulating film sidewall
Forming a second polysilicon film, and then forming a second polysilicon film;
Etch back the silicon film to form a second polysilicon film
Is further applied to the entire surface of the etched silicon substrate.
Polysilicon film, and then a third polysilicon film
Pattern the source and drain electrodes
It is made to form. This configuration allows these
Pattern the electrodes by forming a polysilicon film once
Compared to self-aligned contact
It is possible to increase the margin of the switching condition . Moreover,
Utilization of ru-a-line contacts for MOSIC integration
Not only can be improved, but also the MOSIC
It is possible to achieve a flattened wiring pattern as a result.

[Brief description of the drawings]

FIG. 1 shows an MO having a ring-shaped gate electrode according to the present invention.
FIG. 3 is a diagram illustrating an example of an SFET (MOSIC).

FIG. 2 shows an MO having a ring-shaped gate electrode according to the present invention.
It is a first half process figure of SFET (MOSIC).

FIG. 3 shows an MO having a ring-shaped gate electrode according to the present invention.
It is a latter half process drawing of SFET (MOSIC).

FIG. 4 shows a MOSF having an arcuate gate electrode according to the present invention.
It is a figure showing the pattern of other examples of ET.

5 is an equivalent circuit diagram of the MOSFET pattern shown in FIG.

FIG. 6 is a first half process diagram illustrating a conventional method for manufacturing a MOSFET.

FIG. 7 is a latter half process chart for describing a conventional method for manufacturing a MOSFET.

FIG. 8 is a perspective view of a main part of FIG. 7 (b).

[Explanation of symbols]

1,11 silicon substrate 2,12,12a gate oxide film 3,17,17a polysilicon (poly-Si) film 3a, 13a polysilicon gate electrode 4 SiO ₂ film 4a, 14a SiO ₂ film pattern 6,16 SiO ₂ side Wall 8 Second polysilicon (poly-Si) film 8a, 8b Second layer electrode 9 Poly-Si etching remaining film 18a Drain electrode (poly-Si) 18b Source electrode (poly-Si) 20 Opening

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) H01L 29/78 H01L 21/336

Claims (3)

(57) [Claims] A silicon substrate having a predetermined thickness provided on the silicon substrate;
A gate oxide film and a first polysilicon film provided on the gate oxide film
A ring-shaped gate electrode, an insulating film provided on the ring-shaped gate electrode, and a sidewall provided on the ring-shaped gate electrode including the insulating film.
Insulating film sidewalls and phosphorus separated by the insulating film sidewalls.
Bonded to the silicon substrate inside the gate electrode
A first electrode and phosphorus separated by the insulating film sidewall;
Bonded to the silicon substrate outside the gate electrode
A second electrode, wherein the first electrode is a drain electrode or a source electrode,
The second electrode is a source electrode or a drain electrode, and the first and second electrodes are separated by the insulating film and the insulating film sidewall.
Of silicon substrate with ring-shaped gate electrode
After the second polysilicon film is formed,
And the second polysilicon film after the etch back.
A MOSIC comprising a third polysilicon film patterned thereon. 2. A silicon substrate and a plurality of arcs of a predetermined thickness provided on the silicon substrate.
Gate oxide film and a first polysilicon film provided on the gate oxide film.
An arc-shaped gate electrode, an insulating film provided on the arc-shaped gate electrode, and an insulating film provided on the side wall of the arc-shaped gate electrode including the insulating film.
An edge film sidewall and an arc shape element-isolated by the insulating film sidewall
A plurality of parts joined to the silicon substrate inside the gate electrode
And an arc-shaped element separated by the insulating film sidewall.
Second joined before Symbol silicon substrate outside of the gate electrode
And a electrode, the first electrode is a source electrode, the second electrode
A drain electrode, wherein the first electrode and the second electrode are separated from each other by the insulating film and the insulating film sidewall;
Over the entire surface of the silicon substrate having the arc-shaped gate electrode
After the second polysilicon film is formed,
On the second polysilicon film after the etch back.
A MOSIC comprising a patterned third polysilicon film . 3. A silicon substrate on a gate oxide film, and forming first <br/> polysilicon film and the insulating film sequentially, the insulating film by patterning the insulating film and the first polysilicon film And a ring or arc made of the first polysilicon film
Forming a Jo gate electrode, forming an insulating film sidewall on the sidewall of the first polysilicon film includes the insulating film, other than the lower portion of the gate electrode and the insulating film sidewall
A step of exposing the silicon substrate surface by removing the gate oxide film, after forming a second polysilicon film on the entire surface of the silicon substrate, the step of etching back the polysilicon film
And the second polysilicon film is etched back.
And characterized in that it comprises the steps of by Patanigu polysilicon film of the third forming a source <br/> source electrode and a drain electrode after forming a third polysilicon film on the entire surface of the silicon substrate Of manufacturing MOSIC.