JP3204441B2 - Code error inserter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a code error inserter for artificially generating a code error according to predetermined code error occurrence pattern information and inserting the code error into a transmission path.

[0002]

2. Description of the Related Art Code error characteristics do not always occur constantly and may change with time. Further, in an error of a type in which a plurality of bits occur collectively (burst error), various occurrence patterns exist depending on the cause of occurrence. It is important to evaluate the influence of the temporal change of the bit error rate and the pattern of occurrence of a burst error on the communication device or communication quality when designing and evaluating a communication network.

[0003]

By the way, in order to insert a code error in real time, conventionally, the influence of a time change of a certain code error and a pattern of occurrence of a burst error on a communication apparatus or communication quality has been known. Is evaluated by computer simulation or the like, a signal in which a code error is added to an input signal is created, and this signal is used for evaluation. If the frame synchronization is lost in a frame synchronization type multiplexing device, etc., the information to be transmitted becomes unknown, so it is designed to transmit a fixed pattern code until frame synchronization is re-established. There is. It is also important to evaluate the effect of replacing a transmission signal with a fixed pattern on a communication device and communication quality when designing and evaluating a communication network.

However, when evaluating the influence of code replacement on a communication device or communication quality, conventionally, a signal in which a part of an input signal is code replaced by computer simulation or the like is created and used for evaluation. I have.

[0005] Therefore, in the above conventional example, there is a problem that it takes a lot of time to prepare an evaluation test, and there is a problem that only an input signal prepared in advance can be used in the evaluation test.

Conventionally, even when it is desired to perform comparison and evaluation on the spot by instantaneously switching code error occurrence pattern information (or replacement code generation pattern information) during a code error insertion operation (or a code replacement operation). However, since only an evaluation test in which input signals prepared in advance are switched and presented can be performed, there is a problem that bias is likely to occur in evaluation.

According to the present invention, it is possible to insert, in real time, at least one of a code error corresponding to an arbitrary code error generation pattern and a replacement code according to an arbitrary replacement code generation pattern into an arbitrary input signal. It is another object of the present invention to provide a code error inserter which can select one of a plurality of generation patterns and can switch even during a code error insertion operation or a code replacement operation.

[0008]

SUMMARY OF THE INVENTION The present invention provides a method for generating a code error.
If the bits constituting the pattern information are 0,
All bits of the specified fixed number of bits are free from errors
Means the bits constituting the above-mentioned code error occurrence pattern information.
If the bit is 1, the following bit sequence is used to
Compression that describes a code error pattern for a fixed number of bits
Code error occurrence pattern described by description format
And a code error generating means for outputting the presence or absence of a code error as a time series in bit units according to the input code error generation pattern information, and an input signal and an output signal of the code error generating means. , A signal adding means for performing addition by exclusive OR in bit units.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing a code error inserter WI1 according to a first embodiment of the present invention. The inserter WI1 has a code error generator 1 and a signal adder 2.

The code error generator 1 is provided with code error occurrence pattern information P1 in advance. According to the designated code error occurrence pattern information P1, the code error generator 1 uses the input start time of the input signal Si as a base point and corresponds to the current time. It outputs whether a code error has occurred or not, outputs "0" if "no code error", and outputs "1" if "a code error exists". This code error generator 1 outputs a code error time series C1, which is a binary time series that changes with time.

The signal adder 2 receives an input signal Si and a code error time series (a time series indicating whether a bit error has occurred in a bit unit) C1 and performs an exclusive OR operation in a bit unit. It is a logical OR operator and outputs an output signal So1.

Due to the nature of the exclusive OR operation, at the time when the code error time series C1 is "0" (time corresponding to "no code error"), the output signal So1 becomes the input signal Si.
At the time when the code error time series C1 is "1" (time corresponding to "the presence of a code error"), the output signal So1 has the sign of the input signal Si inverted. That is, the output signal So1 is a signal in which a code error corresponding to the code error occurrence pattern information P1 is inserted into the input signal Si.

That is, the code error insertion unit WI1 inputs the code error occurrence pattern information, and outputs the presence or absence of the code error occurrence as a time series in bit units according to the input code error occurrence pattern information. This is an example of a code error inserter having means and signal addition means for adding an input signal and an output signal of the code error generation means by exclusive OR in bit units.

FIG. 2 shows the configuration of the code error inserter WI1.
It is a figure which shows the example of the code error occurrence pattern information P1, the code error time series C1 corresponding to this code error occurrence pattern information P1, the input signal Si, and the output signal So1 in the above case.

In the code error occurrence pattern information P1 shown in FIG. 2, if "no code error" continues for 8 bits, these 8 bits are described by 1 bit of "0". , And 9 bits including a leading "1" and 8 bits including the code error ("0" for "no code error" and "1" for "with code error"). In this way, if "no code error" continues for 8 bits, the storage capacity can be compressed by describing the 8 bits as 1 bit of "0". Note that FIG.
The description method of the code error occurrence pattern shown in (1) is merely an example, and various other methods may be adopted.

FIG. 3 is a block diagram showing a code error inserter WI2 according to a second embodiment of the present invention.

The code error inserter WI2 has a plurality of code error generators 11, 12,..., 1n, code error generator selection means SEL2, and a signal adder 2.

Code error generators 11, 12,..., 1n
Are respectively different code error occurrence patterns P11,
, P1n are given in advance, and according to the given code error occurrence patterns P11, P12,..., P1n, code error time series C11, C12,.
C1n is output. Code error time series C11,
Each of C12,..., C1n is based on the input start time of the input signal Si, and determines whether a code error corresponding to the current time is "0" if "no code error", and "0" if "code error". For example, it is a signal output as "1", that is, a binary time series that changes with time. , C1n exist in the same number as the number of the code error generators 11, 12,..., 1n.

The selection means SEL2 of the code error generator designates an arbitrary one of a plurality of code error time series C11, C12,..., C1n and outputs it as a code error time series C1. .

The signal adder 2 receives the input signal Si and the code error time series C1, performs an exclusive OR operation for each bit, and outputs an output signal So2.

Due to the nature of the exclusive OR operation, at the time when the code error time series C1 becomes "0" (corresponding to "no code error"), the output signal So2 becomes equal to the input signal Si. At the time when the error time series C1 becomes “1” (corresponding to “with code error”), the output signal So2 is obtained by inverting the sign of the input signal Si. That is, the output signal So2 includes the code error occurrence pattern information P11, P12,
... A signal in which a code error corresponding to one piece of code error occurrence pattern information selected from P1n is inserted into the input signal Si. Here, the code error generators 11, 12, ..., 1
n are simultaneously operated, the code error occurrence pattern information P11, P12,.
1n can be switched and output.

In the example shown in FIG. 2, the code error occurrence pattern information P1 is
.., P1n, the code error time series C1 is replaced with the code error time series C11, C12,..., C1n, and the output signal So1 is replaced with the output signal So2.
The example shown in FIG. 2 is an example in the code error inserter WI2.

That is, the code error inserter WI2 inputs the code error occurrence pattern information, and outputs a plurality of bits for outputting the presence or absence of a code error as a time series in bit units according to the input code error occurrence pattern information. Code error generating means;
Selecting means for selecting one code error generating means from the plurality of code error generating means, and a signal for adding an input signal and an output signal of the selected code error generating means by exclusive OR in bit units It is an example of a code error inserter having addition means.

FIG. 4 is a block diagram showing a code error inserter WI3 according to a third embodiment of the present invention. The code error inserter WI3 has a permutation code generator 3 and a signal permuter 4.

The permutation code generator 3 receives the permutation code generation pattern information P2 in advance, and uses the input start time of the input signal Si as a base point according to the specified permutation code generation pattern information P2, and corresponds to the current time. Bit string to be replaced (replacement code consisting of finite length bit string) C
2 is output.

A permutation code C2 consisting of a bit string of finite length
Is a time series composed of flag information indicating “no replacement” when the replacement process is not performed and a bit string to be replaced when the replacement process is performed.

The signal replacement unit 4 outputs the input signal Si while the replacement code C2 composed of a finite length bit string indicates "no replacement processing", and outputs the finite length to be replaced while the replacement code C2 indicates "with replacement processing". It outputs a bit string. This output signal is the output signal So3 in FIG. The output signal So3 is
The signal is a signal obtained by inserting a replacement code corresponding to the replacement code generation pattern information P2 into the input signal Si.

That is, the code error inserter WI3 inputs the replacement code generation pattern information, and outputs the finite length bit string intermittently in accordance with the input replacement code generation pattern information. This is an example of a code error inserter including a signal replacement unit that replaces an input signal with the above-described bit sequence only while the replacement code generation unit is generating a bit sequence.

FIG. 5 shows the code error inserter WI3 shown in FIG.
, And the information P2
FIG. 10 is a diagram showing an example of a code error time series C2, an input signal Si, and an output signal So3 corresponding to.

In the example shown in FIG. 5, 8-bit continuous information of "no replacement" is described by 2 bits of "00", 8-bit continuous information of "with replacement" is described by 2 bits of "11", “No permutation code” of less than 8 bits or “with permutation code” of less than 8 bits is expressed by a total of 5 bits of 2 bits “01” or “10” and 3 subsequent bits indicating the bit length
Described in bits.

In the example shown in FIG. 5, a chain of "1" is always used as a finite-length bit string used for replacement regardless of the bit length. The description method of the replacement code generation pattern used in this example is merely an example, and various other methods are conceivable.

FIG. 6 is a block diagram showing a code error inserter WI4 according to a fourth embodiment of the present invention. The code error inserter WI4 includes a plurality of replacement code generators 31, 32,.
.., 3n, a signal replacement unit 5, and a selection unit 6 for a replacement code generator.

Each of the replacement code generators 31, 32,..., 3n has a different replacement code generation pattern P21,
, P2n are given in advance, and replacement codes C21, C22,..., C2n are respectively provided in accordance with the given code error occurrence patterns P21, P22,.
Is output. Replacement codes C21, C22, ...
.., C2n are bit strings (replacement codes composed of bit strings of finite length) for which the presence or absence of a replacement code corresponding to the current time is replaced based on the input start time of the input signal Si. Replacement code C2 consisting of a finite length bit string
Is the flag information indicating “no replacement” when the replacement process is not performed, and is a time series composed of a bit string to be replaced when the replacement process is performed. There are as many replacement codes C21, C22,..., C2n as bit strings of finite length, the same number as the number of replacement code generators 31, 32,.

The selecting means SEL4 of the permutation code generator selects any one of a plurality of permutation code time series C21, C22,..., C2n. The signal is sent to the signal adder 5 as a replacement code time series C2.

The signal replacing unit 4 selects the replacement code C2
While the input signal Si indicates "no replacement processing", the input signal Si is output as it is, and the selected replacement code C2 is "with replacement processing".
During this period, a bit string of a finite length to be replaced is output. This output signal is the output signal So4 in FIG. The output signal So4 is the replacement code generation pattern information P2.
1, P22,..., P2n are signals obtained by inserting replacement codes into the input signal Si.

Here, the selection means SEL of the permutation code generator
By selecting any one of the replacement code generators 31, 32,..., 3n with 4, the replacement code generation pattern information P21, P22,. If the replacement code generators 31, 32,..., 3n are operated at the same time, the code replacement occurrence patterns P21, P22,.

In the example of FIG. 5, the replacement code generation pattern information P2 is used instead of the replacement code generation pattern information P2.
.., C2n are displayed in place of the replacement code C2, and So4 is displayed instead of the output signal So3, as shown in FIG. The example is an example in the code error inserter WI4.

That is, the code error inserter WI4 receives the permutation code generation pattern information and outputs a plurality of permutation code intermittently and outputs a bit string of a finite length. Selecting means for selecting one of the permutation code generation means, and inputting the input signal with the bit string generated by the selected permutation code generation means only while the selected permutation code generation means generates the bit string. 5 is an example of a code error inserter having signal replacement means for replacement.

FIG. 7 is a block diagram showing a code error inserter WI5 according to a fifth embodiment of the present invention.

The mixed error occurrence pattern information P3 includes code error occurrence pattern information P1 due to sign inversion and replacement code occurrence pattern information P2 which is pattern occurrence information due to code replacement.
And inserter selection information SI5 for selecting the code error inserters WI1 and WI3.

The information separator 5 separates the mixed error occurrence pattern information P3 into code error occurrence pattern information P1, replacement code generation pattern information P2, and inserter selection information SI5. The code error occurrence pattern information P1 is used by the code error inserter WI1, and the replacement code generation pattern information P2 is used by the code error inserter WI3.

The information separator 5 always outputs inserter selection information SI5. The input signal Si is input to the code error inserter W
It is input to both I1 and WI3. For this reason, both the inserter WI1 and the inserter WI3 are always operating. The output signal of inserter WI1 and the output signal of inserter WI3 are
It is sent to the output inserter selector SEL5.

The output inserter selector SEL5 selects one of the output signal of the inserter WI1 and the output signal of the inserter WI3 according to the inserter selection information SI5, and outputs the selected output signal to the entire apparatus. As an output signal So5. As a result, the output signal So5 becomes a signal in which a code error and a replacement code are inserted into the input signal Si in accordance with the code error occurrence pattern information P3 including code replacement.

That is, the code error insertion unit WI5 inputs the code error occurrence pattern information and outputs the presence / absence of the code error as a time series in bit units according to the input code error occurrence pattern information. A first inserter comprising signal input means for adding an input signal and an output signal of the code error generating means by exclusive OR in a bit unit; and inputting permutation code generation pattern information. According to the input permutation code generation pattern information, a permutation code generation means for intermittently outputting a finite-length bit string, and an input signal is generated by the bit string only while the permutation code generation means generates the bit string. A second inserter constituted by signal replacement means for replacement and mixed error occurrence pattern information are input, and based on the input mixed error occurrence pattern information, Information separating means for creating code error occurrence pattern information, the replacement code generation pattern information, and inserter selection information for selecting the first inserter or the second inserter, and the inserter selection information Is an example of a code error inserter having an inserter selecting means for selecting the first inserter or the second inserter.

FIG. 8 is a block diagram showing a code error inserter WI6 according to a sixth embodiment of the present invention.

This inserter WI6 is basically the same as the inserter WI5, except that a selector SEL6 is provided instead of the selector SEL5 of the output inserter, and an information separator 51 is provided instead of the information separator 5. Is provided.

The selector SEL6 is provided with a code error inserter WI
1, WI3 as well as the code error inserters WI1, W1 as supply destinations for supplying the input signal Si.
I3 is selected. The information separator 51 calculates the code error occurrence pattern information P1 from the signal occurrence pattern information P3.
, Replacement code generation pattern information P2, and inserter selection information S
And I6. Inserter selection information SI6
Is a signal for selecting each output signal of the code error inserters WI1 and WI3, and a signal for selecting the code error inserters WI1 and WI3 as a supply destination for supplying the input signal Si.

In the inserter WI6, the input signal Si
Is a signal in which a code error according to the pattern information P3 of occurrence of a code error including code replacement and a replacement code are inserted.

FIG. 9 is a block diagram showing a code error inserter WI7 according to a seventh embodiment of the present invention.

The code error inserter WI7 includes code error inserters WI1, WI3, WI5 and WI6, and a code error inserter selecting means S for selecting one of these code error inserters.
EL7. Code error inserters WI1, WI3, W
Both I5 and WI6 are always operating.

In the code error inserter WI7, the output signal So7 is a signal obtained by inserting a code error corresponding to the selected code error occurrence pattern information P1, P2, P3 into the input signal Si, or replacing the input signal Si with a replacement code. It is. In addition, by operating each of the code error inserters WI1, WI3, WI5, and WI6 simultaneously, it is possible to switch the code error generation pattern even during the code error insertion operation.

In the code error inserter WI7, four code error inserters are provided.
Alternatively, five or more code error inserters may be provided. In this case, the code error inserters WI1, WI3, W
It is sufficient that there is a code error inserter including at least one of I5 and WI6.

FIG. 10 is a block diagram showing a code error inserter WI8 according to an eighth embodiment of the present invention.

The inserter WI8 is basically the same as the inserter WI7, except that a selector SEL8 is provided instead of the selector SEL7. Selector SEL8
Selects the output signals of the code error inserters WI1, WI3, WI5, and WI6. The code error inserters WI1, WI3,
WI5 and WI6 are selected.

In the code error inserter WI8, the output signal So8 is a signal obtained by inserting a code error corresponding to the selected code error occurrence pattern information P1, P2, P3 into the input signal Si, or replacing the input signal Si with a replacement code. It is. In addition, by operating each of the code error inserters WI1, WI3, WI5, and WI6 simultaneously, it is possible to switch the code error generation pattern even during the code error insertion operation.

In the code error inserter WI8, four code error inserters are provided.
Alternatively, five or more code error inserters may be provided. In this case, the code error inserters WI1, WI3, W
It is sufficient that there is a code error inserter including at least one of I5 and WI6.

That is, the code error inserters WI6, WI7,
The WI 8 selects a plurality of inserters including at least one of a first inserter, a second inserter, and a third inserter, and selects one of the plurality of inserters. And a selection means for outputting an output signal of the selected inserter. In this case, the first inserter inputs the code error occurrence pattern information, and outputs the presence or absence of the occurrence of the code error as a time series in bit units according to the input code error occurrence pattern information. Means for adding an input signal and an output signal of the code error generating means by a bit-wise exclusive OR operation, wherein the second inserter includes a permutation code generating means. A replacement code generating means for inputting pattern information and intermittently outputting a bit string of a finite length in accordance with the input replacement code generation pattern information; and inputting only while the replacement code generating means generates the bit string. An inserter comprising signal replacement means for replacing a signal with the bit string, wherein the third inserter includes the first inserter, the second inserter, and an input mixed error generating pattern. Information separating means for creating the code error occurrence pattern information, the replacement code generation pattern information, and the inserter selection information for selecting the first inserter or the second inserter based on the information; An inserter comprising: inserter selecting means for selecting the first inserter or the second inserter according to inserter selection information.

FIG. 11 shows a list of error occurrence methods, switching operations, and the like in the above embodiments.

In each of the above embodiments, any pattern can be used as a pattern for generating a code error to be inserted and a replacement code, and it operates in real time. As described above, since it is possible to insert a code error corresponding to an arbitrary code error occurrence pattern including code replacement into an arbitrary input signal, it is possible to insert codes of various generated patterns including code replacement caused by loss of frame synchronization. An evaluation test of the effect of an error on a communication device or communication quality can be applied to an unpredictable input signal, and can be executed in a short preparation period.

Furthermore, in the code error inserter WI2, any one of a plurality of previously prepared code error generation patterns can be switched and used in real time. In the code error inserter WI4, Any one of a plurality of replacement code generation patterns prepared in advance can be switched and used in real time. In the code error inserters WI5, WI6, WI7, and WI8, generated pattern information in which both code errors and replacement codes are mixed can be used. As described above, a plurality of code error occurrence patterns can be switched even during a code error insertion operation, so that comparison and evaluation between conditions becomes easy, and
Since the input signal does not need to be specified in advance, an unbiased evaluation test can be performed.

[0061]

According to the first aspect of the present invention, at least one of a code error corresponding to an arbitrary code error generation pattern and a replacement code corresponding to an arbitrary replacement code generation pattern is applied to an arbitrary input signal. When inserting in real time , any code error
This has the effect that the pattern can be compressed and described . According to the invention described in claims 2 to 8, optional
Input signal according to any code error occurrence pattern
Code error, replacement code according to any replacement code generation pattern
That at least one of the issues can be inserted in real time
This has the effect.

[Brief description of the drawings]

FIG. 1 shows a code error inserter W according to a first embodiment of the present invention.
It is a block diagram of I1.

FIG. 2 shows, in a code error inserter WI1, code error occurrence pattern information P1, a code error time series C1 corresponding to the code error occurrence pattern information P1, an input signal Si, and an output signal So1 in the above case. It is a figure showing an example.

FIG. 3 shows a code error inserter W according to a second embodiment of the present invention.
It is a block diagram of I2.

FIG. 4 shows a code error inserter W according to a third embodiment of the present invention.
It is a block diagram of I3.

FIG. 5 shows code error occurrence pattern information P2 in the code error inserter WI3 shown in FIG. 4, a code error time series C2 corresponding to this information P2, an input signal Si, and an output signal So3.
FIG.

FIG. 6 shows a code error inserter W according to a fourth embodiment of the present invention.
It is a block diagram of I4.

FIG. 7 shows a code error inserter W according to a fifth embodiment of the present invention.
It is a block diagram of I5.

FIG. 8 shows a code error inserter W according to a sixth embodiment of the present invention.
It is a block diagram of I6.

FIG. 9 shows a code error inserter W according to a seventh embodiment of the present invention.
It is a block diagram of I7.

FIG. 10 is a block diagram of a code error inserter WI8 according to an eighth embodiment of the present invention.

FIG. 11 shows a list of error occurrence methods, switching operations, and the like in each of the above embodiments.

[Explanation of symbols]

 WI1 to WI8: Code error inserter, 1, 11 to 1n: Code error generator, 2: Signal adder, 3, 31 to 3n: Permutation code generator, 4: Signal substituter, 5, 51: Information separator , Si: input signal, P1, P11 to P1n: code error occurrence pattern information, C1, C11 to C1n: code error time series, C2, C21 to C2n: replacement code, P3: mixed error occurrence pattern information, SI5, SI6 ... Inserter selection information, SEL2, SEL5 to SEL8 ... selector.

Continuation of the front page (56) References JP-A-6-141056 (JP, A) JP-A-63-290423 (JP, A) JP-A-4-287438 (JP, A) JP-A-63-310246 (JP, A) JP-A-63-136738 (JP, A) JP-A-5-235907 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 1/00

Claims (8)

(57) [Claims] 1. Bits constituting code error occurrence pattern information.
If the bit is 0, a predetermined fixed number of bits
Means that there are no errors in all bits of
If the bit constituting the raw pattern information is 1,
Using the following bit sequence, the code for the fixed number of bits
Described in a compressed description format that describes the signal error pattern
Code error generating means for inputting the code error occurrence pattern information and outputting the presence / absence of a code error as a time series in bit units according to the input code error occurrence pattern information; And a signal adding means for adding an output signal of the means by an exclusive OR in a bit unit. 2. A plurality of code error generating means for inputting code error generation pattern information and outputting the presence or absence of a code error as a time series in bit units in accordance with the input code error generation pattern information; Selecting means for selecting one code error generating means from a plurality of code error generating means; signal addition for adding an input signal and an output signal of the selected code error generating means by exclusive OR in bit units Means; and a code error inserter. 3. A permutation code generating means for inputting permutation code generation pattern information and intermittently outputting a bit string of a finite length in accordance with the input permutation code generation pattern information; And a signal replacement means for replacing an input signal with the bit sequence only while the signal is being generated. 4. A plurality of permutation code generating means for inputting permutation code generation pattern information and intermittently outputting a bit string of a finite length; and selecting one permutation code generation means from the plurality of permutation code generation means. Signal replacement means for replacing an input signal with the bit string generated by the selected replacement code generation means only while the selected replacement code generation means is generating the bit string; A code error inserter comprising: 5. A code error generating means for inputting code error generation pattern information and outputting the presence or absence of a code error as a time series in bit units in accordance with the input code error generation pattern information; A first inserter constituted by signal addition means for adding an output signal of the code error generation means by exclusive OR in a bit unit; and inputting replacement code generation pattern information; In accordance with the pattern information, a permutation code generating means intermittently outputting a bit string of a finite length, and a signal permutation means for replacing an input signal with the bit string only while the permutation code generation means generates the bit string. Composed second
Inputting the mixed error occurrence pattern information, and based on the input mixed error occurrence pattern information, the code error occurrence pattern information, the replacement code generation pattern information, the first inserter or the above Information separating means for creating inserter selection information for selecting a second inserter; inserter selecting means for selecting the first inserter or the second inserter according to the inserter selection information; A code error inserter comprising: 6. The inserter according to claim 5, wherein the input signal is input to both the first inserter and the second inserter, or the first inserter and the second inserter are input. Wherein the input signal is input only to the selected inserter. 7. A plurality of inserters including at least one of a first inserter, a second inserter, and a third inserter; and one of the plurality of inserters. And selecting means for outputting an output signal of the selected inserter. The first inserter inputs code error occurrence pattern information, and outputs the input code error occurrence pattern information Accordingly, a code error generating means for outputting the presence or absence of a code error as a time series in a bit unit, and a signal adding means for adding an input signal and an output signal of the code error generating means by exclusive OR in a bit unit The second inserter receives permutation code generation pattern information and outputs a finite-length bit string intermittently according to the permutation code generation pattern information. Generating means and the substitution code A signal replacement unit that replaces an input signal with the bit sequence only while the generating unit is generating the bit sequence; and the third inserter includes the first inserter and the second inserter. And the inserter to select the first or second inserter, based on the input mixed error occurrence pattern information, and the code error occurrence pattern information, the replacement code generation pattern information, and the second inserter. An inserter comprising: information separating means for creating selection information; and inserter selecting means for selecting the first inserter or the second inserter according to the inserter selection information. Code error inserter. 8. The input signal according to claim 7, wherein the input signal is input to only one of the plurality of inserters, or the input signal is input to all of the plurality of inserters. A code error inserter.