JP3204743B2 - Control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device for a peripheral I / O such as a memory by a microprocessor.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a conventional control device. In FIG. 3, reference numeral 1 denotes a microprocessor which can change the access timing to the peripheral I / O by inputting a wait signal from the outside.

First, the operation when the microprocessor 1 accesses the peripheral I / O will be described with reference to FIG. FIG. 4A is a timing chart showing the state of the machine cycle of the microprocessor in the non-wait state, in which T1, T2, T
3 states.

The wait signal is sampled by the microprocessor at the falling edge of the clock in the T2 state, and if it is "1", it enters a non-wait state and the T3 state comes immediately after the T2 state. Conversely, if it is "0", the Tw state is inserted immediately after the T2 state as shown in FIGS. The wait signal is also sampled at the falling edge of the clock in the Tw state. If the wait signal is "0", the next Tw state is inserted. Become.

Generally, a microprocessor outputs an address signal indicating an address to be accessed and an address enable signal indicating a timing at which the address signal is stable and effective. The address signal is output at the rising edge of a clock in the T1 state. Assuming that the address enable signal is active from the falling edge of the clock in the T1 state to the falling edge of the clock in the T3 state, the address enable signal is controlled by controlling the active time width of the wait signal as described above.
The active time width of the address signal and the address enable signal can be controlled.

Since a signal obtained by taking an AND condition between the address enable signal and the address signal is used as a chip select signal of the peripheral I / O, the peripheral I / O is controlled by controlling the active time width of the wait signal.
The active time width of the chip select signal can be controlled.

Conversely, in order for the microprocessor to normally access the peripheral I / O whose access time changes, the active time width of the wait signal may be controlled.

In FIG. 3, reference numeral 2 denotes a peripheral I / O such as a memory, and reference numeral 3 denotes an address decoder for generating a chip select signal of the peripheral I / O based on an AND condition of an address signal and an address enable signal output from a microprocessor. Reference numeral 4 denotes an oscillator for supplying a clock signal to the microprocessor and the wait signal generating means, reference numeral 5 denotes a battery for supplying power to the device, and reference numeral 6 denotes a microprocessor which normally operates on the periphery based on the clock signal and the chip select signal.
Is a wait signal generating means for generating a wait signal for accessing.

Based on the above, the operation of the control device in the conventional example will be described with reference to FIGS. 3 and 4B and 4C. The microprocessor 1 is supplied with a clock signal from the oscillator 4, and the microprocessor 1 accesses the peripheral I / O 2 in synchronization with the clock signal. When the microprocessor 1 attempts to access the peripheral I / O2, the microprocessor 1 outputs an address signal in synchronization with the rise of the clock signal in the T1 state, and outputs an address enable signal in synchronization with the fall of the clock signal. Output.

In the address decoder 3, a signal is generated under the AND condition of the address signal and the address enable signal, and this signal is output to the peripheral I / O 2 and the wait signal generating means 6 as a chip select signal. When the chip select signal becomes active, the peripheral I / O 2 has the exclusive right of the bus of the microprocessor 1 and the microprocessor 1 can be accessed. At this time, since the wait signal generation means 6 knows that the peripheral I / O 2 has been accessed by the chip select signal, the wait signal is activated for the required time in synchronization with the clock signal supplied from the oscillator 4. Therefore, the Tw state is inserted into the machine cycle of the microprocessor 1, and as a result, the active time width of the chip select signal is extended, and the access time of the peripheral I / O2 is guaranteed.

Here, how the active time width of the wait signal is set will be described. The power of the apparatus is supplied by a battery 5, and the voltage of the battery 5 decreases as the usage time increases. On the other hand, it is known that the peripheral I / O2 represented by a memory or the like has a reduced power supply voltage and an increased access time. Therefore, the access time of the peripheral I / O2 increases as the use time of the device increases.

For this reason, for example, at the start of use of the device, that is, when the battery voltage is at the maximum, as shown in FIG. 4B, the active time width of the wait signal is set to one cycle of the clock signal, and one Tw state is inserted. Although the access time could be guaranteed only by using the apparatus, as the battery voltage was reduced by using the apparatus, when the voltage was lower than a certain voltage, FIG.
As shown in (C), two Tw states may need to be inserted. In such a case, the conventional control device is not configured to notify the wait signal generation unit of the decrease in the battery voltage, and therefore, the conventional control device corresponds to the access time of the peripheral I / O2 at the minimum value of the battery voltage range using the device. The active time width of the wait signal for realizing the number of insertions of the Tw state is set.

[0013]

As described above, in the conventional control device, the active time width of the wait signal is set according to the access time of the peripheral I / O at the minimum value of the battery voltage range using the device. Therefore, there is a problem that a Tw state is inserted more than necessary even at the beginning of use of a device having a high battery voltage, which leads to a reduction in processing speed in a microprocessor.

According to the present invention, there is provided a control method for controlling a microprocessor to access a peripheral I / O at an appropriate timing corresponding to a voltage of a battery and to speed up processing in the microprocessor. It is intended to provide a device.

[0015]

In order to achieve the above object, a control device according to the present invention comprises: a reference voltage generating means for generating a constant reference voltage from an output of a battery; The voltage dividing means for dividing the voltage, the output voltage from the reference voltage generating means and the output voltage of the voltage dividing means are compared , and the result is calculated.
A voltage comparison means for outputting a weight switching signal based on the result, a wait signal generating means for varying the active time duration of the wait signal to be input to the <br/> microprocessor according to the weight switching signal from the voltage comparator means It is provided.

[0016]

According to the present invention, the output voltage of the voltage dividing means for dividing the output voltage of the reference voltage generating means for generating a constant reference voltage regardless of the battery voltage and the output voltage of the battery at a constant ratio, according to the present invention, is provided. Are compared in the voltage comparing means, and the result is transmitted as a signal to the weight signal generating means,
The wait signal generation means can detect whether the battery voltage has dropped below a certain voltage, and therefore can change the active time width of the wait signal input to the microprocessor according to the change in the battery voltage. .

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the control device according to the present invention. In FIG. 1, 1 is a microprocessor, 2 is a peripheral I / O such as a memory, 3 is an address decoder, 4 is an oscillator, and 5 is a battery. And the description is omitted.

Reference numeral 10 denotes a weight signal generating means for generating a weight signal according to a weight switching signal from a voltage comparing means 9 described later based on a clock signal and a chip select signal. Reference numeral 7 denotes a constant reference voltage from the output of the battery. Reference voltage generating means such as a three-terminal regulator for generating the voltage, voltage dividing means 8 for dividing the output voltage of the battery at a fixed ratio, and 9 comparing the output voltage from the reference voltage generating means with the output voltage from the voltage dividing means. A weight switching signal which becomes "0" when the output voltage from the reference voltage generating means 7 is higher and "1" when the output voltage from the voltage dividing means 8 is higher is a weight signal. Output to the generating means 10. In response to this, the wait signal generating means 10 outputs
When the wait signal is "1", a wait signal that is active for one cycle of the clock signal is output. When the wait switching signal is "0", a wait signal that is active for two cycles of the clock signal is output.

Next, the operation of the control apparatus according to the present embodiment will be described with reference to FIGS. A clock signal is supplied from the oscillator 4 to the microprocessor, and the microprocessor 1 synchronizes the peripheral I / O with the clock signal.
Access to O2. When the microprocessor 1 attempts to access the peripheral I / O2, the microprocessor 1 outputs an address signal in synchronization with the rise of the clock signal in the T1 state, and the address enable signal is synchronized with the fall of the clock signal. Is output.

In the address decoder 3, a signal is generated under the AND condition of the address signal and the address enable signal, and the signal is output to the peripheral I / O 2 and the wait signal generating means 10 as a chip select signal. When the chip select signal becomes active, the peripheral I / O 2 has the exclusive right of the bus of the microprocessor 1 and the access to the microprocessor 1 becomes possible. At this time, the wait signal generation means 10 knows that the peripheral I / O 2 has been accessed by the chip select signal, so that the wait signal active for the time corresponding to the wait switching signal is synchronized with the clock signal supplied from the oscillator 4. Generate. Therefore, the Tw state is inserted into the machine cycle of the microprocessor 1, and as a result, the active time width of the chip select signal is extended, and the access time of the peripheral I / O2 is guaranteed.

FIG. 2A shows the battery 5 at the beginning of use of the apparatus.
Peripheral I / O of the microprocessor 1 when the voltage of the
2 is a timing chart showing a state of access to the reference voltage generator 2. At this point, the output voltage from the voltage divider 8 is still higher than the output voltage from the reference voltage generator 7, and the weight switching signal is "1". Therefore, wait signal generating means 10 is active for one cycle of the clock signal, one Tw state is inserted, and the active time width of the chip select signal is extended accordingly.

FIG. 2B is a timing chart showing the state of access to the I / O 2 around the microprocessor 1 when the use time of the apparatus has considerably elapsed and the voltage of the battery 5 has dropped. The output voltage from the reference voltage generating means 7 is higher than the output voltage from the voltage dividing means 8, and the weight switching signal is "0". Therefore, wait signal generating means 10 is active for a period of two cycles of the clock signal, two states of Tw are inserted, and the active time width of the chip select signal is extended accordingly.

Here, when the access time of the peripheral I / O 2 is longer than the active time width of the chip select signal when one Tw state is inserted, the voltage comparison means 9 determines that the access time is just “0”. If the reference voltage of the reference voltage generating means 7 and the voltage dividing ratio of the voltage dividing means 8 are set so as to output a wait switching signal, the microprocessor 1 can control the peripheral I / O and the peripheral I / O at an appropriate timing corresponding to the battery voltage. And the speed of the processing in the microprocessor 1 can be increased.

[0024]

As described above, according to the present invention, reference voltage generating means for generating a constant reference voltage from the output voltage of the battery, voltage dividing means for dividing the output voltage of the battery at a constant ratio, The output voltage from the voltage generating means is compared with the output voltage from the voltage dividing means, and based on the result, the weight switching signal is output.
A voltage comparing means for outputting the item, web from the voltage comparator means
Weight signal generating means for changing the active time width of the wait signal input to the microprocessor in response to the light source switching signal , so that the weight generating means detects a change in the battery voltage, and responds to the change in the battery voltage. Can change the active time width of the wait signal input to the peripheral I / O at an appropriate timing corresponding to the battery voltage.
An excellent control device that can access the O and can achieve high-speed processing in the microprocessor can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a control device according to the present invention.

FIG. 2 is a timing chart of an embodiment of a control device according to the present invention.

FIG. 3 is a block diagram of a control device in a conventional example.

FIG. 4 is a timing chart of a control device in a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Microprocessor 2 Peripheral I / O 3 Address decoder 4 Oscillator 5 Battery 7 Reference voltage generating means 8 Voltage dividing means 9 Voltage comparing means 10 Wait signal generating means

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 9/30-9/355 G06F 13/10 G06F 1/04-1/14

Claims (3)

(57) [Claims] 1. A microprocessor capable of changing the access timing to peripheral I / O by inputting a wait signal from the outside, a battery for supplying power to the apparatus, and a constant output from the battery. compares the reference voltage generating means for generating a reference voltage, a voltage divider for dividing the output voltage of the battery at a constant rate, the output voltage of the output voltage and the voltage divider from the reference voltage generating means, the Based on the results
A voltage switching means for outputting a wait switching signal; and a wait signal generating means for changing an active time width of a wait signal input to the microprocessor in response to a weight switching signal from the voltage comparing means. Control device. 2. The method according to claim 1, wherein the wait signal generating means includes a clock signal.
Based on the signal and the chip select signal.
Generating a wait signal according to the weight switching signal
The control device according to claim 1, wherein: 3. A method of externally inputting a wait signal.
More variable I / O access timing
Microprocessor, peripheral I / O such as memory,
A battery that supplies power to the
A reference voltage generating means for generating a reference voltage;
Voltage dividing means for dividing the input voltage at a fixed ratio;
The output voltage from the voltage generating means and the output voltage from the voltage dividing means.
And outputs a wait switching signal based on the result.
Voltage comparing means, and an output from the microprocessor.
Based on the address signal and the address enable signal
Address data for generating chip select signals for peripheral I / O
A coder, the microprocessor and a wait signal
An oscillator for supplying a clock signal to the generating means;
Clock signal and chip select signal supplied from the
Based on the weight switching signal from the voltage comparing means,
Weight signal generating means for generating the same weight signal
Wherein the weight signal generating means includes the chip select.
That the peripheral I / O has been accessed by the
A wait switching signal in synchronization with the clock signal.
An active wait signal is generated for the time corresponding to
Chip based on signals from the microprocessor.
Extend the active time width of the select signal.
Characteristic control device.