JP3205146B2 - Engine control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an engine control device, and more particularly to troubleshooting in a market.

[0002]

2. Description of the Related Art Conventionally, an engine control device has been used to control an engine. The engine control device has a CPU which operates according to a predetermined program and a ROM which is a nonvolatile memory for storing the program. Is provided. The ROM stores a program and data for determining a fuel injection amount supplied to the engine, an ignition timing, and the like. In recent years, CPUs with a built-in ROM and capable of single-chip mode have been put on the market. However, programs and data can be written only once into the ROM in the CPU. Have been invented.

As described above, Japanese Patent Application No. Hei.
There is an official gazette.

[0004]

In the above prior art, the CP
Although U can be written to the built-in ROM after U is mounted on the board, erasing and rewriting of data are not considered. That is, there is a problem that even if it is desired to rewrite the data in the ROM after supplying the engine control device to the market, it cannot be performed.

An object of the present invention is to provide an engine control device which can easily rewrite ROM data even during engine operation by troubleshooting in the market.

[0006]

The object of the present invention is to erase data.
Removed by and the non-volatile memory can be written, data writing
And it can included and readable volatile memory, the non
Operates according to the program written in the volatile memory.
Engine control device with a microcomputer
Stomach, the change of the program of the non-volatile memory (erase及
And write) are stored in the nonvolatile memory in advance.
An erase and write program that is
The information input from the control device outside the external device, the volatilized
Transfer and store in volatile memory
Based on the engine control device
More achieved .

[0007]

[0008]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the present invention. 1 is an engine control device. Reference numeral 2 denotes an engine controlled by the engine control device 1. Although not shown, the engine 2 is provided with various sensors for indicating an operating state, and signals from the sensors are transmitted to the engine control device 1.
Is input to The engine control device 1 includes an input processing circuit 4 that performs waveform processing on a signal from the sensor, and a CPU 3 that receives the sensor signal and calculates an optimal operation state of the engine 2.
And an output circuit 5 that receives the calculated result as a control signal and drives an actuator such as a fuel injection device or an ignition device attached to the engine 2 (not shown). The CPU 3 includes an MPU 7 operating according to a control program, a ROM 8 storing a program for operating the MPU 7, a RAM 9 storing an operation result of the MPU 7, a signal from the input processing circuit 4, an output circuit, 5 which outputs a control signal to I
A communication circuit 10 for data communication with / O6 and an external device is built in. The engine control device 1 can be electrically connected to a memory rewriter 11 which is an external device.
It is connected to the communication circuit 10 in the PU3. 12 is CPU3
In the case of a watchdog circuit that monitors whether the CPU 3 is operating normally, if the above occurs in the CPU 3, the CPU 3 can be reset. Here, the ROM 8 is a memory in which contents can be erased and written under special conditions.

FIG. 2 shows a memory map of the CPU 3. FIG. 2A is a memory map of the entire CPU 3.
a is the area of the ROM 8, 3b is the external memory space, 3c is the R
The area of AM9, 3d is an internal register area of MPU7. (b) shows a block configuration in the ROM 8. RO
M8 is divided into several blocks.
Is divided into 17 blocks A to Q. Among them, the contents of AP are erasable for each block, and Q is a non-erasable area. Engine control device 1
The configuration in the ROM 8 used in the above is roughly divided into a program area in which a control program is stored, an area in which control data is stored, and a non-erasable area. In this embodiment, blocks A to K are program areas,
Blocks L to P are data areas, and block Q is a non-erasable area. In this embodiment, the block Q has R
A program for erasing and rewriting OM contents and a program for outputting a pulse signal for notifying a normal operation of the microcomputer to an external watchdog timer are stored.

FIG. 3 shows the structure of a dedicated register for erasing data in the ROM 8. The erase register is arranged in the internal register area 3d and is composed of 2 bytes. Each bit of the erase registers 1 and 2 corresponds to each of the blocks A to P in the ROM 8, and when this bit is set to 1, for example, the contents of the corresponding block are erased. Therefore, for example, when it is desired to rewrite only the data of the block M which is the data area, first, the erase register 2
The operation of writing data to the block M may be performed by erasing the data of the block M by setting the bit 4 of 1 to 1.
In the present embodiment, the erasure register of the block Q is not set so that the block Q cannot be erased. FIG. 4 is a state transition diagram showing the internal state of the CPU 8 when rewriting the contents of the memory in the CPU 8 through communication with the memory rewriter 11 as an external device. Before the communication with the memory rewriter 11 is started, it is in a state of waiting for communication from the memory rewriter 11 in S1. Here, when a command “INIT” is input from the memory rewriter 11, a command “<INIT>” is transmitted from the engine control device 1 to the memory rewriter 11 to notify that the “INIT” command has been received. At the same time, it enters a state of waiting for a setting command in S2. S
If a command other than "INIT" is input in step 1, an <error> command is transmitted, and the process returns to the original state S1. Hereinafter, similarly, even if it is placed in each state, if a command corresponding to that state is input, a command for that is transmitted,
Transition to the next state. In other cases, an <error> command is transmitted, and the process returns to S1, which is the initial state.
After inputting the "INIT" command from the initial state S1, the state transits to the setting command waiting state in S2 and waits for the next command.
"PRO" to enter the program change mode in S2
When a "G" command is received, the process goes to S3, when a "DATA" command to enter the data change mode is received, the process goes to S7, otherwise, to S1. When a transition is made to S3, a program change mode is entered, and when a transition is made to S7, a data change mode is entered. "GO" in S3
If a command has been received, the process proceeds to step S4, and if data for change has been input, the process proceeds to step S5 to perform data change processing.
When this process is completed, the process returns to S4 after transmitting a <data> command in order to wait for the next data to be input.
When a predetermined number of data has been input, the process proceeds from S5 to S6 in a wait state for an end command. In step S6, when the “EXIT” command is received, an <EXIT> command is transmitted,
Returning to S1, the program change mode ends. on the other hand,
When the "DATA" command is received in S2, the mode is changed to the data change mode. In S7, "ADDR" data, which is the designation of the block in the ROM 8 to be changed, is received, and the flow proceeds to S8. After receiving the "GO" command which is the process start command in S8, the data change process is performed in S9 and S10.
In S9, when the data to be changed is received, the process proceeds to S10, and the change process is executed. After the processing is completed, <data> is transmitted, the process returns to the state of S9, and waits for the next data. When a predetermined number of data has been input, the flow shifts to the state of S6 and "E
XIT "command waiting state. Thereafter, when the "EXIT" command is input in the same manner as in the program change mode, an <EXIT> command is transmitted, the process returns to the state of S1, and the data change mode ends.

FIG. 5 is a flowchart showing the operation of the program in the engine control device 1 when the communication shown in FIG. 4 is performed. In this embodiment, the communication with the memory rewriter 11 uses serial communication. FIG. 5 shows the processing of an SCI interrupt that occurs when data is transmitted from the memory rewriter 11. When an SCI interrupt occurs, first in S20
INIT flag, PROG flag in S21, DATA flag in S22
Check if is 1. If the INIT flag is 0 in S20, it indicates that the communication is in the waiting state for communication, which is S1 in FIG. 4, and the data input this time is "INI" in S28.
Check if it is a "T" command. If the command is not the "INIT" command, the process proceeds to S25, outputs an <error> command, sets each flag of INIT, PROG, and DATA to 0, and returns to the initial state of communication.
The interrupt processing ends. If it is confirmed in step S28 that the command is an "INIT" command, in step S29, an <INIT> command is output to the memory rewriter 11, and the INIT flag is set to 1
To end the process. If the INIT flag is 1 in S20, it indicates that the state is after S2 in FIG. 4, and it is checked below which state it is. In S21
The program change mode is confirmed by the PROG flag, and if the flag is 1, the process proceeds to S31 to perform a program change process. If not, it is checked in S22 whether the mode is the data change mode by the DATA flag. If the mode is the data change mode, the process proceeds to S30, where data change processing is performed.

If the flag is 0 in S30, it means that the data entered this time is "PROG" because it is in the state of S2 in FIG.
Alternatively, S23 and S24 determine whether the command is a "DATA" command.
Confirm with. If it is determined in step S23 that the "PROG" command has been input, the flow advances to step S27 to output a <PROG> command, set PROG flag to 1, and enter the program change mode. On the other hand, if it is determined in step S24 that the "DATA" command has been input, the process proceeds to step S26, where the output of the <DATA> command and the DATA flag are set to 1 to enter the data change mode. If neither command is confirmed in S23 and S24, it is determined that a data communication error has occurred, and the flow advances to S25 to output an <error> command and INIT, PROG, D
Each flag of ATA is set to 0, and the process returns to the initial state of S1 in FIG.

FIG. 6 shows a program for erasing and rewriting ROM contents and a program for outputting a signal for notifying a normal operation of the microcomputer to an external watchdog timer on a volatile memory. It is a flowchart explaining the process of S31 at the time of entering a program change mode. The processing of FIG. 6 shows the processing in which the program is executed on the RAM 9.
The program for rewriting the program is originally stored in the ROM 8, and is executed after the program is once transferred to the RAM 9. In S40 of FIG. 6, it is checked whether the command is a "GO" command. If the command is not a "GO" command, the transmitted command is abnormal, so the process proceeds to S43 and outputs an <error> command. flag to 0
And return to the initial state. If it is a "command", the process proceeds to S41, in which a process of transferring the rewritten program from the ROM 8 to the RAM 9 is performed. After the transfer process is completed,
Jump to the program transferred to the RAM 9 at 42
Execute the program on AM9.

With the above method, the program or data on the ROM 8 can be changed by communication from an external device.

[0016]

According to the present invention, the content of the ROM data can be changed without converting the engine control unit when a trouble occurs, and the trouble shooting can be easily performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of the present invention.

FIG. 2 is a diagram showing a memory map showing a configuration of a ROM built in a CPU.

FIG. 3 is a configuration diagram illustrating a configuration of a register that is erased for each block in a ROM.

FIG. 4 is a state transition diagram showing states in a CPU when communication with a memory rewriter is performed.

FIG. 5 is a flowchart showing an operation when shifting to a program change mode or a data change mode.

FIG. 6 is a flowchart illustrating a process of S31 when a program change mode is entered in the process of FIG. 5;

[Description of Signs] 1 ... Engine control device, 2 ... Engine, 3 ... CPU, 3
a: ROM area, 3b: external memory space, 3c: RAM
Area, 3d: internal register area, 4: input processing circuit, 5
... output circuit, 6 ... I / O, 7 ... MPU, 8 ... flash ROM, 9 ... RAM, 10 ... communication circuit, 11 ... memory rewriter, 12 ... watchdog circuit.

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hideaki Ishikawa 2520, Oaza Takaba, Katsuta-shi, Ibaraki Hitachi, Ltd. Automotive Equipment Division (56) References JP-A-2-99746 (JP, A) JP-A-5-189981 (JP, A) JP-A-63-78253 (JP, A) JP-A-4-326148 (JP, A) JP-A-5-233267 (JP, A) JP-A-63-286992 (JP , A) (58) Fields surveyed (Int. Cl. ⁷ , DB name) F02D 45/00

Claims (1)

(57) [Claims] And 1. A non-volatile memory capable of erasing and writing data, the write and read, volatile memory of the data, the engine control unit having a microcomputer operating in accordance with the non-volatile memory written program In the execution of a change (erase and write) of a program in the nonvolatile memory, the erase and write program stored in advance in the nonvolatile memory is executed by inputting information from an external device outside the engine control device. An engine control device, wherein the engine control device is transferred and stored in a volatile memory, and is performed based on the stored program.