JP3206178B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a semiconductor integrated circuit used as a latch circuit in a bipolar integrated circuit.

[0002]

2. Description of the Related Art In recent years, with respect to bipolar logic integrated circuits, there has been a demand for a semiconductor integrated circuit having an improved driving capability with a reduction in power consumption due to higher integration and an increase in chip size. In addition, due to the reduction in parasitic capacitance due to the miniaturization of circuit elements, it is required that latch circuits and the like have a circuit resistance to noise. As a latch circuit corresponding to such a request, a circuit shown in FIG. 4 has been conventionally proposed. As shown in FIG. 4, in this conventional example, the data input signal 1
02 and 103 are input, and the NPN transistor 45 whose emitters are connected in common and functions for data transfer
And 48, NPN transistors 46 and 47 having emitters connected in common and acting as data holding,
Collectors are respectively connected to the common emitters of the NPN transistors 45 and 48 and the common emitters of the NPN transistors 46 and 47, and NPN transistors 49 and 50 whose bases receive clock signals 103 and 104, respectively, and PNP transistors 49 and A constant current source 51 (current I ₅ ) connected between the common emitter section 50 and the power supply, between the common collector section of the NPN transistors 45 and 46 and the ground point, and NP
N-transistors 47 and 48 are connected between a common collector section and a ground point, respectively, and serve as load resistances 56 and 57. The bases are commonly connected, and the collectors are connected to the ground point. , NPN transistors 52 and 53 forming emitter follower circuits, respectively, and NPN transistors 52 and 53 forming emitter follower circuits, respectively. It comprises a constant current source 42 (current I ₃ ), 43 (current I ₄ ), 54 (current I ₅ ) and 55 (current I ₆ ) connected between the emitter of the transistor and the power supply.

In FIG. 4, at timings when clock signals 103 and 104 are input at "H" level and "L" level, respectively, data input signals 102 and 106 are taken into the latch circuit, and N
Via the on / off states of the PN transistors 45 and 48, the potentials of the resistors 56 and 57 are determined. At this time, NPN transistors 46 and 47 for holding data are used.
Are both off. The potentials determined at the resistors 56 and 57 correspond to NPN transistors 40 and 53 forming an emitter follower circuit, respectively.
Is transferred to the outside through the operation of NPN transistors 41 and 52 which form an emitter follower circuit.
It is supplied to the bases of transistors 47 and 46.

Conversely, clock signals 103 and 10
4 are input at the “L” level and “H” level, respectively.
And 48 are both turned off, so that the latch circuit is in a data holding state without being affected by an external data input. In this case, in the NPN transistors 46 and 47 for holding data,
One of the NPN transistors is turned on by the potential relation of the base determined at the time of data capture (during data transfer), and the data holding state is maintained through the potential relation holding action. .

Generally, when switching from a data transfer to a data holding state, NPN transistors 46 and 4
7 turns on, a charging current to the base flows, and Grigg noise occurs in the resistors 56 and 57. In this circuit, however, a sufficient amount of current flows through the emitter follower circuit. Since current is supplied, noise immunity is improved.
In this case, in order to improve noise immunity, in particular, α-rays and the like are supplied to NPN transistors 46 and 4 for data retention.
7, the current flowing through the emitter follower circuit formed by the NPN transistors 41 and 52 is reduced as much as possible to prevent the soft errors and the like from occurring at the load resistors 56 and 57. The Grigg noise,
It is desirable that the noise should not be fed back to the transistors 46 and 47. On the other hand, in the emitter follower circuit for external driving formed by the NPN transistors 40 and 53, it is better to increase the current as much as possible in order to improve the driving capability, particularly the falling characteristic.

[0006]

In the above-described conventional semiconductor integrated circuit, in order to improve noise immunity,
When the current of the emitter follower circuit formed by NPN transistors 41 and 52 is reduced, the potential determination with respect to the base point of NPN transistors 46 and 47 is delayed due to the rounding of the waveform in the emitter follower circuit when data is taken in, and the operation cycle is shortened. This makes it difficult to hold data.

Further, since the emitter follower circuit for feeding back to the NPN transistor for holding the latch circuit and the emitter follower circuit for external driving are separately provided, the number of circuit elements is inevitably increased. However, there is a disadvantage that the degree of integration is reduced and power consumption is increased.

[0008]

According to a first aspect of the present invention, in a semiconductor integrated circuit forming a latch circuit, a collector is connected to a ground point, and an emitter is a first and a second data output, respectively. First and second NPN transistors respectively connected to terminals and individually acting as emitter follower circuits; and load resistors connected between the bases of the first and second NPN transistors and ground, respectively. A first and a second resistor, respectively, and a collector connected to the bases of the first and second NPN transistors, respectively, and a base connected to the first and second data input terminals, respectively, and an emitter. Are connected in common, and the third and fourth NPN transistors acting for data transfer and the collector are connected to each other. Each said third and fourth NPN
Fifth and sixth NPN transistors which are connected to the collector of the transistor, the bases are connected to the second and first data output terminals, respectively, and the emitters are connected in common, and serve to hold data; Are respectively connected to the common emitter section of the third and fourth NPN transistors and the fifth and sixth NPN transistors.
The base is connected to the common emitter of the transistor,
Seventh and eighth NPNs respectively connected to the first and second clock input terminals and having emitters connected in common
A transistor, a constant current source connected between a common emitter section of the seventh and eighth NPN transistors and a power supply, and a collector, the first and second NP transistors respectively.
Ninth and tenth NPN transistors connected to the emitters of the N transistors, the bases are connected in common, and a predetermined bias voltage is applied, and the emitters are respectively connected to a power supply and function for current control;
A bias circuit that is formed between a power supply and a ground point, is arranged in series with a third resistor, a forward diode, and a fourth resistor in this order from the ground point side and connected in series, and outputs the bias voltage; A capacitor connected between the first clock input terminal and the base of the ninth NPN transistor.

According to a second aspect of the present invention, in the semiconductor integrated circuit forming the latch circuit, the collector is connected to the ground point, and the emitter is connected to the first and second data output terminals. A first and a second NPN transistor individually acting as an emitter follower circuit, and a second and a third NPN transistor respectively connected between the bases of the first and the second NPN transistors and a ground, and acting as a load resistance. A first and a second resistor and a collector are respectively connected to the first and second NPs.
Third and fourth NPN transistors connected to the base of an N-transistor, the bases being connected to the first and second data input terminals, respectively, and having the emitters connected in common, acting for data transfer; Are connected to the collectors of the third and fourth NPN transistors, respectively, and the bases are connected to the second and first data output terminals, respectively, and the emitters are commonly connected to act as data holding. Fifth and sixth NPN transistors and a collector are respectively connected to a common emitter part of the third and fourth NPN transistors and a common emitter part of the fifth and sixth NPN transistors, and a base is respectively connected. Connected to the first and second clock input terminals, the emitters are commonly connected 7th and 8th NPN transistors, a constant current source connected between a common emitter section of the 7th and 8th NPN transistors and a power supply, and an anode section of the first and second NPN transistors, respectively. The first and second diodes are connected to a power supply via third and fourth resistors, and the cathode portion is connected in common, and the collector is connected to the first and second diodes. A ninth NPN transistor, which is connected to the common cathode portion, has a predetermined bias voltage applied to the base, and has an emitter connected to the ground point, and a third point between the power supply and the ground point from the ground point side, between the power supply and the ground point A bias circuit that is formed by arranging a resistor, a forward diode, and a fourth resistor in this order and connected in series, and that outputs the bias voltage; A capacitor connected between the base of the ninth NPN transistor, the is characterized in that at least provided.

[0010]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention. As shown in FIG. 1, in this embodiment, the data input signals 102 and 103 are input to the base, respectively, and the emitters are connected in common and operate for data transfer.
Collectors are provided at PN transistors 8 and 11, NPN transistors 9 and 10 whose emitters are connected in common and function for data retention, and a common emitter of NPN transistors 8 and 11 and a common emitter of NPN transistors 9 and 10, respectively. NPN transistors 12 and 13 which are connected to each other and receive clock signals 103 and 104 at their bases respectively; a constant current source 14 (current I ₁ ) connected between a common emitter of PNP transistors 12 and 13 and a power supply; , NPN transistors 8 and 9 are connected between a common collector and ground, and NPN transistors 10 and 11 are connected between a common collector and ground, respectively. Is connected to the ground point and the base is N It is connected to a common collector portion of the N transistors 8 and 9, NPN for emitter follower emitter connected to the base of NPN transistor 10
Similarly to transistor 1, the collector is connected to the ground point, the base is connected to the common collector of NPN transistors 10 and 11, and the emitter acts as a transistor for an emitter follower whose emitter is connected to the base of NPN transistor 9. NPN transistor 17, collectors are respectively connected to emitters of NPN transistors 1 and 17, bases are connected in common, emitters are respectively connected to power supplies, NPN transistors 2 and 18 acting as current control transistors, and resistors are connected. A bias circuit 4 formed of NPN transistors 5 and 6 and a diode 7, the bias output voltage of which is connected to the bases of NPN transistors 2 and 18;
And 18 and a capacitor 21 connected between the common base portion of the NPN transistor and the base of the NPN transistor.

In FIG. 1, the current value in the current controlling NPN transistors 2 and 18 is several μA to several tens μA by the bias voltage supplied from the bias circuit 4.
It is set in a state where a very small current flows. When the clock signal 104 changes from “L” level to “H” level and the clock signal 103 changes from “H” level to “L” level, the latch circuit enters a data fetch (data transfer) state. , Data input signal 102
NPN transistors 8 and 11 are turned on and off, respectively, through the inputs of and 106, whereby data output to resistors 15 and 16 are passed through NPN transistors 1 and 17 forming an emitter follower circuit. Are output to the outside as output signals 101 and 105, respectively, and are in an off state.
It is fed back to the bases of transistors 10 and 9. At this time, as shown in FIGS. 2A and 2B, in the transition state of the rising edge of the clock signal 103, the rising edge signal is supplied via the capacitor 21 to the bases of the NPN transistors 2 and 18 of the current controlling transistor. , Whereby the base potentials of NPN transistors 2 and 18 rise, current values 107 and 108 in NPN transistors 2 and 18 both increase transiently, and a large current also flows through NPN transistors 1 and 17. As a result, a rapid discharge is performed in the load capacitance on the output side, the fall of the signal output is accelerated, and the NPN transistor 9 for holding data is obtained.
The output signal is fed back at a high speed to the bases 10 and 10. Therefore, even in the case of a high-speed cycle, data can be held in the latch circuit.

When the clock signal 103 falls, the base potential of the NPN transistors 2 and 18 for current control recovers to a level set by the bias voltage supplied from the bias circuit 4, forming an emitter follower circuit. The current value of the NPN transistors 1 and 17 becomes a very small current of about several μA to several tens of μA. In a steady state, the collector potential of the α-ray etc. Even if the light is incident in the downward direction, the noise waveform is smoothed because the emitter follow current is a very small current, and the NP
The noise resistance is improved without affecting the bases of the N transistors 9 and 10 due to noise.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention. As shown in FIG. 3, in this embodiment, the data input signals 102 and 103 are input to the base, respectively, and the emitters are connected in common, and the emitters are connected in common, and the emitters are connected in common. And NPN transistors 28 and 29 acting as data holding circuits, collectors are respectively connected to the common emitters of NPN transistors 27 and 30 and NPN transistors 28 and 29, and clock signals 103 and 10 are respectively connected to the bases.
4, NPN transistors 31 and 32,
A constant current source 33 (current I ₂ ) connected between the common emitter section of the PNP transistors 31 and 32 and the power supply;
Between the common collector of NPN transistors 27 and 28 and ground, and between NPN transistors 29 and 3
0, which are connected between the common collector section of P.O. 0 and the ground point, respectively, and serve as load resistances. The collector is connected to the ground point, and the base is the NPN transistor 2.
7 and 28, the emitter is connected to the ground point, and the bases are connected to the NPN transistors 29 and 30. NPN transistor which is connected to a common collector portion of the NPN transistor, and whose emitter is connected to the base of the NPN transistor 28 to act as a transistor for an emitter follower.
Transistor 34, diodes 20 and 38 whose cathodes are connected in common and whose anodes are connected to the emitters of NPN transistors 19 and 34, respectively, and whose collector is connected to the common cathode of diodes 20 and 38, have a predetermined bias voltage applied to the base. Is supplied, and the NPN transistor 35 for current control in which the emitter is connected to the power supply.
And a bias circuit 23 formed of resistors 24 and 25 and a diode 26 for outputting the bias voltage and supplying the bias voltage to the base of an NPN transistor 35, and a bias circuit 23 connected between the base of the NPN transistor 35 and the base of the NPN transistor 31. And the resistors 22 and 39 connected between the anodes of the diodes 20 and 38 and the power supply, respectively.

As is apparent from comparison with FIG.
The difference from the first embodiment is that the current controlling transistor is one.
The NPN transistors 35 are shared by the two emitter follower circuits, and fall from the “H” level to the “L” level at the time of transition of the clock signal at the time of data fetch (data transfer) due to the output level of the latch circuit. This circuit allows more current to flow selectively to the emitter follower circuit on the side,
As a result, higher speed operation is realized. In FIG. 3, resistors 22 and 39 are bleeder resistors for flowing a current to the emitter follower circuit on the low level side of the latch output. In a steady state, the emitter follower circuit has a very small voltage of about several μA to several tens μA. This is a resistor for setting so that a current flows. The overall operation of this embodiment is the same as that of the first embodiment.

[0016]

As described above, according to the present invention, the function of the emitter follower circuit for driving the external output is used in addition to the function for outputting the feedback signal in addition to the function for the original external output. The feedback signal from the emitter follower circuit is fed back to the transistor pair for holding data, and the current of the emitter follower circuit is synchronized with the clock signal input, thereby simplifying the circuit configuration and integrating the semiconductor integrated circuit. And the current can be increased only at the time of level transition at the time of data acquisition. This increase in current increases the operation in high-speed cycles and improves the noise resistance without reducing the integration degree. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a timing chart showing operation signals in the first embodiment.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a conventional example.

[Explanation of symbols]

1, 2, 8 to 13, 17 to 19, 27 to 32, 34, 3
5, 40, 41, 45 to 50, 52, 53 NPN transistor 3, 21 capacitance 4, 23 bias circuit 5, 6, 15, 16, 22, 24, 25, 36, 37,
39, 56, 57 Resistance 7, 20, 26, 38 Diode 14, 33, 42, 43, 51, 54, 55 Constant current source

Claims (2)

(57) [Claims] In a semiconductor integrated circuit forming a latch circuit, a collector is connected to a ground point, and an emitter is connected to first and second data output terminals, respectively.
First and second NPN transistors each individually acting for an emitter follower circuit, and first and second NPN transistors respectively connected between the bases of the first and second NPN transistors and a ground and acting as load resistors. A second resistor and a collector connected to the bases of the first and second NPN transistors, respectively, a base connected to the first and second data input terminals, respectively, and an emitter commonly connected; Third and fourth NPN transistors acting for data transfer; and collectors connected to the collectors of the third and fourth NPN transistors, respectively, and bases connected to the second and first data output terminals, respectively. And the emitters are connected in common, and the fifth and 6 and NPN transistor having a collector, a common emitter of each of the third and fourth NPN transistors, said fifth and sixth N
Seventh and eighth N transistors connected to a common emitter portion of the PN transistor, the bases are connected to the first and second clock input terminals, respectively, and the emitters are commonly connected.
A PN transistor, a constant current source connected between a common emitter of the seventh and eighth NPN transistors and a power supply, and a collector connected to the emitters of the first and second NPN transistors, respectively. A ninth and a tenth NPN transistor which are connected to a base and are commonly connected to apply a predetermined bias voltage, and whose emitters are respectively connected to a power supply and serve for current control, are connected between the power supply and a ground point. A bias circuit which is formed by arranging a third resistor, a forward diode, and a fourth resistor in this order from the ground point and connecting in series, and outputting the bias voltage; A capacitor connected between the base of the ninth NPN transistor and the semiconductor integrated circuit. 2. A semiconductor integrated circuit forming a latch circuit, wherein a collector is connected to a ground point, and an emitter is connected to first and second data output terminals, respectively.
First and second NPN transistors each individually acting for an emitter follower circuit, and first and second NPN transistors respectively connected between the bases of the first and second NPN transistors and a ground and acting as load resistors. A second resistor and a collector connected to the bases of the first and second NPN transistors, respectively, a base connected to the first and second data input terminals, respectively, and an emitter commonly connected; Third and fourth NPN transistors acting for data transfer; and collectors connected to the collectors of the third and fourth NPN transistors, respectively, and bases connected to the second and first data output terminals, respectively. And the emitters are connected in common, and the fifth and 6 and NPN transistor having a collector, a common emitter of each of the third and fourth NPN transistors, said fifth and sixth N
Seventh and eighth N transistors connected to a common emitter portion of the PN transistor, the bases are connected to the first and second clock input terminals, respectively, and the emitters are commonly connected.
A PN transistor; a constant current source connected between a common emitter of the seventh and eighth NPN transistors and a power supply; and an anode connected to the emitters of the first and second NPN transistors, respectively. And a first and second diode connected to a power supply via third and fourth resistors and having a cathode section commonly connected, and a collector connected to a common cathode section of the first and second diodes. A ninth NPN transistor having a base to which a predetermined bias voltage is applied and an emitter connected to a ground point; and a third resistor, a forward resistor, between the power supply and the ground point from the ground point side. A bias circuit that is formed by arranging a diode and a fourth resistor in this order and connecting them in series, and that outputs the bias voltage; the first clock input terminal and the ninth NPN The semiconductor integrated circuit comprising: the capacitor is connected between the base of the transistor, at least.