JP3206525B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a technique devised for a pellet structure of a high-power semiconductor.

[0002]

2. Description of the Related Art High-output field-effect transistors (hereinafter referred to as F
In order to improve the performance of ET, that is, to increase the output, the reduction of the thermal resistance is an important factor, and it is effective to reduce the pellet pressure and improve the heat dissipation.

However, when the pellet thickness is reduced,
The warpage of the pellets increases during heat treatment such as the mounting process during assembly, increasing the number of pellet cracks, making automatic assembly difficult,
This may cause residual stress, etc., and impair the FET characteristics, reliability and assembly workability. That is, there is a trade-off relationship between pellet thickness and thickness reduction for reducing thermal resistance.

As a means for solving the above-mentioned problems, a pellet structure in which the thickness of GaAs, that is, the thickness of the semiconductor substrate is reduced only in the active region serving as a heat source is being studied.

FIGS. 7, 8 and 9 show a conventional example which solves the above-mentioned problem. 7 is a top plan view, FIG. 8 is a cross-sectional view taken along the line BB ' in FIG. 7, and FIG. 9 is a line A-
FIG. 4 shows a cross-sectional view taken along line A ′ .

A back surface treatment is performed by providing a single step on the back surface of the semiconductor substrate 9, ie, just below the active region 11 formed on the GaAs substrate 9, so that the substrate thickness is reduced. Then, a metal such as Au or Ag is plated to fill the metal layer 10 .

As a result, the thermal resistance is reduced in the active region 11 serving as a heat source, and since the thickness of the GaAs substrate 9 in the peripheral portion is large, it is possible to obtain a highly reliable pellet which is resistant to stress.

[0008]

A first problem is that, in a pellet having a multi-cell structure accompanying an increase in output, a matching loss occurs due to an output difference of each unit transistor cell during operation, and deterioration of high frequency characteristics is reduced. Is what happens.

[0009] The reason is that all the back surface the semiconductor substrate thickness beneath each unit transistor cells connected in parallel the same, i.e. because the heat resistance is uniform, the unit transistor cells and the edge of the central portion adjacent to the heat source during operation This is because a channel temperature difference occurs between the unit transistor cells of each unit, and a gain difference and an output difference between the unit transistor cells occur due to the transistor gain and the temperature dependency of the output at the time of high-frequency operation, resulting in non-uniform operation. .

A second problem is that the metal filling yield of the backside recess decreases. The reason for this is that the concave portion is one step, and the step is large, so that discontinuity is likely to occur at the step of the base electrode as a current bus for Au plating, for example.

Therefore, according to the present invention, among the high-output semiconductor pellets for high frequency using a material having a low thermal conductivity such as GaAs , a pellet having a multi-cell structure for high output has a small unbalance operation between cells. Provided is a technique capable of supplying pellets with low output matching loss with good yield.

[0012]

The gist of the present invention is that a high-frequency high-output GaAsFET pellet having a PHS structure is used to form a gate, a drain and a source electrode on a GaAs substrate (1). An active region (2) having the unit transistor cell (4,5,6,7) connected in parallel is formed.
5, 6, 7), a bonding wire is connected through a desired bonding pad (8) provided for each of the unit transistor cells (4, 6, 7).
5, 6, 7) are operated in parallel, and their outputs are matched outside the high- frequency high-output GaAsFET pellet to obtain high output. The high-frequency high-output GaAsFET pellet is composed of a unit transistor. The step () is formed so that the area of the unit transistor cell (5, 6) at the center part is thinner just below the active area (2) of the cell and the thickness of the unit transistor cell (4, 7) at the end is thicker than the rear face. 1a, 1b), a depression is formed in the GaAs substrate (1), and the depression is filled with a metal layer (3) by plating. 6) The GaAs just below the active region
The step formed by the thickness (a) of the s substrate (1) and the thickness (b) of the GaAs substrate (1) immediately below the active region of the unit transistor cell (4, 7) at the end is the most The thinner the thickness of the GaAs substrate (1), that is, the smaller the thickness (a) of the GaAs substrate (1) immediately below the active region of the unit transistor cells (5, 6) in the center, the smaller the thickness, and the larger the thickness. The thickness of the metal layer (3) is set to approximately 15 μm with respect to the thickest part of the GaAs substrate (1), and the thickness of the unit transistor cells (5, 6) in the central part is The thickness (a) of the GaAs substrate (1) immediately below the active region is set to about 10 μm, and the thickness (a) of the GaAs substrate (1) immediately below the active region of the unit transistor cell (4, 7) at the end portion ( b) is set to approximately 20 μm. It resides in a semiconductor device that.

[0013]

Next, an embodiment of the present invention will be described in detail with reference to the drawings. 1, 2 and 3 are top plan views, cross-sectional views taken along line BB 'in FIG. 1, and cross-sectional views taken along line AA' in FIG. 1 according to the embodiment of the present invention. Is shown.

Also in this embodiment, an active region 2 having a desired electrode is formed on a semiconductor substrate 1 to form a transistor. Transistors connected in parallel unit transistor cells (unit basic cell) 4, 5, 6, 7 are composed of, the desired bonding pad 8 provided for each unit transistor cell 4,5,6,7 And a bonding wire (not shown) is connected thereto, wiring is performed, and the unit transistor cells 4 , 5 , 6 , 7 are operated in parallel.
The output is matched outside the pellet to obtain high output.

Here, as shown in FIG. 2, the pellet of the present invention is thinner only under the active region 2 of the unit transistor cell , in the region of the unit transistor cells 5 and 6 at the center than the back surface, and at the end. A step is formed in the semiconductor substrate 1 by providing steps 1a and 1b so as to be thicker in the region of the cells 4 and 7, and then the metal layer 3 is filled in the recess.

[0016]

Embodiment 1 Next, an embodiment of the present invention will be described in detail with reference to FIGS. 1, 2 and 3. This embodiment is directed to a high-frequency, high-output GaAs FET having a PHS structure.
It is an example in a pellet.

An active region 2 having a gate, a drain, and a source electrode is formed on a GaAs substrate (semiconductor substrate) 1 to form an FET. The transistor operates the unit transistor cells 4 , 5 , 6 , 7 connected in parallel in parallel to match the output outside the pellet, thereby obtaining a high output.

Here, in the first embodiment of the present invention,
As shown in FIG. 2 and FIG. 3, only under the active region 2 of the unit transistor cell , the thickness a of the region of the unit transistor cells 5 and 6 at the center from the back surface is equal to the thickness of the region of the unit transistor cells 4 and 7 at the end. Ba = approximately 1 so as to be thinner with respect to the thickness b.
A recess having steps 1a and 1b is formed in the GaAs substrate 1 by etching or the like with a step of about 0 μm.

Thereafter, a metal such as Au , A
The g layer (metal layer 3) is filled by plating. The thickness of the metal layer 3 is larger than the thickest part of the GaAs substrate 1.
About 15 μm is desirable (the part of thickness c in FIG. 3).

Next, the operation of the embodiment of the present invention will be described in detail in comparison with the conventional example. 5, Ga directly under the unit transistor cell as in the conventional example shown in FIGS. 7 to 9
The channel temperature distribution when the thickness of the As substrate is all constant is calculated based on an example of an actually measured value.

In this case, since the absolute value of the channel temperature differs in an actual device, it is shown as a percentage with respect to the highest channel temperature. Here, the horizontal axis indicates the position between the lines AA ′ in FIG. 7 with the A side as the origin, and the vertical axis indicates the ratio of channel temperature / maximum channel temperature in the active region. The solid line indicates the temperature difference at each position, and the dashed line and the hatched portion indicate the average value in the unit transistor cell.

A temperature difference of about 30% occurs between the center and the edge of the active region, and about 14% also occurs between cells. For example, the maximum channel temperature in the unit transistor cell average is 150 ° C.,
That is, if the channel temperature of the unit transistor cells 5 and 6 at the center is 150 ° C., the unit transistor cells 4 at the end and
7 is about 128 ° C. with an average channel temperature difference of about 22 ° C.

Here, the gain and the output at the time of high frequency operation have temperature dependency, and the gain and the output change to 0.026 dB / ° C. and 0.016 dB / ° C., respectively. Therefore, about 22 ° C
If the difference of the channel temperature, the unit transistor cells 5 of the central portion, 6 a unit transistor cell end 4, about 0.6 dB in gain between 7 causes a difference 0.4 dB at the output, these A matching loss occurs when matching outside the pellet.

In the embodiment of the present invention, a step is provided so that the thickness of GaAs immediately below the active region is thinner at the unit transistor cells 5 and 6 at the center and thicker at unit transistor cells 4 and 7 at the ends. By making the thermal resistance of the unit transistor cell at the end different from that of the other, the channel temperature can be offset and the matching loss can be reduced.

FIG. 6 shows an example of a calculated value of an increase in thermal resistance with respect to the thickness of the GaAs substrate 1 in order to obtain a specific numerical value of the step. Since the absolute value of the thermal resistance varies depending on the pattern of the transistor region, the PKG used for assembling, the assembling accuracy, and the like, the absolute value is shown as a percentage with respect to the GaAs thickness of 0.

Here, the channel temperature Tch is represented by Tch = Tr + ΔTch (Tr = ambient temperature) (1), and ΔTch is represented by ΔTch = dsIdsxVdsx (1-ηadd)｝ xRth (2) Ids: Drain current at RF operation Vds: Drain voltage at RF operation ηadd: Power added efficiency Rth: Thermal resistance Therefore, the channel temperature is proportional to the thermal resistance Rth.

[0027] Thus, for example, in order to offset the average channel temperature difference between about 14% of the unit transistor cells, the unit transistor cell in the central portion shown in FIG. 1 from 6
If the thickness a of the GaAs substrate 1 immediately below the active regions 5 and 6 is, for example, 10 μm, the thickness b of the GaAs substrate 1 immediately below the active regions of the unit transistor cells 4 and 7 at the end is about 20 μm, and a step of about 10 μm is formed. Required.

This step is the thinnest GaAs substrate 1
, That is, the thickness a of the GaAs substrate 1 immediately below the active region 2 of the unit transistor cell at the center needs to be smaller, and larger as the thickness is larger.

[0029]

Embodiment 2 Next, a second embodiment of the present invention is shown in FIG. 4 as a sectional view. The thickness of the semiconductor substrate 1 just below the active region 2 of the unit transistor cell at the center and the thickness of the semiconductor substrate of the unit transistor cell at the end are provided with a continuous and uniform slope, not a step. Thereby, the channel temperature uniformity can be further improved.

[0030]

[Effect of the Invention] The first effect is, this can reduce the output matching loss of each basic cell in the high-output semiconductor pellet having a parallel-connected unit transistors cell structure
And

The reason is that a step is provided so that the thickness of the semiconductor substrate immediately below the active region of each unit transistor cell connected in parallel becomes thinner at the center where the channel temperature rises adjacent to the heat source and becomes thicker at the end. This is because the channel temperature difference is canceled by the thermal resistance difference, and the channel temperature difference between the unit transistor cells can be eliminated, thereby enabling uniform operation.

The second effect is that it is possible to improve a reduction in the yield of filling the metal into the concave portion on the back surface. The reason is that the discontinuity at the step of, for example, the Au plating current bus base electrode can be eliminated by using a plurality of steps of the concave portion, reducing each step, or inclining the steps. is there.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line BB ′ of FIG. 1;

FIG. 3 is a sectional view taken along line AA ′ of FIG. 1;

FIG. 4 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.

FIG. 5 is an explanatory diagram showing a graph of a channel temperature distribution during operation of a conventional semiconductor pellet.

FIG. 6 shows the thickness of a GaAs substrate according to the embodiment of the present invention.
It is an explanatory diagram showing graphically the thermal resistance increase with respect to the GaAs substrate thickness for explaining the optimum value.

FIG. 7 is a plan view showing a conventional semiconductor device.

FIG. 8 is a sectional view taken along line BB ′ of FIG. 7;

FIG. 9 is a sectional view taken along line AA ′ of FIG. 7;

[Explanation of symbols]

Reference Signs List 1 semiconductor ( GaAs ) substrate 1a step 1b step 2 active region 3 metal layer 4 unit transistor cell (unit basic cell) 5 unit transistor cell (unit basic cell) 6 unit transistor cell (unit basic cell) 7 unit transistor cell (unit basic) Cell) 8 Bonding pad 9 Semiconductor (GaAs) substrate 10 Metal layer 11 Active area

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/04 H01L 21/822 H01L 29/78

Claims (1)

(57) [Claims] 1. High frequency high power Ga having a PHS structure
An active region (2) having a gate, a drain, and a source electrode is formed on a GaAs substrate (1) by using an AsFET pellet to form an FET. The FET includes unit transistor cells (4, 5, 5) connected in parallel. 6, 7), and wiring is performed by connecting a bonding wire via a desired bonding pad (8) provided for each of the unit transistor cells (4, 5, 6, 7). , The unit transistor cells (4, 5, 6, 7) are operated in parallel, and the output is output from the high-frequency high-output GaAs FET.
The high-frequency high-output GaAsFET pellet is configured so as to obtain a high output by matching outside the pellet, and the unit transistor cell (5, 5) located at the center of the back surface only under the active region (2) of the unit transistor cell. The steps (1a, 1b) are provided so as to be thinner in the region of 6) and thicker in the region of the unit transistor cell (4, 7) at the end.
A recess is formed in the As substrate (1), and the recess is filled with a metal layer (3) by plating. The recess is formed immediately below the active area of the central unit transistor cell (5, 6). The step formed by the thickness (a) of the GaAs substrate (1) and the thickness (b) of the GaAs substrate (1) immediately below the active region of the unit transistor cell (4, 7) at the end is the smallest. The thinner the thickness of the GaAs substrate (1), that is, the smaller the thickness (a) of the GaAs substrate (1) immediately below the active region of the unit transistor cells (5, 6) in the center, the smaller the thickness, and the larger the thickness. The thickness of the metal layer (3) is set to about 15 μm with respect to the thickest part of the GaAs substrate (1), and the thickness of the unit transistor cells (5, 6) in the central part is The GaAs substrate just below the active area 1) The thickness of the (a) is substantially 10
μm, and the thickness (b) of the GaAs substrate (1) immediately below the active region of the unit transistor cell (4, 7) at the end is approximately 20 μm.
m, which is set to m.