JP3206562B2 - Computer system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a computer system, and more particularly to a computer system having a buffer for receiving and storing requests from a plurality of request issuing nodes via a system bus.

[0002]

2. Description of the Related Art Conventionally, a computer system of this type has a configuration in which, when the capacity of a buffer for storing requests from a plurality of request issuing nodes becomes saturated, that is, when the buffer becomes full and the requests cannot be accepted, each of the request issuing nodes becomes inoperative. In order to prevent the issuance of a request repeatedly, the issuance of the request to each request issuing node is suppressed to prevent the repeated transmission of the request. One example of such a conventional computer system is disclosed in Japanese Patent Application Laid-Open No. Hei 9-114727.

In the computer system described in the above publication, the request receiving node monitors the status of the request receiving buffer and the status of the request receiving buffer, and indicates the full status of the request receiving buffer and the status one stage before the full status. Monitoring means for notifying the above request issuing nodes. The request issuing node monitors the status of the request receiving buffer notified from the monitoring means of the request receiving node, and issues the request to the request receiving node when the request receiving buffer is in a state one stage before the request receiving buffer becomes full. Deter.

[0004]

In the above-mentioned prior art,
When the request receiving buffer is in a state one stage before becoming full, the request issuing node is suppressed from issuing a request. For this reason, in the related art, as long as there is no request transmitted between the time when the request issuance is instructed to the request issuing node and the time when the issuance of the request is actually inhibited, the remaining entry in the request reception buffer is not deleted. One stage is not valid. That is, there is a problem in that suppression of a request is started without utilizing all the resources of the request reception buffer, which are limited hardware resources.

An object of the present invention is to provide a computer system capable of receiving a request to all entries of a buffer for receiving a request while preventing unnecessary requests from being repeatedly transmitted to a bus.

[0006]

According to another aspect of the present invention, there is provided a computer system comprising: a request issuing unit; and a request receiving unit that receives a request transmitted by the request issuing unit. The request receiving means includes a buffer for storing the request, a first sending means for sending a first notification indicating that the usage of the buffer has reached a predetermined amount, and a usage of the buffer having reached the predetermined amount. Second sending means for sending a second notification indicating that the request could not be stored in the buffer when the request has been reached,
The request issuing unit includes: a inhibiting unit that inhibits issuance of a request to the request receiving unit in response to the first notification from the first sending unit of the request receiving unit; Request reissuing means for reissuing a request in response to the first and second notifications from each of the second sending means.

In another computer system according to the present invention, the reissuing means may be configured so that the first notification indicates that the used amount of the buffer has not reached a predetermined amount, and the second notification indicates that the buffer has not reached the predetermined amount. The request is reissued when it indicates that there is a request that could not be stored in the buffer.

Further, in another computer system according to the present invention, the first sending means may be configured such that the first sending means stores the first request when all requests in the buffer are stored in all stages.
Is transmitted.

A computer system according to the present invention is an information processing apparatus having a request issuing means and a request receiving means for receiving a request transmitted by the request issuing means, wherein the request receiving means comprises: a buffer for storing the request; First instructing means for instructing the request issuing means to inhibit request issuance when the used amount of the buffer reaches a predetermined amount; and requesting after the first instructing means instructs to inhibit request issuance. Second request means for instructing re-issuing of the request when there is a request issued before the issuance is suppressed, wherein the request issuing means transmits the request from the first instruction means Issuance of a request to the request receiving means when an instruction to inhibit the request is issued Includes inhibiting means, and a request reissue means for reissuing the request when the reissue request is instructed from said second instruction means.

In another computer system according to the present invention, the first instructing means instructs the issuance of the request to be issued when the requests are stored in all of the entries of the buffer. I do.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a computer system according to the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, a computer system 1000 of the present invention includes request issuing nodes 100 and 200, a request receiving node 300, and a system bus 400. The request issuing nodes 100 and 200 and the request receiving node 300 are connected to each other via a system bus 400. The request issuing nodes 100 and 200 are connected to each other by a bus acquisition signal line 500. Request issuing nodes 100 and 200 and request receiving node 30
0 is a large scale integrated circuit (Large Sca), respectively.
le Integration (LSI).

Request issuing nodes 100 and 200
Sends a request to the request receiving node 300, respectively. For example, the request issuing node 10
When 0 and 200 are processors and the request receiving node 300 is an input / output device, the requests issued by the request issuing nodes 100 and 200 include an input / output request. Hereinafter, the request issuing node 100
Will be described, the request issuing node 20
0 has the same configuration.

The request issuing node 100 includes an issue request holding buffer 110 and a reissue instruction
, Issuance suppression circuit 130 and request issuance instruction circuit 1
40. The issue request holding buffer 110 and the request issue instruction circuit 140 are connected by an issue instruction line 150. The reissue instruction line 160 connects the reissue instruction circuit 120 and the request issuance instruction circuit 140. Issue suppression circuit 130 and request issue instruction circuit 1
40 is connected by a suppression instruction line 170.

The issue request holding buffer 110 includes:
Request receiving node 30 via system bus 400
The request sent to 0 is stored.

The reissue instruction circuit 120 is connected to the system bus 4
The NO-ACK signal line 420 of 00 is monitored. NO-A
The CK signal line 420 is a signal line to which a signal indicating that there is a request that has not been accepted because the request reception buffer 310 has become full has been transmitted.
When the NO-ACK signal line 420 is valid, the reissue instruction circuit 120 notifies the request instruction circuit 140 of the reissue of the request to the request receiving node 300 via the reissue instruction line 160.

The issue suppression circuit 130 is connected to the FULL signal line 4
Monitor 30. The FULL signal line 430 is a signal line through which a signal indicating that the request reception buffer 310 has become full is transmitted. When the FULL signal line 430 is valid, the issue suppression circuit 130 notifies the request instruction circuit 140 of the request inhibition to the request receiving node 300 via the inhibition instruction line 170.

The request issuance instruction circuit 140 monitors the inhibition instruction line 170 and the reissue instruction line 160, and controls the issuance of the request held in the issuance request holding buffer 110 by the issuance instruction line 150.

Request issuing nodes 100 and 200
Have bus arbitration means for arbitrating requests sent to the system bus 400. Bus acquisition signal line 5
00 is used for bus arbitration between the request issuing nodes 100 and 200. Specifically, the request issuing nodes 100 and 200 are connected to the bus acquisition signal line 5
A bus acquisition signal is sent to the partner node via the "00".

The request receiving node 300 has a request receiving buffer 310 and a request receiving buffer counter 320.

The request receiving buffer 310 holds requests issued from the request issuing nodes 100 and 200 via the address / command signal line 410.

Request reception buffer counter 320
Detects the usage of the request reception buffer 310. In the present embodiment, it is monitored whether or not the request reception buffer 310 has become full due to requests from the request issuing nodes 100 and 200. Specifically, the request issuing nodes 100 and 200 are stored in all of the plurality of entries of the request receiving buffer 310.
It is monitored whether or not the request from is stored. When detecting that the request reception buffer 310 is in the full state, the request reception buffer counter 320 enables the FULL signal line 430. Further, the request reception buffer counter 320 instructs the suppression of request issuance by making the FULL signal line 430 valid, and then issues the request issuing nodes 100 and 20.
If there is a request issued before the request is suppressed at 0, the NO-ACK signal line 420 for instructing reissuance of the request is enabled.

The system bus 400 includes the request issuing nodes 100 and 200 and the request receiving node 300
And a system bus for connecting System bus 400
Indicates an address / command signal line 410 and a NO-ACK
It has a signal line 420 and a FULL signal line 430. The system bus 400 includes a data bus (not shown).

Next, the operation of the present embodiment will be described in detail with reference to the drawings.

Referring to FIGS. 1 and 2, at time T 2, request issuing node 100 receives bus / acquisition signal line 50, which is a request to acquire address / command signal line 410.
Enable 0.

When the address / command signal line 410 can be obtained, at time T4, the request issuing node 1
00 validates the request, ie, address and command.

At time T4, the request reception buffer 310 of the request reception node 300
It is assumed that valid requests are held up to the state before one step. At this time, the request reception buffer counter 320 is in a state one stage before the full state (FULL-1).
Is shown.

At time T6, the request reception buffer 310 becomes full due to the request issued at time T4, and the request reception buffer counter 320
Indicates a full state FULL. At the same time, the request reception buffer counter 320 enables the FULL signal line 430.

On the other hand, at time T6, the request issuing node 200 makes the bus acquisition signal line 500, which is a request to acquire the address / command signal line 410, valid. Since the FULL signal line 430 is invalid before the request issuing node 200 validates the bus acquisition signal line 500, the request issuing node 200 can acquire the address / command signal line 410, and at time T8, the address and the command signal are acquired. Enable command.

Since the request receiving buffer 310 is in the full state, it cannot receive the request issued at time T8. Therefore, the request reception buffer counter 320 enables the NO-ACK signal line 420 indicating that the request could not be received at time T10.

On the other hand, issue suppression circuits 130 and 230 of request issuing nodes 100 and 200, respectively.
Monitor the FULL signal line 430. At time T7, since the FULL signal line 430 indicates validity, the inhibition instruction lines 170 and 270 are validated, respectively. Suppression instruction lines 170 and 270 are input to the request issuance instruction circuits 140 and 240, respectively, and while the inhibition instruction lines 170 and 270 are valid, the issuance of the requests held in the issue request holding buffers 110 and 210 is suppressed. .

At time T10, the re-issuing instruction circuit 220 of the request issuing node 200 activates the re-issuing instruction line 260 at time T11 because the NO-ACK signal line 420 becomes valid for the request issued by itself. At the same time, the request issuing instruction circuit 240 is notified of an instruction to reissue the request held in the issued request holding buffer 210.

The request issuing instruction circuit 240 monitors the inhibition instruction line 270 and the re-issuing instruction line 260.
At time T15, the inhibition instruction line 270 is invalid, and
When the reissue instruction line 260 detects a valid state, the issue instruction line 250 is validated and the issue request holding buffer 21
0 is instructed to reissue the request. The issue request holding buffer 210 validates the bus acquisition signal 500,
The request is reissued by validating the address and the command on the address / command signal line 410.

In the present embodiment, the computer system 1000 has one request receiving node, but a plurality of request receiving nodes may be provided.

Further, in the present embodiment, the request issuing nodes 100 and 200 are inhibited from issuing a request when the request receiving buffer 310 is in the full state, but the usage of the request receiving buffer 310 is reduced to a predetermined amount. Request issuing node 10 when it reaches
You may be comprised so that request issue of 0 and 200 may be suppressed.

As described above, according to the present invention, the FULL signal indicating that the usage of the request reception buffer 310 has reached the predetermined amount is sent to the request reception node 300, and the usage of the request reception buffer 310 is reduced to the predetermined amount. , A request reception buffer counter 320 for transmitting a NO-ACK signal indicating a request that could not be stored in the request reception buffer 310 when
An issue suppression circuit 170 that inhibits each of the request issuing nodes 100 and 200 from issuing a request to the request receiving node 300 in response to a notification from the request receiving buffer counter 320 of the request receiving node 300; A request issuing instruction circuit 140 for reissuing a request in response to a notification from the buffer counter 320 is provided. Therefore, the request can be received by all entries of the request reception buffer 310 while preventing unnecessary requests from being repeatedly sent to the system bus 400.

[0037]

As is apparent from the above description, according to the present invention, the first notification indicating that the used amount of the buffer for storing the request has reached the predetermined amount, and the used amount of the buffer has reached the predetermined amount. A request receiving unit that sends out a second notification indicating that the request could not be stored in the buffer in that case, and suppressing the issuance of the request to the request receiving unit in response to the first notification from the request receiving unit. Request issuing means for reissuing the request in response to the first and second notifications from the request receiving means. Therefore, there is an effect that the request can be received by all entries of the buffer that receives the request while preventing unnecessary requests from being repeatedly transmitted to the bus.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a waveform chart showing an operation of the first exemplary embodiment of the present invention.

[Explanation of symbols]

 1000 Computer system 100, 200 Request issuing node 110 Issue request holding buffer 120 Reissue instruction circuit 130 Issue suppression circuit 140 Request issue instruction circuit 300 Request receiving node 310 Request receiving buffer 320 Request receiving buffer counter 400 System bus 500 Bus acquisition signal line

Claims (1)

(57) [Claims] 1. A computer system comprising: a request issuing unit; and a request receiving unit for receiving a request transmitted by the request issuing unit. The request receiving unit comprises: a buffer for storing the request; The buffer's en
First instructing means for instructing the request issuing means to inhibit request issuance when the number of birds reaches the total number of stages; and request issuing is inhibited after the first instructing means instructs request issuance inhibition. And a second instructing means for instructing re-issuing of the request when there is a request issued before the request is issued. Including an inhibiting means for inhibiting the issuance of a request to the request receiving means when instructed, and a request reissuing means for reissuing the request when an instruction to reissue the request is issued from the second instructing means A computer system characterized by the following: