JP3206580B2 - DMA data transfer control method and input / output processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a DMA data transfer control method and an input / output processing device in a computer system.

[0002]

2. Description of the Related Art DMA (Direct Memory)
The Access control method includes a hardware mechanism dedicated to data transfer between a central processing unit (CPU) and a peripheral device, and centrally processes data transfer between a main memory and a peripheral device according to an instruction from the central processing unit. This is a system that performs autonomous operation independently of the operation of the device. In particular, in a large-scale computer, the DMA mechanism which is a hardware mechanism for DMA transfer is used.
An input / output processing device (I) having a plurality of hardware resources
OP) is provided between the central processing unit and the peripheral devices, and the D channel between the main memory and many peripheral devices is controlled by the channel control method.
I / O that executes data transfer by MA control system in parallel
An O processor system is adopted.

In a conventional input / output processing device, when a data transfer request is made from a central processing unit, the request is an output transfer from a main memory to a peripheral device, or vice versa. Regardless of the input transfer, the DMA hardware resources are allocated with the same weight. That is, input transfer, O
There is no particular difference in the probability of allocating DMA hardware resources due to the difference in output transfer.

[0004]

By the way, in the input and output in the computer system, the input transfer and the output
It is said that the ratio of the t transfer is 2: 1 or 3: 1. The ratio of the input transfer to the output during the entire transfer is Outpu.
More than t transfers. Also, taking as an example data transfer to and from a magnetic disk device which is considered to occupy most of the DMA data transfer, Output transfer tends to have a shorter processing time than Input transfer for the same data length. . The reason is that at present, most magnetic disk devices have a disk cache, and when the cache is empty, an address,
When the data is written, the write operation is completed and the I / O processing unit does not have to wait until the writing to the disk medium is completed. On the other hand, in the input transfer, the disk seek is performed to read the data from the disk medium to the cache. This is because the time and the rotation waiting time are involved.

[0005] For this reason, in the prior art in which the probability of allocating DMA hardware resources does not differ depending on the difference between input transfer and output transfer as described above, all DMA hardware resources are blocked by input transfer, and output transfer is performed. Is often awaited, which has been a factor in reducing the system throughput.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to improve the throughput by controlling the allocation of DMA hardware resources so that the DMA transfer does not block the DMA hardware resources during DMA data transfer. .

[0007]

According to the DMA data transfer control method of the present invention, an address register, a data register, and a
Counter, various control flags, and control these
A DMA that includes a control unit and performs a plurality of DMA data transfers in parallel between a main memory and a peripheral device by using a plurality of DMA hardware resources in which information necessary for the DMA transfer is set and operates independently. In the data transfer control method,
Depending on the difference between input transfer and output transfer, D
A difference is made between the allocation probabilities of the MA hardware resources. Specifically, the plurality of DMA hardware resources can be transferred only by the first resource group used for both the input transfer from the peripheral device to the main memory and the output transfer from the main memory to the peripheral device and the output transfer. It is divided into a second resource group to be used, and at the time of input transfer, an unused resource is allocated from the first resource group. At the time of output transfer, an unused resource is allocated from the first and second resource groups. It is characterized by assigning things. As a result, the DMAs included in the second resource group
Hardware resources are not allocated for input transfer, but are dedicated to output transfer.
This prevents all DMA hardware resources from being blocked by transfer.

Further, the input / output processing device of the present invention has an address
Registers, data registers, counters, various control flags
And n independent DMAs, each of which includes a control unit for controlling these and sets information necessary for DMA transfer and operates independently
It has hardware resources, and has a plurality of Ds between a main memory and a peripheral device based on a data transfer request from a central processing unit.
In an input / output processing device that performs MA data transfer in parallel, when the requested data transfer is an input transfer from a peripheral device to a main memory at the time of a data transfer request from the central processing unit, the n DMAs An unused DMA hardware resource is searched for by using nm of the hardware resources as a search range and allocated for the input transfer. When the requested data transfer is an output transfer from the main memory to the peripheral device, The unused DMA hardware resources are used as search ranges for unused DMA hardware resources.
A hardware lock control unit that searches for hardware resources and allocates the hardware resources for the output transfer is provided.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a schematic configuration diagram of an embodiment of the present invention. In the figure, A indicates a case where a plurality of DMA data transfers between the main memory C and the peripheral device D are performed by using a plurality of DMA hardware resources B which are independently set with information necessary for the DMA transfer. It is an input / output processing device that is performed in parallel. The plurality of DMA hardware resources B are used for input transfer from the peripheral device D to the main memory C and for the main memory C
Are logically divided into a first resource group E used for both Output transfer to the peripheral device D and a second resource group F used only for Output transfer. D
Assuming that the total number of MA hardware resources B is n and the number of DMA hardware resources B included in the second resource group F is m, the DMA number included in the first resource group E is
The number of hardware resources B is nm. The value of m is determined in consideration of the ratio between the input transfer and the output transfer, and is, for example, 1, 2, or the like.

When a data transfer request is sent from a central processing unit (not shown), the input / output processing unit A requests the data transfer from the peripheral device D to the main memory C or vice versa. It is determined whether the transfer is an Output transfer to D. Next, in the case of the input transfer, the unused DMA hardware resources B
Is searched and assigned for the input transfer. next,
Information necessary for DMA data transfer is set in the DMA hardware resource B to prepare for DMA transfer, and then the DMA hardware resource B is used to transfer a DMA from the peripheral device D to the main memory C. Perform data transfer. When the DMA data transfer ends, the D
The MA hardware resource B is returned to the unused state.

On the other hand, when a request from a central processing unit (not shown) is an output transfer, an unused DMA hardware resource is searched for from the first resource group E and the second resource group F, and the output transfer is performed. Assign for As the search order at this time, for example, the first resource group E is searched first, and if there is no unused DMA hardware resource in the first resource group E, then the second resource group E Search in F. Next, information necessary for DMA data transfer is set for the DMA hardware resource to prepare for DMA transfer, and then the DMA hardware resource is used to transfer data from the main memory C to the peripheral device D. Performs DMA data transfer. When the DMA data transfer is completed, the DMA hardware resource B is returned to the unused state.

If the input / output processing device A has a processor controlled by firmware, the
The search for the DMA hardware resources for the t transfer and the output transfer is performed by executing a predetermined microinstruction.

As described above, the input / output processing device A of the present embodiment
According to the above, the DMA hardware resource B included in the second resource group F is not allocated for input transfer, and is dedicated to output transfer.
This prevents all DMA hardware resources B from being blocked by nput transfer.

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing an example of a computer system to which the present invention is applied. The computer system of this example includes a main storage device 1, a central processing unit 2, a global bus 6 connecting them, an input / output processing unit 3 connected to the central processing unit 2, and a connection to the central processing unit 3. Done 1
It is composed of at least one peripheral processing device (for example, a magnetic disk device) 4 and one or more peripheral devices (for example, a magnetic disk device) 5 connected to each peripheral processing device 4. Although the computer system of this example has only one input / output processing device 3 connected thereto, the present invention is also applicable to a computer system having a plurality of input / output processing devices.

FIG. 3 shows an example of the internal configuration of the central processing unit 2. The central processing unit 2 of this example includes an arithmetic processing unit (EP
U) 21, a global bus controller (GBC) 22 connected to the global bus 6, and an input / output controller (IOC)
23, arithmetic processing unit 21, global bus control unit 22
And a local bus 25 interconnecting the input / output control unit 23, the input / output control unit 23 and each input / output processing device (IO
P) 3 and a general-purpose port (GPC) 24 provided therebetween. The arithmetic processing unit 21 corresponds to a central processing unit in a narrow sense, and the DMA data transfer between the main storage device 1 and the peripheral device is performed independently of the operation of the arithmetic processing unit 21. In this case, the data transfer path in the case of the input transfer is a path from the input / output processing device 3 → the general-purpose port 24 → the input / output control unit 23 → the global bus control unit 22 → the main storage device 1.
In the case of the output transfer, the main storage device 1 → global bus control unit 22 → input / output control unit 23 → general-purpose port 24 →
This is a path of the input / output processing device 3.

The connection form between the input / output processing device 3 and the main storage device 1 is not limited to those shown in FIGS. 2 and 3, for example, the main storage device 1, the central processing device 2, the input / output processing device 3 May be mutually connected via a system control unit (SCU).

Referring again to FIG. 2, the input / output processing device 3 in this embodiment comprises a processor 31, a local memory 32 connected thereto, two channel controllers 33 connected to the processor 31, Channel control unit 33
And one or more peripheral processing devices 4 are connected to each channel 34. The processor 31 is a part that executes main processing of the input / output processing device 3, is controlled by the firmware 311, and has n DMA hardware resources 3.
13-1 to 313-n, and a hardware lock control unit 312 for managing and controlling the hardware lock control unit. The local memory 32 stores information necessary for DMA data transfer (transfer destination, transfer source, start address,
DMA transfer control areas 321-1 to 321-m for storing data transfer amounts (counts, control flags, and the like) are appropriately generated. The channel control unit 33 has an interface between the channel 34 and the processor 31, and controls the channel 34. The channel 34 has an interface with the peripheral processing device 4 and performs data transfer with the peripheral device 5 through the peripheral processing device 4.

Each DMA hardware resource 313
-1 to 313-n all have the same configuration, and are composed of all hardware necessary for DMA data transfer, such as an address register, a data register, a counter, various control flags, and a control unit for controlling these. DMA hardware resources 313-1 to 313-n
The information required for data transfer (transfer destination, transfer source, start address, data transfer amount (count)) is set by the firmware of the processor 31, and when the start of data transfer is instructed, it is independent of the firmware thereafter. Then, data is transferred between the main storage device 1 and the peripheral processing device 4 via the channel control unit 33 and the channel 34.

DMA hardware resources 313-1 to 313-1
The number of 313-n is arbitrary as long as it is plural, but in this embodiment, n = 32, that is, 32 in total. DMA hardware resources 313-1 to 313-
n is numbered from 1 to 32.

The input / output processing device 3 according to the present embodiment generally operates as follows.

(1) First, upon receiving a request from the central processing unit 2, the processor 31 of the input / output processing device 3 reads a channel program from the main storage device 1 based on the request, interprets the channel program, and Information necessary for data transfer, such as a transfer destination, a data transfer source, a start address, and a data transfer amount (count), is stored in one DMA transfer control area 321-i (i = 1 to m) secured on the local memory 32. Store. Then, one logical processing unit (process) is activated in the processor 31 by the channel program, and is connected to the channel program execution queue. At this point, the DMA hardware resources have not been allocated yet.

(2) When the above-mentioned process shifts from the execution wait state to the execution state, the hardware lock control unit 312 removes unused DMA hardware resources 313-j (j = 1 to n) as described later. Get one (lock)
Is done. Then, the data transfer control information stored in the DMA transfer control area 321-i is stored in the acquired DMA hardware resource 313-j, and preparation for DMA transfer is performed. At this point, the DMA hardware resources have been allocated.

(3) After that, the processor 31 issues a transfer request to the channel controller 33, and the channel controller 33 issues a transfer request to the corresponding channel 34,
The channel 34 establishes a connection with the corresponding peripheral device 5 via the peripheral processing device 4.

(4) After the connection is established, the main storage 1
← → DMA hardware resource 313-j ← → channel control unit 33 ← → channel 34 ← → peripheral processing unit 4 ← →
Data transfer is performed between the peripheral devices 5. And DMA
When the predetermined data transfer ends, the hardware resource 313-j interrupts the firmware 311 of the processor 31. When the firmware 311 confirms the end of the data transfer, the DMA hardware resource 313
-J is released, and an interrupt is issued to the central processing unit 2 to notify that the data transfer has been completed. Further, the firmware 311 releases the DMA transfer control area 321-i on the local memory 32.

Here, in the processor 31, up to 64 processes can be started simultaneously. In this example, there are 32 DMA hardware resources. Therefore, in this embodiment, logical DMA data transfer processing can be started up to 64 multiplexes, and actual DMA data transfer can be operated with 32 multiplexes (of course, there are n or more channels 34).

Next, the DMA hardware resource allocation, which is a feature of this embodiment, will be described in detail.

FIG. 4 is a block diagram showing a configuration example of the hardware lock control unit 312. The hardware lock control unit 312 of this example includes a control unit 3121 and hardware lock registers (HW lock registers) 3122-1 to 1222 -n corresponding to the DMA hardware resources 313-1 to 313-n on a one-to-one basis. And the selector 312
3 and a hardware resource number register (HW resource number register) 3124.

Hardware lock register 3102-1
3122-n are registers for managing whether or not the corresponding DMA hardware resources 313-1 to 313-n are currently being used, and if so, what kind of DMA data transfer is being used. , As shown in FIG.
Holds valid bits and information on the DMA transfer control area.
The valid bit is set to “0” when the DMA hardware resource corresponding to the hardware lock register is not used, and is set to “1” when the DMA hardware resource is used. The information of the DMA transfer control area is valid only when the valid bit is "1", and the D which activates the lock processing of the DMA hardware resource corresponding to the hardware lock register is activated.
Information for specifying the MA transfer control area is stored.

Hardware resource number register 312
Reference numeral 4 denotes a register for storing a result of the DMA hardware resource lock process executed by the control unit 3121, and holds a valid bit and a DMA hardware resource number as shown in FIG. The valid bit is set to “0” when the lock fails (unusable) and is set to “1” when the lock succeeds (usable). The DMA hardware resource number is valid only when the valid bit is “1”, and stores the number of the DMA hardware resource that has been successfully locked.

The control means 3121 is a part for executing processing related to DMA hardware resource allocation control. In the present embodiment, a microinstruction for locking the DMA hardware resource is provided for each data transfer direction, and the microinstruction is selectively used depending on the data transfer direction. That is, one of the micro instructions, the LCHR instruction, is n
Of the DMA hardware resources 313-1 to 313-n (32 in this embodiment), n-1 (i.e., 31) are to be locked. One LCHRA locks all n DMA hardware resources 313-1 to 313-n. The control unit 3121 performs processing for locking only one DMA hardware resource using the LCHR instruction at the time of input transfer, and only one DMA hardware resource using the LCHRA instruction at the time of output transfer. Perform lock processing.

FIG. 6 is a flowchart showing an example of a DMA hardware resource lock process performed by the control means 3121 of the hardware lock control unit 312. As already described in the schematic operation of the present embodiment, the lock processing of the DMA hardware resource by the hardware lock control unit 312 is performed by the D lock secured in the local memory 32.
This is executed after information necessary for DMA data transfer is stored in the MA transfer control area 321-i.

The control means 3121 first reads out the information stored in the DMA transfer control area 321-i and outputs the information from the information of the data transfer destination and the data transfer source therein.
t transfer or input transfer (step S
1). If the transfer is an input transfer, the lock processing is performed by the LCHR instruction (step S2), and the output is performed.
If the transfer is t, the lock processing is performed by the LCHRA instruction (step S3).

FIG. 7 shows a flow of processing executed by the LCHR instruction. First, after initially setting the variable n to 1, the control unit 3121 selects the output of the hardware lock register 3102-1 by the selector 3123 and checks its valid bit (step S11). If the valid bit is “1” indicating that it is in use (No in step S12), the variable n is incremented by 1 to 2 (step S15), and step S15 is performed.
Returning to the process of No. 11, the above process is repeated. When the hardware lock register 3122-j in which the valid bit is “0” indicating unused is found (Yes in step S12), the lock is successful. At this time, the valid bit of the hardware lock register 3122-j is set to “1”, the information for specifying the DMA transfer control area 321-i is set in the information of the DMA transfer control area, and The valid bit of the hardware resource number register 3124 is set to “1”, and the number of the DMA hardware resource corresponds to the DM corresponding to the hardware lock register 3122-j.
The number of the A hardware resource 312-j is set (step S13). Then, the process according to the LCHR instruction is completed.

On the other hand, if the hardware lock register whose valid bit is “0” indicating unused is not found even after checking the hardware lock register 3122-31 (Yes in step S14), the lock is disabled. It is a failure. At this time, the valid bit of the hardware resource number register 3124 is set to "0" (step S16), and the process according to the LCHR instruction ends.

FIG. 8 shows a flow of processing executed by the LCHRA instruction. The content of the process is almost the same as the process of FIG. 7 executed by the LCHR instruction,
The final value of the search range in 4 is 31 in the LCHR instruction, but is 32 in the LCHRA. Therefore, in the LCHRA instruction, even if the hardware lock register whose valid bit is “0” indicating that the valid bit is not used is not found even when the hardware lock register 3122-31 is checked, the last 32nd hardware lock register 3122-31 is not used. If the valid bit of the wear lock register 3122-32 is "0" indicating unused, the corresponding DMA hardware resource 313-32 is allocated.

If the DMA hardware resource lock processing is successful, the hardware resource number register 3
The contents of 124 (particularly the numbers of the DMA hardware resources) are stored in the DMA transfer control area 321-i of the activation source by the firmware. DMA transfer control area 3
The number of the DMA hardware resource stored in the DMA transfer control area 321-i is the information necessary for the DMA data transfer (data transfer destination, data transfer source, start address, data transfer) stored in the DMA transfer control area 321-i. The amount is used to specify a DMA hardware resource to be set.

In the case of lock failure, that is, Inpu
When all of the 31 DMA hardware resources 1 to 31 are blocked at the time of the t transfer,
If all 32 DMA hardware resources from No. 1 to No. 32 are blocked at the time of the tput transfer,
The DMA hardware resource lock process is repeated until the lock succeeds.

As described above, in this embodiment, there are 32 D
The last DMA hardware resource 313-32 of the MA hardware resources 313-1 to 313-32
Can be dedicated to output transfer, so that all DMA hardware resources can be prevented from being blocked by input transfer.

In the above embodiment, n (32 in the example)
Only one of the DMA hardware resources is Ou
Although reserved for tpout transfer, in general,
m (1 ≦ m <n) DMA hardware resources are O
Reserved for output transfer. Here, the actual value of m is optimized according to the ratio between the input transfer and the output transfer. The ratio of Input / Output transfer can be checked, for example, as follows.

Generally, an input / output processing device has a tracer function as a debugging function. This tracer function is a function in which the firmware 311 of the processor 31 stores processing information of data transfer in the local memory 32 in real time. Therefore, by operating this tracer function for a certain period of time, and then extracting the stored processing history information, the ratio of Input / Output transfer can be checked. Also, since the OS keeps history information even when the software of the central processing unit 2 starts data transfer, it is also possible to take out this information and check it.
The ratio of Output transfer can be checked.

When the ratio of the input transfer is relatively large, and when m = 1, all DMA hardware resources are blocked by the input transfer, and there are many cases where the output transfer is more waiting than the input transfer. , M = 2 (or a value of 2 or more).

In the embodiment in which only m of the n DMA hardware resources are reserved for output transfer, n of the n DMA hardware resources 313-1 to 313-n is used as the LCHR instruction. A microinstruction that locks m is used. The processing by this microinstruction is the same as in FIG. However, the determination condition in step S14 is n ≧ (nm).

[0045]

As described above, according to the present invention, even if nm DMA hardware resources out of n DMA hardware resources are all blocked, m DMA hardware resources are dedicated to output transfer. As a result, the ratio of the input transfer is higher than that of the output transfer, and the processing time of the input transfer is output.
Even in a situation where it takes longer than the processing time for the t transfer, it is possible to prevent the output transfer from being waited due to all DMA hardware resources being blocked by the input transfer, thereby improving the system throughput.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an example of a computer system to which the present invention has been applied.

FIG. 3 is a block diagram illustrating an example of an internal configuration of a central processing unit.

FIG. 4 is a block diagram illustrating a configuration example of a hardware lock control unit.

FIG. 5 is an explanatory diagram of contents of a hardware lock register and a hardware resource number register.

FIG. 6 shows D performed by a control unit of a hardware lock control unit.
9 is a flowchart illustrating an example of an MA hardware resource lock process.

FIG. 7 is a diagram showing a flow of a process executed by an LCHR instruction.

FIG. 8 is a diagram showing a flow of processing executed by an LCHRA instruction.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Main storage device 2 ... Central processing unit 3 ... I / O processing unit 31 ... Processor 311 ... Firmware 312 ... Hardware lock control unit 313-1 to 313-n ... DMA hardware resource 32 ... Local memory 321-1 to 321 -M DMA transfer control area 33 Channel control unit 34 Channel 4 Peripheral processing unit 5 Peripheral device

Claims (6)

(57) [Claims] 1. An address register, a data register, and a
Counter, various control flags, and control these
A DMA that includes a control unit and performs a plurality of DMA data transfers in parallel between a main memory and a peripheral device by using a plurality of DMA hardware resources in which information necessary for the DMA transfer is set and operates independently. In the data transfer control method, the plurality of DMA hardware resources are used only in a first resource group used for both an input transfer from a peripheral device to a main memory and an output transfer from a main memory to a peripheral device, and only for the output transfer. , And allocates unused resources from the first resource group at the time of input transfer, and allocates unused resources from the first and second resource groups at the time of output transfer. A DMA data transfer control method, wherein 2. A DMA used for input transfer by using a first microinstruction for locking one unused DMA hardware resource from the first resource group.
DMA hardware resources used for output transfer by using a second microinstruction for allocating hardware resources and locking one unused DMA hardware resource from the first and second resource groups 2. The DMA data transfer control method according to claim 1, further comprising : 3. The second microinstruction first searches for unused DMA hardware resources in the first resource group, and searches for unused DM hardware resources in the first resource group.
3. The DMA data transfer control method according to claim 2, wherein an unused DMA hardware resource is searched for from the second resource group when the A hardware resource does not exist. 4. An address register, a data register and a power register.
Counter, various control flags, and control these
Having n DMA hardware resources including a control unit and operating independently with information required for DMA transfer being set,
An input / output processing device that performs a plurality of DMA data transfers in parallel between a main memory and a peripheral device based on a data transfer request from a central processing unit. When the transfer is an input transfer from the peripheral device to the main memory, an unused DMA hardware resource is searched for by using nm of the n DMA hardware resources as a search range, and the input DMA transfer is performed. And the requested data transfer is O from the main memory to the peripheral device.
In the case of output transfer, a hardware lock control unit is provided which searches for unused DMA hardware resources by using all of the n DMA hardware resources as a search range and allocates the DMA hardware resources for the output transfer. Input / output processing unit. 5. The hardware lock control unit sets an unused DMA hardware resource to one of the n DMA hardware resources with a search range of nm.
Using the first microinstruction to find and lock
A second microinstruction for allocating a DMA hardware resource to be used for nput transfer and searching for and locking one unused DMA hardware resource using all of the n DMA hardware resources as a search range is used. And allocating a DMA hardware resource to be used for the output transfer.
5. The input / output processing device according to 4 . 6. The second micro-instruction first comprises:
When an unused DMA hardware resource is searched for from the (nm) th to (nm) th DMA hardware resource groups and no unused DMA hardware resource is found in the search, 6. The input / output processing device according to claim 5 , wherein an unused DMA hardware resource is searched for from the remaining DMA hardware resources.