JP3206652B2 - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device and a method of manufacturing a semiconductor device capable of protecting a MOS transistor from plasma damage in a manufacturing process. It is about.

[0002]

2. Description of the Related Art Conventionally, electric charges are accumulated in a gate insulating film of a semiconductor device during a manufacturing process of the semiconductor device, especially in various processing steps using plasma.
The charge is gradually accumulated in the gate insulating film at a stage where the plasma processing is repeated, and when the charge exceeds a certain charge accumulation level, the charge flows into the substrate, and at this time, the gate insulating film is deteriorated or destroyed. There are many things and many measures have been proposed.

Specifically, charges are accumulated in a gate electrode by a plasma process such as etching and chemical vapor deposition, and the gate insulating film is deteriorated. Conventionally, a protection diode has been used as a protection element for protecting the device from damage due to the plasma process. less than,
A specific example of a conventional protection diode for protecting an N-type MOS transistor will be described. That is, FIG. 31 is a plan view thereof, and FIG. 32 is a sectional view taken along line AA of FIG.

For example, as shown in FIG. 31, in the case of protection of an N-type MOS transistor 15, the N-type diffusion layer 31 of a protection diode 30 composed of an N-type diffusion layer 31 and a P-type substrate 1 is used.
By connecting the gate electrode 5 to the gate electrode 5, the negative stored charge of the gate electrode 5 is discharged by the forward current of the protection diode 30, and the positive stored charge is discharged at the time of the reverse breakdown. It was discharging with current.

[0005] The gate electrode 5 of the N-type MOS transistor 15 is connected to the protection diode 30 using the first metal wiring 7. In this case, the connection must always be made using the first metal wiring layer, which affects the layout of the first metal wiring layer. FIG. 33 shows such a conventional manufacturing method.
This will be specifically described with reference to FIGS. An element isolation region 3 is formed on a P-type substrate 1. (FIG. 33) Next, the gate electrode 5 having the gate insulating film 4 is formed. (FIG. 34) Thereafter, the N-type impurity is ion-implanted at a high concentration using the resist 18 formed in a predetermined shape by a commonly known method as a mask to form the N-type diffusion layer 8 serving as the source and drain of the N-type MOS transistor 15. At the same time, the N-type diffusion layer 31 of the protection diode 30 is formed (FIG. 35).

Next, after an interlayer insulating film 24 is entirely formed, an N-type diffusion layer 31 and a contact 6 reaching the gate electrode 5 are formed.
Is formed (FIG. 36). Then, the first metal wiring 7 is formed, and the N-type MOS transistor 15 and the protection diode 3 are formed.
0 is connected (FIG. 37).

[0007]

However, when the thickness of the gate insulating film is reduced to 4.5 nm or less, the breakdown voltage of the diode becomes almost equal to the breakdown voltage of the gate insulating film. Therefore, the protection of the diode is no longer effective against the positive accumulated charges. Therefore, recently, a protective element effective especially for positive accumulated charges has been demanded.

Japanese Patent Application Laid-Open No. H10-154808 discloses a configuration in which a plurality of independent dummy electrodes are provided so that charges are not concentrated on a gate insulating film in one electrode. In addition to being long, the structure becomes complicated, and it is impossible to protect the gate insulating film that one wants to protect reliably. Further, Japanese Patent Application Laid-Open Nos. Hei 7-130881 and Hei 5-343684 merely disclose a technique using a diode using a diffusion layer, and do not solve the above problem.

Accordingly, an object of the present invention is to improve the above-mentioned drawbacks of the prior art, and to efficiently discharge charges accumulated in a device by a plasma process in a portion of a gate electrode portion different from a gate insulating film portion. Accordingly, a semiconductor device capable of protecting a MOS device from plasma damage and a method for manufacturing the semiconductor device are provided.

[0010]

SUMMARY OF THE INVENTION The present invention basically employs the following technical configuration to achieve the above object. That is, the first according to the present invention
As an embodiment of the present invention , the MOS transistor and the
The protection element arranged close to the MOS transistor
A semiconductor device provided with the MOS transistor.
And the protection element share a gate insulating film,
Electric field applied to the gate insulating film included in the protection element
The gate whose strength is included in the MOS transistor
If it is configured to be stronger than the electric field strength applied to the insulating film,
In both cases, a highly conductive region is formed in the gate insulating film of the protection element.
And thereby the MOS transistor
When charge is accumulated in the gate insulating film during the manufacturing process,
The electric charge accumulated in the insulating film is used for the gate insulation of the protection element.
Semiconductor configured to be discharged to the substrate through the film
Device, and in a second aspect according to the present invention, a substrate
Above, the MOS transistor and the MOS transistor
Semiconductor device provided with a protection element arranged in close proximity
When manufacturing the MOS transistor and the protection
Elements are mounted on substrates or wells with different conductivity.
And included in the MOS transistor.
The gate insulating film and the gate insulating film included in the protection element.
Integrally formed, and further includes the gate included in the protection element.
The electric field strength applied to the gate insulating film depends on the MOS transistor.
Charge is stored in the gate insulating film contained in the
When stacked, stronger than the electric field strength applied to the insulating film
And a gate insulating film of the protection element.
Semiconductor device that forms a highly conductive region for connecting
It is a manufacturing method of the device.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The semiconductor device and the method of manufacturing the semiconductor device according to the present invention employ the above-described technical configuration. Therefore, the electric charge accumulated in the device by the plasma process is transferred to the gate of the MOS transistor. A protection element having a dummy gate insulating film capable of discharging more efficiently than the insulating film portion is provided.

That is, in the semiconductor device according to the present invention, when the gate electrode is positively charged, the surface of the P well under the gate electrode becomes an inversion region, and the surface of the N well under the gate electrode becomes an accumulation region. . When the inversion region is formed, the voltage applied to the gate electrode is divided into a voltage applied to the gate insulating film and a voltage for forming the inversion layer. But,
When the storage region is formed, the voltage applied to the gate electrode is
All are added to the gate insulating film. That is, the electric field is stronger in the gate insulating film on the N well.

Further, even on the same P-type substrate, an N-type MO
When the potentials of the source and drain of the S transistor are not fixed, electrons for forming an inversion layer on the surface of the P-type substrate are insufficient, and the depletion layer extends toward the P-type substrate. Therefore, no voltage is applied to the gate insulating film any more, and the current flowing through the gate insulating film is saturated. That is, the electric field applied to the gate insulating film of the transistor whose source and drain potentials are not fixed is weaker than the electric field applied to the gate insulating film of the transistor whose source and drain potentials are fixed.

That is, in the present invention, by utilizing the difference in the electric field applied to the gate insulating film, the accumulated charge by the plasma process is discharged through the gate insulating film of the protection element.
It is characterized in that the gate insulating film of the N-type MOS transistor is protected.

[0015]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the structure of a semiconductor device according to the present invention and a method for manufacturing the semiconductor device. That is, FIGS. 1 to 4 are a plan view and a sectional view, respectively, showing the configuration of a specific example of the semiconductor device according to the present invention. In the drawings, the MOS transistor 15 and the MOS transistor 15 In the semiconductor device 100 provided with the protection element 16 disposed in the same manner, the gate insulating film 4-4 included in the protection element 16 is provided.
2 shows the semiconductor device 100 configured so that the electric field intensity applied to the gate insulating film 4-1 included in the MOS transistor becomes stronger than the electric field intensity applied to the MOS transistor.

In the present invention, more specifically, the M
The OS transistor 15 is formed on a P-type substrate, and the protection element 16 is formed on an N-type well. Hereinafter, a first specific example of the semiconductor device according to the present invention will be described in detail. As a first specific example of the present invention, a protection element for protecting a gate electrode of an N-type MOS transistor when a positive charge is accumulated will be described.

FIG. 1 is a plan view thereof. The protection element 16 having the dummy gate insulating film 4-2 formed on the N well 2 is connected to the N-type MOS transistor 15. FIG.
FIG. 2 is a sectional view taken along line A in FIG. FIG. 3 is a cross-sectional view taken along a line B in FIG. FIG. 4 is a sectional view taken along line C in FIG. The gate electrode 5 of the N-type MOS transistor 15 is extended to the protection element 16.

The N-type MOS transistor 15 is formed on the P-type substrate 1 as shown in FIG.
It is formed on the N well 2 as shown in FIG. On the other hand, as shown in FIG.
The N-type diffusion layer 9 in the well 2 is brought into contact with the P-type diffusion layer 10 in the P-type substrate 1. The protection element 16 is an N-type MOS
Since the transistor 15 and the gate electrode 5 are shared,
In order to connect the N-type MOS transistor 15 and the protection element 16, it is not necessary to use the first metal wiring 7 used in the conventional example, and the layout of the first metal wiring layer is not affected.

Further, in the specific example of the present invention, the voltage applied to the gate electrode 5 by the positive charge accumulated in the plasma process is the N-type MOS transistor 1
5, the protection element 16 is the same, but the gate insulating film 4
-2 has a stronger electric field than the gate insulating film 4-1. The current flowing through the gate insulating film is determined by the electric field applied to the gate insulating film. Therefore, since the gate current flows more in the N-well 2 serving as the accumulation region, the electric charge accumulated by the plasma process is discharged through the dummy gate insulating film 4-2 on the N-well 2.

As a result, the N-type MOS transistor 15
The gate insulating film 4-1 is protected because almost no current flows. Next, an example of a method of manufacturing the first specific example of the semiconductor device according to the present invention will be described in detail with reference to FIGS. That is, regarding the description of the method of manufacturing the N-type MOS transistor 15 and the protection element 16 for protecting the N-type MOS transistor 15, the left side in FIGS.
The cross section of the transistor 15 is shown, and the right side is a cross section of the protection element 16.

First, as shown in FIG. 5, an element isolation region 3 is formed on a P-type substrate 1. Next, as shown in FIG. 6, an N well 2 is formed by implanting an N type impurity into the P type substrate 1 using a resist 17 having a predetermined shape as a mask. Then, FIG.
As shown in FIG. 7, after removing the resist 17, the gate insulating film 4-
After forming 1, 4-2, the gate electrode 5 is formed in a predetermined shape.

Subsequently, as shown in FIG. 8, an N-type impurity is ion-implanted at a high concentration using a resist 18 having a predetermined shape as a mask to form an N-type diffusion layer 8 serving as a source and a drain of the MOS transistor 15. An N-type diffusion layer 9 for obtaining the potential of the protection element 16 is formed. However, this N
The type diffusion layer 9 does not need to be adjacent to the gate electrode 5 and may be at any position on the N well 2.

Thereafter, after the resist 18 is peeled off, as shown in FIG. 9, a P-type impurity is ion-implanted at a high concentration using the resist 19 having a predetermined shape as a mask, and the P-type impurity in contact with the N-type diffusion layer 9 is formed.
A P-type diffusion layer 10 is formed on a type semiconductor substrate. If each of the N-type diffusion layer 9 and the P-type diffusion layer 10 has a high concentration,
Since the current easily flows due to the tunneling phenomenon, it can be regarded as being conductive.

That is, the N well 2 of the protection element 16 is:
It can be considered that it is electrically connected to the P-type substrate 1. The electric charge accumulated in the gate electrode 5 by the plasma process flows through the gate insulating film 4-2 of the protection element and is discharged to the substrate. Next, as shown in FIG. 10, after forming an interlayer insulating film 24 over the whole, the N-type diffusion layer 8 of the N-type MOS transistor 15 and the contact 6 reaching the gate electrode 5 are formed, and the first metal wiring 7 is formed. I do.

Of course, a similar structure is effective for this protection in order to reduce damage due to negative accumulated charges in the P-type MOS transistor. Although a current flows through the gate insulating film 4-2 of the protection element 16, the gate insulating film 4-2 is deteriorated, but there is no problem in practical use as long as the gate insulating film 4-2 does not break down. To explain the operation of the semiconductor device in this specific example, the positive accumulated charge is an N-type MOS
The discharge is performed to the P-type substrate 1 through the gate insulating film 4-2 of the protection element 16 without flowing through the gate insulating film 4-1 of the transistor 15.

When a positive voltage is applied to the gate electrode 5,
Since the N-type MOS transistor 15 is formed on the P-type semiconductor substrate, an inversion layer is formed. On the other hand, since the protection element 16 is formed on the N well 2, an accumulation layer is formed. Therefore, the voltage applied to the gate insulating film is higher in the gate insulating film 4-2 of the protection element 16 where the inversion layer is not formed.

From the above, the accumulated positive charges are discharged through the gate insulating film 4-2 of the protection element 16, so that the gate insulating film 4-1 of the N-type MOS transistor 15 is discharged.
Degradation can be prevented. Next, a second specific example of the semiconductor device according to the present invention will be described. That is, in the second specific example of the semiconductor device 100 according to the present invention, the thickness of the gate insulating film 4-2 included in the protection element 16 is
The gate insulating film 4-1 included in the MOS transistor 15 is configured to be thinner than the film thickness.

That is, in the second embodiment of the present invention, the gate insulating film 21 of the protection element 25 is
This is to make it thinner than the gate insulating film 20 of the S transistor 15. That is, as described above, the thinner the gate insulating film, the easier the current to flow, so that more accumulated charges can be released to the substrate.

FIG. 11 is a plan view of a semiconductor device 100 according to the second embodiment of the present invention, and FIGS.
FIG. 4 shows a cross-sectional view thereof. That is, the planar configuration of the semiconductor device 100 according to this example is the same as that of the first example, and the protection element 25 having the dummy gate insulating film 21 formed on the N well 2 is formed in the N-type MOS transistor 15. Connect.

FIG. 12 is a sectional view taken along line AA of FIG. FIG. 13 is an N-type MO viewed from the line BB in FIG.
FIG. 4 is a sectional view of an S transistor 25. Further, FIG.
It is sectional drawing seen from CC line of the protection element 25. FIG.
As is apparent from the above, in the present specific example, the thickness of the gate insulating film 21 included in the protection element 25 is configured to be smaller than the thickness of the gate insulating film 20 included in the MOS transistor 15. Is what it is.

Next, a specific example of a method of manufacturing the semiconductor device 100 according to the second specific example of the present invention will be described with reference to FIGS. 15 to 22, the left side of each figure is a cross-sectional view of the N-type MOS transistor 15, and the right side is a cross-sectional view of the protection element 25, as in the first specific example. As shown in FIG. 15, at the same time as forming the element isolation region 3 on the P-type substrate 1, an N-type impurity is ion-implanted by using a resist 17 of a predetermined shape as a mask to form an N-well of the protection element 25. A well 2 is formed.

Next, as shown in FIG.
After the gate insulating film 20 is formed, a region of the protection element 25 is formed using the resist 51 having a predetermined shape as a mask. As shown in FIG. 17, the gate insulating film 20 in the protection element 25 is removed by wet etching of an oxide film.

Next, as shown in FIG.
Is removed, and a gate insulating film 21 is formed. At this time, the gate insulating film 21 is deposited on the gate insulating film 20 already formed in the MOS transistor 15 forming region. Therefore, the gate insulating film 21 of the protection element 25
Is thinner than the gate insulating film 20 of the N-type MOS transistor.

Thereafter, as shown in FIG. 19, the gate electrode 5 is formed in the region where the MOS transistor 15 is formed and the region where the protection element is formed. Next, as shown in FIG. 20, an N-type impurity is ion-implanted at a high concentration using a resist 18 having a predetermined shape as a mask to form an N-type diffusion layer 8 serving as a source and a drain of the N-type MOS transistor 15 and a protection element. An N-type diffusion layer 9 for obtaining a potential of 25 is formed.

Thereafter, after the resist 18 is peeled off, FIG.
As shown in FIG. 1, a P-type impurity is ion-implanted at a high concentration using a resist 19 having a predetermined shape as a mask, and a P-type diffusion layer 10 is formed on the P-type semiconductor substrate in contact with the N-type diffusion layer 9. If the N-type diffusion layer 9 and the P-type diffusion layer 10 each have a high concentration, a current easily flows due to a tunneling phenomenon, and thus it can be considered that they are conducting. That is, it can be considered that the N well 2 of the protection element 25 is electrically connected to the P-type substrate 1.

Therefore, the electric charge accumulated in the gate electrode 5 by the plasma process is discharged to the substrate mainly through this path by the current flowing through the gate insulating film 21 of the protection element 25. Finally, after an interlayer insulating film 24 is entirely formed, as shown in FIG. 22, an N-type diffusion layer 8 of the N-type MOS transistor 15 and a contact 6 reaching the gate electrode 5 are formed, and the first metal wiring 7 is formed. Form. As in the first embodiment, the first
It does not affect the layout of the metal wiring layer.

That is, in this embodiment, since the gate insulating film of the protection element portion is thinner than the gate insulating film of the NMOS transistor portion, current flows easily. That is, it is possible to more efficiently release the charge due to charging to the substrate. Next, a third specific example of the semiconductor device according to the present invention will be described. That is, a third specific example according to the present invention is directed to a semiconductor device in which a MOS transistor and a protection element arranged close to the MOS transistor are provided on a substrate, wherein the protection element is A substrate or a well in which a transistor is provided is provided in a substrate or a well having the same conductivity, and a high conductive region is formed in the protective element adjacent to a gate insulating film of the protective element. I have.

In this embodiment, the shortage of electrons for forming the inversion layer is eliminated and the extension of the depletion layer is suppressed. The feature is that an electric field stronger than that of the gate insulating film 4 is applied. The electric charge accumulated by the plasma process is discharged through the gate insulating film 27 of the protection element 26 using the difference in the electric field, thereby protecting the gate insulating film 4 of the N-type MOS transistor 15. .

Therefore, in this embodiment, it is not necessary to form an N-well below the gate electrode of the protection element 26 as compared with the first and second embodiments. FIG. 23 is a plan view showing the configuration of the semiconductor device 100 in this example, and FIG.
FIG. 3 is a sectional view taken along line BB of FIG. FIG. 25 corresponds to FIG.
FIG. 5 is a cross-sectional view taken along line CC of FIG.

FIGS. 26 to 30 show that the left side of FIG.
23 corresponds to the N-type MOS transistor 15, and the right side corresponds to the protection element 26 of the present invention in the section C of FIG.
That is, first, as shown in FIG. 26, the element isolation region 3 is formed on the P-type substrate 1. Next, as shown in FIG.
A common gate electrode 5 for the type MOS transistor 15 and the protection element 26 is formed.

Thereafter, as shown in FIG. 28, using a resist 18 of a predetermined shape as a mask, N-type impurities are ion-implanted at a high concentration to form an N-type diffusion layer 8 serving as a source and a drain of the N-type MOS transistor 15. With protection element 26
An N-type diffusion layer 9 for obtaining the potential of the above is formed. Further, as shown in FIG. 29, after the resist 18 is peeled off, a P-type impurity is ion-implanted at a high concentration using the resist 19 having a predetermined shape as a mask, and the P-type diffusion layer 10 is formed adjacent to the N-type diffusion layer 9. Form.

If the N-type diffusion layer 9 and the P-type diffusion layer 10 each have a high concentration, a current easily flows due to a tunneling phenomenon, so that it can be considered that they are conducting. Therefore, since electrons are supplied from the N-type diffusion layer 9, P
An inversion layer on the surface of the mold substrate 1 is formed. That is, since the depletion layer does not extend on the surface of the P-type substrate 1 of the protection element 26, the electric field is stronger in the gate insulating film 27 of the protection element 26 than in the gate insulating film 4 of the N-type MOS transistor 15.

The electric charge accumulated in the gate electrode 5 by the plasma process is discharged to the substrate through the gate insulating film 4-2 of the protection element 27. However, since it is necessary to supply electrons to the inversion layer on the surface of the P-type substrate 1, the N-type diffusion layer 9
Must be formed adjacent to the gate electrode 5.
Next, as shown in FIG. 30, after forming an interlayer insulating film 24 on the whole, the N-type diffusion layer 8 of the N-type MOS transistor 15 is formed.
Then, a contact 6 reaching the gate electrode 5 is formed, and a first metal wiring 7 is formed.

As in the first and second embodiments, the present embodiment does not affect the layout of the first metal wiring layer. As understood from the description of each of the above specific examples, the method for manufacturing the semiconductor device according to the present invention includes the steps of:
When manufacturing a semiconductor device provided with a MOS transistor and a protection element disposed in close proximity to the MOS transistor, the electric field strength applied to the gate insulating film included in the protection element includes an electric field intensity included in the MOS transistor. This is a method for manufacturing a semiconductor device configured to be stronger than the electric field intensity applied to a gate insulating film.

In the method of manufacturing a semiconductor device according to the present invention, the MOS transistor is formed on a P-type substrate or a P-type well, and the protection element is formed on an N-type well or an N-type substrate. Things are desirable. In the method of manufacturing a semiconductor device according to the present invention, the thickness of the gate insulating film included in the protection element is smaller than the thickness of the gate insulating film included in the MOS transistor. It is also desirable to form it.

Further, in the method of manufacturing a semiconductor device according to the present invention, the diffusion layer adjacent to the gate insulating film of the protection element is in contact with the diffusion layer of the same conductivity type as the semiconductor substrate. Another specific example of the method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device in which a MOS transistor and a protection element arranged close to the MOS transistor are provided on a substrate. The protection element is provided on a substrate or well having the same conductivity as the substrate or well on which the MOS transistor is provided, and the protection element has a high conductivity connected to a gate insulating film of the protection element. 6 is a method for manufacturing a semiconductor device for forming a region.

[0047]

As described above, the semiconductor device and the method of manufacturing the same according to the present invention employ the above-described technical configuration.
5 can be prevented from being deteriorated. The reason is,
This is because the charge charged on the gate electrode is discharged to the P-type substrate 1 through the gate insulating film 4-2 of the protection element 16 without flowing through the gate insulating film 4-1 of the N-type MOS transistor 15.

The second effect of the present invention is that the N-type M
In the OS transistor 15, the gate insulating film 4-1 can be protected even for positive accumulated charges in the gate electrode 5. The reason is that the positive accumulated charges are not discharged by the current due to the breakdown of the P / N junction, but are discharged by the current flowing through the gate insulating film.

The third effect of the present invention is that the layout of the first metal wiring layer is not affected.
The reason is that the protection element 16 shares the gate electrode 5 with the N-type MOS transistor 15 and does not require the first metal wiring 7.

[Brief description of the drawings]

FIG. 1 is a plan view illustrating a configuration of a specific example of a semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view of the specific example of the semiconductor device according to the present invention shown in FIG. 1 as seen from line AA.

FIG. 3 is a cross-sectional view taken along line BB of one specific example of the semiconductor device according to the present invention shown in FIG. 1;

FIG. 4 is a cross-sectional view of the specific example of the semiconductor device according to the present invention shown in FIG. 1 as seen from the line CC.

FIG. 5 is a cross-sectional view for explaining one step in a specific example of the method for manufacturing a semiconductor device according to the present invention.

FIG. 6 is a cross-sectional view for explaining one step in a specific example of the method for manufacturing a semiconductor device according to the present invention.

FIG. 7 is a cross-sectional view for explaining one step in a specific example of the method for manufacturing a semiconductor device according to the present invention.

FIG. 8 is a cross-sectional view for explaining one step in a specific example of the method for manufacturing a semiconductor device according to the present invention.

FIG. 9 is a cross-sectional view for explaining one step in a specific example of the method for manufacturing a semiconductor device according to the present invention.

FIG. 10 is a cross-sectional view for explaining one step in a specific example of the method for manufacturing a semiconductor device according to the present invention.

FIG. 11 is a plan view illustrating a configuration of another specific example of the semiconductor device according to the present invention.

FIG. 12 is a cross-sectional view of the specific example of the semiconductor device according to the present invention shown in FIG. 11, as viewed from line AA.

FIG. 13 is a cross-sectional view of the specific example of the semiconductor device according to the present invention shown in FIG. 11, as viewed from the line BB.

FIG. 14 is a cross-sectional view of the specific example of the semiconductor device according to the present invention shown in FIG. 11 as seen from line CC.

FIG. 15 is a cross-sectional view for explaining one step in another specific example of the method for manufacturing a semiconductor device according to the present invention.

FIG. 16 is a cross-sectional view for explaining one step in another specific example of the method for manufacturing a semiconductor device according to the present invention.

FIG. 17 is a cross-sectional view for explaining one step in another specific example of the method for manufacturing a semiconductor device according to the present invention.

FIG. 18 is a cross-sectional view for explaining one step in another specific example of the method for manufacturing a semiconductor device according to the present invention.

FIG. 19 is a cross-sectional view for explaining one step in another example of the method for manufacturing a semiconductor device according to the present invention.

FIG. 20 is a cross-sectional view for explaining one step in another example of the method for manufacturing a semiconductor device according to the present invention.

FIG. 21 is a cross-sectional view for explaining one step in another specific example of the method for manufacturing a semiconductor device according to the present invention.

FIG. 22 is a cross-sectional view for explaining one step in another specific example of the method for manufacturing a semiconductor device according to the present invention.

FIG. 23 is a plan view illustrating the configuration of another specific example of the semiconductor device according to the present invention.

FIG. 24 is a cross-sectional view of another specific example of the semiconductor device according to the present invention shown in FIG. 23, taken along line BB.

FIG. 25 is a sectional view of another specific example of the semiconductor device according to the present invention shown in FIG. 23, as seen from line CC.

FIG. 26 is a cross-sectional view for explaining one step in another specific example of the method for manufacturing a semiconductor device according to the present invention.

FIG. 27 is a cross-sectional view for explaining one step in another specific example of the method for manufacturing a semiconductor device according to the present invention.

FIG. 28 is a cross-sectional view for explaining one step in another specific example of the method for manufacturing a semiconductor device according to the present invention.

FIG. 29 is a cross-sectional view for explaining one step in another specific example of the method for manufacturing a semiconductor device according to the present invention.

FIG. 30 is a cross-sectional view for explaining one step in another specific example of the method for manufacturing a semiconductor device according to the present invention.

FIG. 31 is a plan view illustrating a configuration of a conventional semiconductor device.

FIG. 32 is a cross-sectional view of the conventional semiconductor device shown in FIG. 31 taken along line AA.

FIG. 33 is a cross-sectional view for explaining one step in the conventional method of manufacturing a semiconductor device.

FIG. 34 is a cross-sectional view for explaining one step in a conventional method of manufacturing a semiconductor device.

FIG. 35 is a cross-sectional view for explaining one step in the conventional method of manufacturing a semiconductor device.

FIG. 36 is a cross-sectional view for explaining one step in a conventional method of manufacturing a semiconductor device.

FIG. 37 is a cross-sectional view for explaining one step in the conventional method of manufacturing a semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... P type semiconductor substrate 2 ... N well 3 ... Element isolation film layer 4,4-1,4-2,20,21,27 ... Gate insulating film 5 ... Gate electrode 6 ... Contact 7 ... Metal wiring 8,9, DESCRIPTION OF SYMBOLS 31 ... N type diffusion layer 10 ... P type diffusion layer 15 ... MOS transistor 16, 26, 27 ... Protective element 24 ... Insulating interlayer film 30 ... Protective diode 7, 17, 18, 19, 51 ... Resist 100 ... Semiconductor device

Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/336 H01L 29/78 H01L 21/265 H01L 21/8234 H01L 27/088

Claims (10)

(57) [Claims] A MOS transistor and a protection element are provided on a substrate.
In a semiconductor device provided with
The transistor is formed on a P-type substrate or a P-type well.
And the protection element is an N-type well or N-type
Formed on the substrate and included in the protection element.
When charge is accumulated in the gate insulating film during the manufacturing process
In addition, the electric field strength applied to the insulating film depends on the MOS transistor.
The electric field strength applied to the gate insulating film contained in the
The protection element is
N-type well or N-type substrate in which
An N-type diffusion layer and a P-type
Providing a highly conductive region connected to the mold diffusion layer;
The protection element from the P-type substrate or P-type well.
It is configured so that electrons are supplied to the lower region of the rim
A semiconductor device characterized by the following. 2. The gate insulation included in the protection element.
The film thickness of the film included in the MOS transistor
It is configured to be thinner than the thickness of the heat insulating film.
The semiconductor device according to claim 1, wherein: 3. The MOS transistor and the protection element.
Means that the gate insulating film is shared
Item 3. The semiconductor device according to item 1 or 2. 4. A MOS transistor and said M transistor on a substrate.
A protection element placed close to the OS transistor is provided.
Semiconductor device, the MOS transistor
And the protection element share a gate insulating film.
During the manufacturing process, the gate insulating film included in the protection element is
Electric field strength applied to the insulating film when charge is accumulated
Is the gate insulation included in the MOS transistor
When it is configured to be stronger than the electric field strength applied to the film,
A highly conductive region is formed in the gate insulating film of the protection element.
Therefore, the gate voltage of the MOS transistor is
The charge stored in the gate insulating film is
That it is configured to discharge to the substrate through the edge film
Characteristic semiconductor device. 5. A MOS transistor and said M transistor on a substrate.
A protection element placed close to the OS transistor is provided.
In the semiconductor device, the MOS transistor
And the protection element share a gate insulating film.
The protection element includes the MOS transistor.
Substrate or well having the same conductivity as the substrate or well
And the protection element is provided in the
N-type diffusion layer connected to the gate insulating film of the protection element and P-type
A highly conductive region connected to the diffusion layer is formed, and
Therefore, from the substrate or well to the lower part of the insulating film of the protection element
It is characterized in that it is configured to supply electrons to the area
Semiconductor device. 6. A MOS transistor and said M transistor on a substrate.
A protection element placed close to the OS transistor is provided.
In manufacturing a semiconductor device that has been
The transistor and the protection element are connected to groups having different conductivity.
Formed on a plate or well, and
The gate insulating film included in the transistor and the protective element
The gate insulating film to be formed is integrally formed,
The electric field strength applied to the gate insulating film contained in the
The gate insulating film included in the MOS transistor
When charge is accumulated during the fabrication process, it
It is configured to be stronger than the electric field strength,
Highly conductive area for connecting the gate insulating film of the device to the substrate
Forming a semiconductor device. 7. The semiconductor device according to claim 6, wherein the MOS transistor is formed on a P-type substrate or a P-type well, and the protection element is formed on an N-type well or an N-type substrate. Production method. 8. The semiconductor device according to claim 6, wherein the thickness of the gate insulating film included in the protection element is smaller than the thickness of the gate insulating film included in the MOS transistor. 8. The method for manufacturing a semiconductor device according to item 7. 9. The device according to claim 6, further comprising an element portion in which a diffusion layer adjacent to the gate insulating film of the protection element is in contact with a diffusion layer of the same conductivity type as the semiconductor substrate. 13. The method for manufacturing a semiconductor device according to item 5. 10. A MOS transistor and a MOS transistor on a substrate.
The protection element arranged close to the MOS transistor
When manufacturing the provided semiconductor device, the protection element
The substrate on which the MOS transistor is provided or
Formed on a substrate or well with the same conductivity as the well
And insulation of the protection element from the substrate or well
In order to supply electrons to the lower region of the film, the protection element
An N-type diffusion layer and a P-type diffusion layer are connected to the gate insulating film.
It is characterized by connecting the highly conductive regions configured by
A method for manufacturing a semiconductor device.