JP3206960B2 - Extended central processing unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a central processing unit, and more particularly to an extended central processing unit having a register file memory in an integrated circuit device provided with a basic central processing unit.

[0002]

2. Description of the Related Art Generally, when a plurality of software processes (hereinafter, referred to as programs) are executed by a central processing unit (hereinafter, referred to as CPU), as shown in FIG.
A general-purpose register 1 provided in the U for storing data such as operation data and address pointers in each program unit
The data content of a differs for each program. Therefore,
When a plurality of programs are time-divisionally processed and processed using one CPU 1, when a program is switched from one program to another, first, the data currently stored in the general-purpose register 1a in the CPU is transferred to the CPU.
For example, the data is stored in a predetermined area of a RAM (read / write memory) 2 provided on a chip different from the chip 1 (hereinafter, such an operation is referred to as save), and then general-purpose data necessary for the next program is stored. In order to set the register state, necessary data is stored in the general-purpose register 1a from another area of the RAM 2 in which necessary data is stored (hereinafter, such an operation is referred to as return). Normally, the above evacuation and return operations are performed by the CPU.
RAM by software using the instructions provided in
2 and the CPU 1.

For example, when shifting from the program A to the program B, the data stored in the general-purpose register 1a in the program A of the CPU 1 is stored in the area 2a in the RAM 2 where the data corresponding to the program A is stored. Of the program B stored in the area 2b of the RAM 2 to the general-purpose register 1a. At this time, if the number of general-purpose registers 1a to be saved and restored is large in the architecture of the CPU 1, the time required for saving and restoring (hereinafter, referred to as register switching time) increases, and the program processing speed of the CPU 1 is reduced. descend. As a technique for reducing the register switching time, a register file method is known. The register file method means that the CPU itself does not have a general-purpose register, and the RAM is mounted on the same IC (integrated circuit) provided with the CPU.
(Hereinafter referred to as a register file RAM), and one or more sets of general-purpose registers (hereinafter referred to as register sets) of the CPU are allocated on the register file RAM. The register switching time can be increased by accessing the register file RAM on the same IC which can be accessed at a higher speed than when accessing an external memory (hereinafter referred to as external RAM) by an IC separate from the provided IC. This is a technique for reducing Incidentally, there are the following two methods in the register file system.

As shown in FIG. 15, a method 1 is a current bank which stores address pointer data as a pointer indicating a head position of a register set used in a current program in a CPU 3 as shown in FIG. A number register (hereinafter referred to as CBNR) 4 is provided.
On the basis of the stored value of NR4, a register number specified by an instruction in a program is added as an offset, the addition result data is output as an address, and the data of the register file RAM 5 indicated by the address is used as general-purpose register data. It is a method of accessing as equivalent to. Here, the CPU 3 performs data access,
As shown in FIG. 16, a data bus and an address bus common to the external RAM and the register file RAM 5 are used. In this method, the register set can be switched for a plurality of programs only by rewriting the contents of CBNR4, so that the program can be switched at high speed. However, each time the access to the register file RAM 5 is performed, it is necessary to output an address to the register file RAM 5 and read / write data.
There is a disadvantage that the processing speed per instruction is reduced. For example, the data stored in the R0 register and the data stored in the R1 register in the register file RAM 5 are added, and
In order to execute the addition instruction stored in the register, the table 1
As shown in the figure, six machine cycles are required. The machine cycle refers to each stage in the operation in the CPU.

[0005]

[Table 1]

As shown in FIG. 17, in the other system 2, a CBNR 4 is provided in the CPU 3 as in the system 1 as shown in FIG. 17, but unlike in the system 1, the CPU 3 stores the CBNR 4 in the register file RAM 5, the external RAM and the like. On the other hand, it has an independent access address, data bus and the like. As a result, it is possible to perform parallel processing, that is, so-called pipeline processing, of machine cycles such as storage of operation results. As shown in Table 2, the above-described addition instruction can be executed in five machine cycles.

[0007]

[Table 2]

Further, by adopting a dual-port RAM capable of simultaneously accessing two addresses as the form of the register file RAM 5, two read cycles corresponding to the machine cycles 2 and 3 shown in Table 2 can be achieved. Can be processed in parallel, and if a triple port RAM is employed, the write cycle of machine cycle 5 shown in Table 2 can be performed in parallel, and as a result, the instruction can be executed in one machine cycle. High-speed execution of instructions is realized as compared with the above method 1.

[0009]

However, in the method of the above method 2, it is necessary to provide a bus in the external RAM and the like and the register file RAM independently.
2 buses when dual port RAM is used
When a triple port RAM is used, the number of buses is increased to triple the number of buses. In addition, a dual-port or triple-port RAM requires a normal single-port RAM.
Since the number of circuits is larger and larger than that of the RAM of the port, there is a disadvantage that hardware is increased. SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and provides an extended CPU which has a register file configuration with a fast register switching time, suppresses an increase in hardware, and improves processing speed. The purpose is to do.

[0010]

According to the present invention, there is provided a basic CPU having a register set in the basic CPU, the basic CPU including at least one register, and an integrated circuit device having the basic CPU. A register file memory having an extended register set provided with a plurality of register sets having the same data amount as the stored data amount of the basic CPU register set.

With this configuration, the present extended CPU
Has the features of a conventional general-purpose register CPU and a register file CPU.

Further, the present invention provides a basic CPU including a register set in a basic CPU, the basic CPU including a register set in the basic CPU, and data stored in the register set in the basic CPU provided in an integrated circuit device including the basic CPU. A register file memory having an extended register set provided with a plurality of register sets having the same data amount,
When storing data in the basic CPU register set, the data is also written in the extension register set of the register file memory, and when reading data, the stored data of the basic CPU register set is read. When changing the register set constituting the extension register set, the extension register set in the register file memory can be stored without saving data from the register set in the basic CPU to the extension register set in the register file memory. And control means in the basic CPU for performing operation control so that only data is restored to the register set in the basic CPU.

With this configuration, both the register set and the register file memory in the basic CPU store the same data by the microprogram and the control means incorporated in the basic CPU. Therefore, when it is necessary to change all the stored data in the register set in the basic CPU, that is, when the bank needs to be changed, there is no need to save the stored data in the register set in the basic CPU, and new stored data is transferred from the register file memory. Only the operation of returning to the basic CPU register set needs to be performed. As described above, the register set in the basic CPU and the register file memory operate to shorten the program processing time in the extended CPU.

Further, it is used when the data is restored from one register set constituting the extension register set of the register file memory to the register set in the basic CPU provided in the basic CPU. An address data storage register for storing address pointer data indicating a head address of a register set for reading data; an internal connection dedicated bus for connecting the basic CPU to the register file memory; and an integrated circuit device provided with the basic CPU. An external connection-dedicated bus for connecting the basic CPU to the component elements provided externally, wherein the control means changes address pointer data of the address data storage register when changing a register set constituting the extension register set. Rewrite May be from the register set on the rewritten memory for the register file address pointer is data based on the specified to perform only the return operation of the data to the basic central processing unit in the register set.

With this configuration, the basic CPU
When data is stored in the registers in the register set within the basic CPU by the microprogram and the control means configured therein, the data is also written to a register file memory configured by, for example, a RAM.
When changing the so-called bank for changing the storage data of the register set in the basic CPU with the progress of the program, the address pointer data stored in the address data storage register is changed, and the register specified by the data is changed. The stored data is read from the area of the file memory and stored in the register set in the basic CPU. As described above, when storing data in the register set in the basic CPU, the same data is also written in the register file memory. There is no need to save the data stored in the set, and only the data needs to be restored. Therefore, the extended CPU can save the evacuation time, thereby improving the processing speed.

Further, the dedicated bus for internal connection and the dedicated bus for external connection make it possible to independently exchange information between the basic CPU and the register file memory and exchange information between the basic CPU and external components. In executing the operation, the operation is prevented from being interrupted by the fact that the basic CPU is accessing the other constituent elements, thereby improving the processing speed.

Further, as described above, the access between the basic CPU and the register file memory is data writing and reading, and these are not performed simultaneously. Therefore, the register file memory is a single port type memory. Things are enough. Therefore, being configurable with a single-port memory prevents an increase in the number of buses, and does not require a complicated circuit configuration as in the case of using a dual-port or triple-port memory. Acts to prevent.

Further, the present invention provides a basic CPU having a global / local register set having a register file memory and an accessible local register area, the register file memory and an inaccessible global register area, A register file memory provided in an integrated circuit device provided with a CPU and having an extended register set provided with a plurality of register sets having the same data amount as the stored data amount of the local register set; An address pointer indicating the start address of a register set from which data is read from the extended register set, which is used when data is restored from one register set constituting the extended register set of the memory to the local register set. An address data storage register for storing data, an internal connection dedicated bus for connecting the basic CPU and the register file memory, a component provided outside the integrated circuit device provided with the basic CPU, and the basic CPU. An external connection dedicated bus to be connected,
When performing an operation using the data stored in the global register area, reading and writing data to and from the global register area, and performing an operation using the data stored in the local register area, When writing data to the register file, the data is also written to the register set of the register file memory, and when reading data, the data stored in the local register area is read. When changing, the address pointer data of the address data storage register is rewritten. Data is transferred from the register set on the register file memory specified based on the rewritten address pointer data to the local register area. Performs operation control to perform the return operation only, characterized by comprising a control unit in the basic CPU.

Under the control of the control means in the basic CPU, when data is stored in one or a plurality of local register areas constituting a register set in the basic CPU,
For example, the data is also written in a register file memory constituted by a RAM. When changing all the stored data of the register set in the basic CPU according to the progress of the program, that is, when changing the so-called bank, the data stored in the address data storage register is changed and the register specified by the data is changed. The stored data is read from the register set on the file memory and stored in the local register area. As described above, when storing data in the local register area, the same data is also written in the register file memory.
When changing the data stored in the local register area, it is not necessary to save the data stored in the local register area, but only to restore the data. Therefore, the extended CPU can save the evacuation time, thereby improving the processing speed.

Further, the dedicated bus for internal connection and the dedicated bus for external connection make it possible to independently exchange information between the basic CPU and the register file memory and exchange information between the basic CPU and external components. When executing the operation, the operation is prevented from being interrupted by the fact that the basic CPU is accessing the other constituent elements, thereby improving the processing speed.

Further, as described above, the access between the basic CPU and the register file memory is data writing and reading, and these are not performed simultaneously. Therefore, the register file memory is a single port type memory. Things are enough. Therefore, being configurable with a single-port memory prevents an increase in the number of buses, and does not require a complicated circuit configuration as in the case of using a dual-port or triple-port memory. Acts to prevent.

In the above configuration, two types of register sets, a local register area and a global register area, are provided. However, one type of register set is used, and a register file memory is constituted by a RAM and a ROM. You may comprise. The present invention provides a basic CPU having a register set in the basic CPU, a first memory provided in the integrated circuit device having the basic CPU and capable of reading and writing the register set in the basic CPU and data, Store the common data and use the basic C
Second register dedicated to read operation for register set in PU
A register file memory having an extended register set having a plurality of register sets having the same data amount as the stored data amount of the basic CPU register set; and connecting the basic CPU and the register file memory. Internal connection dedicated bus and the basic CP
A dedicated bus for connecting the component elements provided outside the integrated circuit device provided with U and the basic CPU, and when storing data in the register set in the basic CPU, the data is also written in the first memory; On the other hand, when changing the register set that constitutes the register file memory, the data in the register file memory is not saved to the first memory of the register file memory from the register set in the basic CPU. And control means in the basic CPU for performing operation control so as to only restore data from the first and second memories to the register set in the basic CPU.

With this configuration, when all the stored data of the register set in the basic CPU are changed or the bank is changed, similar to the case where the register set in the basic CPU is divided as described above, Only the operation of restoring the data stored in the register file memory needs to be performed without saving the data stored in the register set, thereby improving the processing speed.

Further, the present invention provides a basic CPU provided with an aggregate register set having two register sets each having one or a plurality of registers, and an integrated circuit device provided with the basic CPU, and stores the aggregate register set. A register file memory having an extended register set having a plurality of register sets having the same data amount, a dedicated bus for separately connecting the two register sets of the set register set and the extended register set, When the same data as the data stored in each of the register sets of the collective register set is also written in the extension register set, and when all the stored data in each of the register sets of the collective register set are rewritten, the data is transmitted from the extension register set via the dedicated bus. To the register set above A switch provided on the dedicated bus for performing on / off operation of data transmission on the dedicated bus, a control unit for controlling operation in the basic CPU, and an integrated circuit device provided with the basic CPU so as to transfer data. An external dedicated bus for connecting another element provided outside and the basic CPU is provided.

With this configuration, when storing data in the two register sets constituting the collective register set, the control unit turns on a switch provided on the dedicated bus, and transfers the data to the two register sets. At the same time as storing, the same data as the data stored in the register set is also written to an extended register set of a register file memory constituted by a RAM, for example. or,
When changing all the data stored in the register set as the program proceeds, that is, when changing the so-called bank, the control means turns off the switch and sets the respective stored data from the extended register set of the register file memory. To the two register sets via dedicated buses. As described above, when data is stored in the register set, the same data is also written in the register file memory. Therefore, when changing the data stored in the register set, it is not necessary to save the data stored in the register set. And only the data needs to be restored. Further, since the register set and the extension register sets of the register file memory are connected by respective dedicated buses, data of the data from the register file memory to the two register sets forming the collective register set is transferred from the register file memory. The transfer can be done at once.
Therefore, the extended CPU can save the evacuation time, thereby improving the processing speed.

Further, the internal connection dedicated bus and the external connection dedicated bus enable information exchange between the basic CPU and the register file memory and information exchange between the basic CPU and the external components to be independently performed. In executing the operation, the operation is prevented from being interrupted due to the fact that the basic CPU is accessing the other constituent elements, thereby improving the processing speed.

Further, as described above, the access between the basic CPU and the register file memory is data writing and reading, and these are not performed at the same time. Therefore, the register file memory is a single port type memory. Things are enough. Therefore, being able to be configured with a single-port memory prevents an increase in the number of buses, and does not have a complicated circuit configuration unlike the case of using a dual-port or triple-port memory. Acts to prevent growth.

[0028]

【Example】

First Embodiment FIG. 1 shows the configuration of an extended CPU according to an embodiment of the present invention. The basic configuration is the same as that of the IC including the CPU shown in FIG. 17 described above, and the same components are denoted by the same reference numerals. The same IC has a basic CPU 7 and a register file RAM 5, a basic CPU 7, a register file RAM 5, and a basic CP.
U7 and the external RAM are connected by independent dedicated buses 8 and 9, respectively. The basic CPU 7 has one set of a general-purpose register set (hereinafter, simply referred to as a register set) 10 in the basic CPU, which is an aggregate of an arbitrary number of registers. The data of the set 10 is stored. Note that a plurality of the register sets are assigned to the register file RAM 5 as in the past, and in the following description, the register sets assigned to the register file RAM 5 are collectively called an extended register set. Further, the register set 10 includes a CBNR 4 for storing address pointer data Rp indicating the head address of the extension register set in the register file RAM 5 of the data group used by the program currently being executed. In this embodiment, the register set 10 includes 16 registers, R0 register to R15 register. The register set 10 is composed of triple-port registers, and can perform a read operation on any two registers and a write operation on one register simultaneously. An integrated circuit including the basic CPU 7 and the register file RAM 5 is hereinafter referred to as an integrated circuit.
Called the extended CPU 6.

In the processing of the basic CPU 7, the operation of reading data stored in the register set 10 is performed inside the basic CPU 7, and the operation of writing data to the register set 10 by executing an instruction is performed in the register set 1.
The write operation is performed for both the register 0 and an arbitrary address in the register file RAM 5 corresponding to the register. The above-described read and write operations are executed by a microprogram and a control unit provided in the basic CPU 7. Therefore, the data stored in the register set 10 always keeps consistency with the data on the address corresponding to each register of the register set 10 in the register file RAM 5. The RAM 5 for the register file is a single RAM for the reason described later.
Since the port RAM can perform enough functions,
A single-port RAM is used.

The pipeline operation of the extended CPU configured as described above will be described below. For example, FIG. 2 shows a machine cycle in a case where the stored data of R7 is added to the stored data of the R5 register and the added result data is stored in the R5 register as an example. Show. In FIG. 2, each section in the horizontal axis direction indicates one machine cycle. For example, in the case of the instruction 1, instruction fetch and decode are performed in the first machine cycle. In the second machine cycle, since the register set 10 in the basic CPU 7 is composed of a triple port, the R5 register and R
The read operation of the data stored in the register 7 and the addition operation of the read data are executed in the same machine cycle, and the addition result data is stored in the R5 register and the R5 in the register file RAM 5 in the third machine cycle.
It is stored at the address corresponding to the register. Thus, instruction 1 is executed in three machine cycles.

Instructions 2 to 4 are similarly executed in three machine cycles, but when the operation of the first machine cycle for instruction 1 is completed, the basic CP is executed.
The operation of the instruction reading portion of U7 ends, and the next instruction can be fetched. Therefore, in the second machine cycle, the instruction fetch and decode operations of the instruction 2 are executed. As described above, in the second machine cycle, the arithmetic operation of the instruction 1 and the instruction fetch and decode operations of the instruction 2 can be performed simultaneously.

Similarly, when the operation of the second machine cycle for the instruction 1 is completed, the operation of the basic CPU 7 is completed and the operation of the next instruction can be performed. The arithmetic operation in the instruction 2 is executed. Furthermore, a dedicated bus 9 connected to an external RAM or the like, a basic CPU 7 and a RAM for register files
5 and a special bus 8 for connecting
In the third machine cycle, the instruction 1
Of the operation result data into the register file RAM 5, the operation operation of the instruction 2, the fetch of the instruction from the outside in the instruction 3, and the decoding operation can be simultaneously executed. Apparently, one instruction can be executed in one machine cycle. Will be executed.

The access to the register file RAM 5 is only for storing the operation result data, that is, only writing to the predetermined address of the RAM 5 in one machine cycle. Does not require large RAM, single port RA
M is sufficient. Therefore, since there is no need to increase the number of buses or to provide a complicated circuit, it is possible to execute the pipeline processing at high speed as described above without increasing the hardware.

Next, a case where data stored in the register set 10 is rewritten will be described with reference to FIG.
FIG. 3 shows only relevant parts of the basic CPU 7 and the register file RAM 5 shown in FIG. Rewriting the data stored in the register set 10 is performed by the register file RAM 5 as described below.
Since the data stored in the extended register set is switched, the expression "switching the register file" may be used as the same expression as "rewriting the data stored in the register set 10". In addition, rewriting data of all the registers of the register set 10 may be expressed as switching banks (the same applies to the following embodiments). In addition, a bank is
Each of a plurality of register sets in the register file RAM 5 is referred to, and a bank number is set as one corresponding to the register set number. Switching of the register file is performed by rewriting data stored in CBNR4. As described above, when data is stored in each register of the register set 10,
At the same time, the same data is also written in the corresponding extension register set of the register file RAM 5, so that when switching the register file, there is no need to save the data stored in the general-purpose registers in the CPU as in the conventional case. Only the restoration of data from the extension register set of the RAM 5 to the register set 10 needs to be performed. Therefore, the register switching time requires a time for only the above-mentioned return. Therefore, the register switching time can be shortened and the arithmetic processing speed can be increased as compared with the related art.

The switching of the register file will be described specifically. In a conventional CPU employing the register file system, for example, 16 32-bit registers are provided as general-purpose registers in the CPU, and the data bus capacity for external access is small. In a conventional CPU of 16 bits and two machine cycles of one bus cycle, the switching required for saving and restoring in a register is performed by 16 [number of registers] × (32 [bit length register] ÷ 16
[Bit / bus width]) × 2 [machine cycle] × 2 [save / restore] = 128 [machine cycle]. In the above formula, the description in [] indicates a unit or a comment (the same applies to the following formula).

In the extended CPU 6 of the present invention, the basic CP
The configuration of the register set 10 in U7 is the same as that of the above-mentioned CPU, that is, all 16 registers, and the basic CPU 7 and the register file R
If the access bus between the AMs 5 is 32 bits and the register file RAM 5 can be accessed in one machine cycle, the register switching is 16 [number of registers] × (32 [bit length register] レ ジ ス タ 3
2 [bit bus width]) × 1 [machine cycle] × 1 [return only] = 16 [machine cycle], which is eight times faster than the conventional one.

As described above, in the extended CPU of this embodiment, the register set 1 provided in the basic CPU 7 is used.
0 is constituted by a triple port, and the basic CPU 7 and the register file RAM 5 are connected by the dedicated bus 8, so that the processing time, so-called machine cycle, can be reduced.
Only the operation of restoring data to the register set 10 in 7 need be performed, and the CPU operation time can be further reduced. Further, as described above, the external bus for accessing the external RAM and the like and the RAM access bus for the register file are independent and separated, so that high-speed data transfer is possible by parallel processing. Further, as described above, during the operation of restoring the register set, the access bus 9 for accessing the external RAM or the like of the basic CPU 7 is not used. Higher speed can be achieved.

As described above, the extended CP of this embodiment
U has a register as a register set in the basic CPU as well as a conventional general-purpose register type CPU, and also has a register file memory on the same chip as the CPU. Can be used as both types of CPU, and the versatility can be improved.

Second Embodiment: Second Embodiment of Extended CPU of the Present Invention
FIG. 4 shows a configuration in the embodiment of FIG. The basic configuration is the same as that of the IC including the CPU shown in FIG. 17 described above, and the same components are denoted by the same reference numerals.
The configuration of the register file RAM 5 is the same as that of the first embodiment described above in each of the embodiments described below, and the same reference numerals are given. The extended CPU 106 has a basic CPU 107 and a register file RAM 5, and the basic CPU 107 and the register file RAM 5, and the basic CPU 107 and an external RAM are connected by independent dedicated buses 108 and 109, respectively. The basic CPU 107 has one set of a global / local register set (hereinafter, simply referred to as a register set in the second embodiment) 110 which is an aggregate of an arbitrary number of registers. The set 110 includes a CBNR 4 for storing address pointer data indicating the start address of a local register set 110b, which will be described later, which is used in the currently executing program.

Register set 11 in basic CPU 107
0 is classified into two, a global register set 110a composed of one or a plurality of global registers and a local register set 110b composed of one or a plurality of local registers. For example, as shown in FIG.
The global register set 110a is composed of registers or Rm registers, and the local register set 110b is composed of (Rm + 1) to Rn registers. Each global register stores data such as operation data and pointers commonly used in a plurality of program processes, and each local register stores data such as data and pointers used for each program in a plurality of program processes. Data is stored. Note that register set 11
Numeral 0 is a triple-port register that can simultaneously perform a read operation on any two registers and a write operation on one register at the same time.

In the arithmetic processing of the basic CPU 107, the data stored in the register set 110, that is, the read operation of the data stored in the global register set 110a and the local register set 110b is read by the basic C.
The write operation of data to the register set 110 by the instruction execution is performed inside the PU 107, and the global register set 110a is performed only for the global register set 110a in the basic CPU 107.
When the write operation is performed on the local register set 110b, the local register set 110b in the basic CPU 107 and the local register set 110b
The write operation is performed for both of the extension register sets at an arbitrary address in the register file RAM 5 corresponding to the above. Note that the above read and write operations are performed in the basic C
It is provided in the PU 107 and is controlled by a microprogram and a control unit that control ordinary instruction processing. Therefore, the data of the local register set 110b always keeps consistency with the stored data of the extension register set on the address corresponding to the local register set 110b in the register file RAM 5.

The reason why the register set 110 is divided into two as described above is that, for data common to each program, writing to the register file RAM 5 and reading from the register file RAM 5 are duplicated and unnecessary. In this embodiment, the register set 110 is divided into halves, and access to the register file RAM 5 is made only by the local register set 110b that stores different data in each execution program. This is to reduce the time. The register file RAM 5 is a single-port RAM because a single-port RAM can sufficiently function for the reason described later.

The pipeline operation of the extended CPU configured as described above will be described below. For example, an instruction to add the data stored in the local register R7 to the data stored in the local register R5 register and store the addition result data in the local register R5 register will be referred to as instructions 1 to 4. FIG. 2 shows a machine cycle when the process is repeatedly executed.

In FIG. 2, each section in the horizontal axis direction represents one machine cycle.
In the first machine cycle, instruction fetch and decode are performed. In the second machine cycle, the basic CPU 1
Since the register set 110 in the register 07 is composed of triple ports, the read operation of the data stored in the R5 register and the R7 register and the addition operation of the read data are executed in the same machine cycle, and the third machine cycle is executed. The result of addition is stored at the address corresponding to the R5 register and the R5 register in the register file RAM 5. Thus, instruction 1 is executed in three machine cycles.

Instructions 2 to 4 are similarly executed in three machine cycles, but when the operation of the first machine cycle for instruction 1 is completed, the basic CP is executed.
The operation of the instruction reading portion of U107 is completed, and the next instruction can be fetched. Therefore, in the second machine cycle, the instruction fetch and decode operations of the instruction 2 are executed.
As described above, in the second machine cycle, the arithmetic operation of the instruction 1 and the instruction fetch and decode operations of the instruction 2 can be performed simultaneously.

Similarly, when the operation in the second machine cycle for the instruction 1 is completed, the operation of the basic CPU 107 is completed, and the operation for the next instruction is possible. Therefore, in the third machine cycle, The arithmetic operation in the instruction 2 is executed. Furthermore, a dedicated bus 109 for connecting an external RAM and the like and a dedicated bus 108 for connecting the basic CPU 107 and the register file RAM 5 are provided, and the register set 110 in the basic CPU 107 is a triple port type. In the third machine cycle, the operation result data of the instruction 1 can be written into the register file RAM 5, the operation operation of the instruction 2, the fetch of an external instruction in the instruction 3, and the decoding operation can be simultaneously executed. , One instruction is executed in one machine cycle.

The access to the register file RAM 5 is only for storing the operation result data, that is, only writing to a predetermined address of the RAM 5 in one machine cycle. Single port RAM without large RAM
Is enough. Therefore, since there is no need to increase the number of buses or to provide a complicated circuit, it is possible to execute the pipeline processing at high speed as described above without increasing the hardware.

As an example of the next operation, the data stored in the R0 register included in the global register set 110a is added to the data stored in the R7 register included in the local register set 110b, and the addition result data is stored in the R0 register of the global register set 110a. Consider the case of storing. FIG. 5 shows a machine cycle in this case. In this example, each instruction is executed in three machine cycles in the same manner as in the above-described example. However, the difference from the above-described example is that the addition result data is stored in the global register. There is no access to RAM5. Since a triple port type is adopted as the register set 110, this extended CPU
In the machine cycle, the storage of the operation result data in the R0 register in the instruction 1, the operation in the instruction 2, and the fetch and decode of the instruction in the instruction 3 can be performed simultaneously. For example, in the third machine cycle, the instructions 1 to 3 can be executed simultaneously, and apparently one instruction is one
It is executed in a machine cycle.

Next, switching of the register file will be described with reference to FIG. FIG. 6 shows only the relevant parts of the basic CPU 107 and the register file RAM 5 shown in FIG. Switching of the register file is performed by rewriting data stored in CBNR4. As described above, when data is stored in each register of the local register set 110b, the same data is also written to the extension register set of the register file RAM 5 at the same time. As described above, there is no need to save the data stored in the general-purpose registers in the CPU, and only the data needs to be restored from the extension register set of the register file RAM 5 to the local register set 110b. Therefore, the register switching time requires a time for only the above-mentioned return. Therefore, the register switching time can be reduced as compared with the conventional case, and the calculation processing speed can be increased. The data stored in the global register set 110a is read and written in the basic CPU 107 as described above, and thus has no relation to the switching operation of the register file.

The switching of the register file will be specifically described. A conventional CPU employing the register file system has, for example, 16 32-bit registers as general-purpose registers in the CPU, and has a data bus capacity for external access. In a conventional CPU of 16 bits and two machine cycles of one bus cycle, the switching required for saving and restoring in the register is performed by 16 [number of registers] × (32 [bit length register] ÷ 16
[Bit / bus width]) × 2 [machine cycle] × 2 [save / restore] = 128 [machine cycle]. In the above formula, the description in [] indicates a unit or a comment (the same applies to the following formula).

In the basic CPU 107 of this embodiment, the configuration of the register set 110 in the basic CPU 107 is the same as that of the above-mentioned CPU, that is, all 16 registers, of which eight global registers and eight local registers are provided.
If the access bus between the register 107 and the register file RAM 5 is 32 bits and the register file RAM 5 can be accessed in one machine cycle, the register set 110 is switched by 8 [number of local registers] × (32 [bit length] Register] $ 32 [bit bus width]) x 1 [machine cycle] x 1
[Return only] = 8 [machine cycle], which is 16 times faster than in the past.

As described above, in the extended CPU according to the present embodiment, the register set 110 provided in the basic CPU 107 is constituted by a triple port.
And the RAM 5 for the register file are connected by the dedicated bus 108, so that the operation processing time, that is, the so-called machine cycle, can be shortened. In addition, the CPU operation time can be further reduced. Further, in the present embodiment, the register set 110 is divided into halves,
5 is accessed only by the local register 110b, so that the register switching time is further reduced. Further, as described above, the external bus for accessing the external RAM and the like and the RAM access bus for the register file are independent and separated, so that high-speed data transfer is possible by parallel processing. Further, as described above, during the return operation of the local register, the external RAM of the basic CPU 107
Since the access bus 109 is not used, operations such as fetching the next instruction can be performed, and the processing speed of the CPU can be increased.

Third Embodiment FIG. 7 shows the configuration of the CPU in this embodiment. The same components as those in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted. In this embodiment,
The register set 111 in the basic CPU provided in the basic CPU 112 (hereinafter, simply referred to as a register set in the third embodiment) 111 is divided into two areas, global and local, as in the second embodiment. CBNR4 is provided in the register set 111. A register file memory 115 connected to the basic CPU 112 via the bus 108 includes a register file RAM 115a composed of a RAM,
And a register file ROM 115b composed of M (read only memory).

As for the mapping of the addresses in the register file memory 115, as shown in FIG. 8, one or a plurality of registers are allocated to a continuous address area of the ROM and the RAM for one set of registers 111. . That is, as shown in FIG. 8, the addresses (Rp + 0) to (Rp + m) of the register file memory 115 are stored in the register file ROM 115b and the addresses (Rp + m + 1) to (Rp + n) are stored in the register file memory 115 for the value Rp stored in the CBNR4. Assigned to the file RAM 115a. The register file RAM 115a,
The register file ROM 115b corresponds to each register set in the register file RAM 5 described above. Also, RAM 115 for register file
a, a plurality of register file ROMs 115b may be provided.

As in the second embodiment described above, the register set 111 in the basic CPU 112 is composed of triple-port registers, and a read operation of any two registers is performed by executing a write operation of one register. The register file ROM 115b and the register file RAM 115a are of a single port type for the same reason as described in the second embodiment.

Further, in the processing of the basic CPU 112, (Rm +
1) through Rn register read operation is performed by the basic CPU 1
12 while the above (Rm
+1) to Rn registers, the data write operation is performed using the above (Rm + 1) to Rn registers and (Rm +
The write operation is performed for both 1) to an arbitrary address in the register file RAM 115a corresponding to the Rn register. Therefore, the data stored in the (Rm + 1) to Rn registers is the RA for the register file.
It always maintains consistency with the data on the corresponding address in M115a.

The read operation of the R0 to Rm registers corresponding to the register file ROM 115b is performed by the basic CPU.
R0 to Rm by instruction execution
In the data write operation of the register, the write operation is performed only on the R0 to Rm registers. Therefore, the data stored in the R0 to Rm registers may be different from the data on the corresponding address in the register file ROM 115b when a write operation occurs.

The extended CP of this embodiment configured as described above
The pipeline operation of U will be described below. As an example, a command to add the data stored in the R0 register corresponding to the address in the register file ROM 115b to the data stored in the R7 register corresponding to the address in the register file RAM 115a, and store the addition result data in the R7 register. Think. Instructions 1 to 4
FIG. 9 shows a machine cycle when these instructions are repeated four times. The description of the operation is the same as that of FIG. 2 in the above-described second embodiment, and will be briefly described. However, the extended CPU of this embodiment also has the basic CP as described above.
The U112 and the register file memory 115 are connected by the dedicated bus 108, the basic CPU 112 and the external RAM are connected by the bus 109, and the register set 111 in the basic CPU adopts a triple port type. As in the second embodiment, each instruction is executed in three machine cycles.
In the machine cycle, the addition result data is written to both the R7 register and the corresponding address portion in the register file RAM 115a. Therefore, in the extended CPU of this embodiment, one instruction is apparently executed in one machine cycle as shown in, for example, the third machine cycle in FIG.

As in the case of the second embodiment, a single port RAM is sufficient for the register file RAM 115a, and the same data as the register state of the basic CPU 112 is always stored in the register file RAM 115a. Since it is not necessary to save the data stored in the register set 111 at the time of bank switching and only the restoration is required, the register switching time is only the register switching time for the above-mentioned restoration, and high-speed operation is possible. In the extended CPU according to the present embodiment, constant data used in each program processing is held in the register file ROM 115b.
By simply changing the storage data Rp of NR4, the ROM 1
The constant data can be read out from the register 15b, and only the restoration process needs to be performed at the time of register switching. In particular, the CP corresponding to the register file ROM 115b
Since the data stored in the R0 to Rm registers in U is not saved in the register file ROM 115b even when the registers are switched, it is useless to set data that does not need to be saved in each program processing. Data saving can be omitted.

In the present embodiment, the data stored in the R0 to Rm registers has changed in accordance with the execution of the program, as compared with the case where the constant data is stored in the global register 110a as described in the second embodiment. Even in this case, by restoring the data from the register file ROM 115b, it is possible to easily reset the data to the original stored data, and it is not necessary to consider the change of the constant data in the program creation. This has the advantage that the degree of freedom is improved.

In the same example as described in the second embodiment, if the operation speed of the extended CPU of this embodiment is represented by the number of machine cycles, the second embodiment returns from the register file memory. Although the number of registers is eight for the local registers, the extended CPU of this embodiment uses a register file ROM and a register file RAM.
, The number of registers to be restored is 16. Therefore, the extended CPU of this embodiment
The number of machine cycles related to the operation of (1) is increased by 8 machine cycles as compared with the second embodiment, resulting in a total of 16 machine cycles. It is.

Fourth Embodiment As shown in FIG. 10, this embodiment is a modification of the third embodiment in which a part of the components is changed, and has the same configuration as the configuration shown in FIG. The same reference numerals are given to the portions, and the description thereof will be omitted. In the extended CPU 116 according to the present embodiment, the register file RAM 115a used in the program currently being executed.
CBNR4, which stores the address pointer data Rp 'indicating the start address of the register set of the register file ROM 115b, in addition to the CBNR4 storing the address pointer data Rp indicating the start address of the register set of FIG.
NR113 is provided. Note that CBNR4 and 113
The register set 11 is the same as in the above embodiments.
4 can be included.

As the mapping of the address of the register file memory 115, as shown in FIG.
The address area of (Rp '+ 0) to (Rp' + m) based on the data Rp 'stored in R113 is defined as the register file ROM 115b, and the R0 to Rm registers in the basic CPU 112 are assigned to this area, and the stored data Rp' (Rp + 0) to (Rp + (n-
m)) to the register file RAM 115
and (Rm + 1) in the basic CPU 112 in this area.
Or assign the Rn register. The other configuration is the same as that of the third embodiment, and the description is omitted.

The extended CP of this embodiment configured as described above
The operation at U is basically the same as that of the extended CP of the third embodiment.
Same as U, and has the effect of shortening the switching time of the register file memory and shortening the operation time by omitting useless saving of data by writing data common to each program to the register file ROM 115b. Is the same, and the description is omitted.

In particular, the extended CPU of this embodiment has the following effects. That is, the extension C of the third embodiment
In the PU, since the basic CPU 112 does not have one CBNR 4 for specifying the address of the register file memory, the register file memory always includes a pair of the register file ROM and the register file RAM. One or a plurality of these are provided.
Therefore, for example, even when a plurality of programs have the same data stored in the register file ROM 115b, a plurality of ROMs 115b are provided. On the other hand, in the extended CPU 116 of the present embodiment, the register file RAM
CBNR4 for storing pointer data specifying the address of the address 115a, and CBNR for storing pointer data specifying the address of the ROM 115b for the register file.
113, the common data common to each program is stored in one register file ROM 115b in the above case, and when the program changes and the common data is required, the pointer data of the CBNR 113 is stored. By specifying the address of the ROM 115b, the common data can be returned to the register set in the basic CPU 112.

As described above, the register file memory 1
15, the register file ROM 115b
And a memory capacity required for the register file RAM 1 can be reduced.
15a and the register file ROM 115b can be more freely mapped.

As described above, the extended CPU in each embodiment has a register as a register set in the CPU similarly to the conventional general-purpose register type CPU, and has a register file memory on the same chip as the CPU. Also, it can be used as a general-purpose register type or register file type CPU, and the versatility can be improved.

Fifth Embodiment FIG. 12 shows an example of the configuration of the fifth embodiment. The basic configuration is the same as that of the IC including the CPU shown in FIG. 17 described above, and the same components are denoted by the same reference numerals. In the extended CPU of this embodiment, the basic CPU 207 is included in the extended CPU 206.
And a RAM 5 for a register file.
07, register file RAM 5, and basic CPU 2
07 and an external RAM are connected by independent dedicated buses. That is, the basic CPU 207 and the register file RAM 5 are connected by a control bus 211, an address bus 212, and data buses 213a and 213b, and an external component (not shown) provided separately from the extension CPU 206 and the basic CPU 207 They are connected by a bus 221, an address bus 222, and a data bus 223.

In the basic CPU 207, for example, 16
There are provided a set register set 241 composed of book registers, the CBNR 4, an execution unit 242 for executing an operation, and a control unit 243 for controlling operations of components in the basic CPU 207. The collective register set 241 is divided into two register sets 241a and 241b by eight registers. The data bus 213a connected to the register file RAM 5 is
The execution unit 242 and the register set 241a are directly connected, while the data bus 213b is connected to the register set 2
In addition to being directly connected to 41b, it is also connected to the register set 241a and the data bus 213a via a switch 245 that performs an on / off operation by a control signal sent from the control unit 243.

When data is stored in the register sets 241a and 241b from the execution unit 242, the switch 245 is turned on by a control signal sent from the control unit 243. Therefore, the execution unit 242 is connected to the register set 241a and the register file RAM 5 via the data bus 213a, and is connected to the register file RAM 5 via the data buses 213a and 213b and the switch 245. on the other hand,
When it is necessary to rewrite the data stored in the collective register set 241 due to the progress of the program being executed by the basic CPU 207, the switch 245 is turned off by a control signal sent from the control unit 243, and the register file RAM 5 stores the register set 241a and the register set 241a. 241b.

The execution unit 242 and the register sets 241a and 241b are connected to buses 246 and 24, respectively.
7, and the control unit 243 sends control signals to the CBNR 4, the set register set 241, and the execution unit 242, respectively. The register file RAM 5 stores a single-port RA for the reason described later.
Since M can perform a sufficient function, a single-port RAM is employed. Also, each of the buses 213 described above
a, 213b, 246, 247, register set 241
The bus widths of a and 241b are each 32 bits.

The operation of the thus-configured extended CPU will be described below. In the processing of the basic CPU 207, the operation of reading data stored in the set register set 241 is performed within the bus
6, 247, and the data write operation to the collective register set 241 by executing the instruction is performed by the control unit 2
By turning on the switch 245 by the control signal transmitted by the switch 43, the register set 241a is set via the data bus 213a, the register set 241b is set via the switch 245, and the data buses 213a and 213b are set. R for register file via
The processing is performed on the extension register set of the address portion corresponding to each of the register sets 241a and 241b in the AM5. Therefore, the data stored in the collective register set 241 always keeps consistency with the data of the extension register set on the corresponding address of the collective register set 241 in the register file RAM 5. Note that the above read and write operations are performed in the basic C
It is controlled by a control signal sent from the control unit 243 in the PU 207.

Next, a case where the data stored in the set register set 241 is switched will be described. To switch the data stored in the set register set 241, CBNR
4 is rewritten. As described above, when data is stored in each register set of the collective register set 241, the same data is also written in the extension register set of the register file RAM 5 at the same time, so that the storage of the collective register set 241 is performed. When switching data, it is not necessary to save the data stored in the general-purpose registers in the CPU as in the related art, and only the data needs to be restored from the extended register set of the register file RAM 5 to the set register set 241.

When the above-mentioned return is performed, the switch 245 is turned off by a control signal sent from the control unit 243, so that the data buses 213a and 213b become independent, and the data read from the register file RAM 5 Is transferred to the register set 241a via the data bus 213a and to the register set 241b via the data bus 213b. That is, since the data buses 213a and 213b are each configured with a 32-bit width as described above, 64-bit data is transferred from the register file RAM 5 to the collective register set 241.
To the register set 241 in this embodiment.
Since the number of registers constituting a and 241b is eight, the transfer is completed in eight cycles.

The clock rates of the data buses 213a and 213b are adjusted by the data bus 223 connected to the external components.
Assuming that the data bus 223 has a bit width of 16 bits at twice the clock rate of the data bus 223, data stored in a total of 16 32-bit registers constituting the collective register set 241 is transferred via the data bus 223. The number of cycles at the time of transfer from the external component, for example, a RAM or the like, is 64 as shown in the following equation. 16 (number of registers) × 32 (bit width of register) ÷ 1
6 (bus width) × 2 (clock rate) = 61 cycles Note that the description in parentheses indicates a numerical annotation. In addition, actually,
The external RA of the data stored in the set register set 241
Since the save time to the M is also required, switching of the data stored in the register by accessing the external RAM requires one step.
It requires 28 (= 64 × 2) cycles.

On the other hand, in the extended CPU 206 according to the present embodiment, the number of cycles is eight as shown in the following equation. 16 (number of registers) × 32 (bit width of register) ÷ 6
4 (bus width) = 8 cycles Note that the description in parentheses indicates a numerical annotation. As described above, according to the extended CPU 206, the stored data of the collective register set can be switched 16 times faster than the conventional CPU, and the arithmetic processing speed can be increased.

Next, the pipeline operation of the extended CPU 206 will be described below. In addition, set register set 2
41 is configured as a triple port type. For example, an instruction to add the data stored in the R1 register to the data stored in the R0 register in the R0 to R15 registers included in the set register set 241, and store the addition result data in the R5 register is referred to as an instruction 1. FIG. 13 shows a machine cycle when the process is repeatedly executed four times from No. 4 to No. 4.

In FIG. 13, each section in the horizontal axis direction indicates one machine cycle. For example, in the case of instruction 1, instruction fetch and decode are performed in the first machine cycle. In the second machine cycle, the basic CP
Since the set register set 241 in the U207 is configured by a triple port, the R0 register and the R1
The read operation of the data stored in the register and the addition operation of the read data are executed in the same machine cycle,
At the third machine cycle, the addition result data is R0
It is stored at an address corresponding to the R0 register in the register and register file RAM 5. Thus, instruction 1 is executed in three machine cycles.

Instructions 2 to 4 are similarly executed in three machine cycles. When the operation of the first machine cycle for instruction 1 is completed, the basic CP is executed.
The operation of the instruction reading portion of U207 ends, and the next instruction can be fetched. Therefore, in the second machine cycle, the instruction fetch and decode operations of the instruction 2 are executed.
As described above, in the second machine cycle, the arithmetic operation of the instruction 1 and the instruction fetch and decode operations of the instruction 2 can be performed simultaneously.

Similarly, when the operation of the second machine cycle for instruction 1 is completed, the operation of the basic CPU 207 is completed, and the operation of the next instruction is possible, so that in the third machine cycle, The arithmetic operation in the instruction 2 is executed. Further, dedicated buses 221, 222, 223 for connecting to an external RAM or the like, and a basic CPU 20.
7 and the register file RAM 5, dedicated buses 211, 212, 213 a, and 213 b are provided, and the set register set 241 in the basic CPU 207 adopts a triple port type. The operation result data of the instruction 1 can be simultaneously written into the register file RAM 5, the operation operation of the instruction 2, the fetch and decode operation of the instruction from the outside in the instruction 3 can be simultaneously executed, and apparently one instruction is one machine cycle. Will be executed.

Access to the register file RAM 5 is only for storing the operation result data, that is, only writing to a predetermined address of the RAM 5 in one machine cycle. A large RAM is not required, and a single port RAM is sufficient. Therefore, since there is no need to increase the number of buses or to provide a complicated circuit, it is possible to execute the pipeline processing at high speed as described above without increasing the hardware.

As described above, in the extended CPU 206 in this embodiment, the set register set 241 is divided into two sets, and the respective register sets 241a and 241b
And the register file RAM 5 are connected to a dedicated bus 213a,
213b, the CPU operation time can be shortened because only the operation of restoring data to the set register set 241 in the basic CPU 207 should be performed when the register file is switched. Further, as described above, the external bus for accessing the external RAM and the like and the RAM access bus for the register file are independent and separated, so that high-speed data transfer is possible by parallel processing. further,
As described above, during the register return operation, the basic CPU
207, access buses 221 and 22 for access to an external RAM, etc.
2 and 223 are unused, so that operations such as fetching the next instruction can be performed, and the processing speed of the CPU can be increased.

A register set is provided in the basic CPU as shown in each of the above-described embodiments, and the basic CP
In the extended CPU in which a register file RAM is provided on the same IC as U, and the basic CPU and the register file RAM are connected by a dedicated bus, the basic CPU
And the RAM for register file are connected by a dedicated bus, so that the RA for register file is stored in the extended CPU.
Whether or not to provide M can be freely selected.

That is, a CPU employing the conventional register file system and a CPU employing no register file system
Operation is fundamentally different from
PUs were used for different purposes.
In this case, either method can be selected. As described above, since a program for performing frequent process switching is executed, when selecting a CPU that needs to perform the switching at high speed, registering on the same IC R for file
When the AM is provided and the hardware scale is to be made smaller than the arithmetic processing speed, the RAM for the register file need not be provided.

RAM for register file in extended CPU
When the CPU is not provided, the operation of the extended CPU is the same as that of the conventional general-purpose register system CPU, and the switching of the data stored in the register set is performed by accessing an external RAM provided outside the extended CPU.

As described above, according to the extended CPU of this embodiment, an appropriate CPU according to the method of use can be obtained only by selecting whether or not the register file RAM is provided in the extended CPU. Therefore, it is not necessary for the semiconductor maker to design a CPU used for an IC for a specific application from the beginning for each specific IC, and the above-mentioned extended CPU is a CPU used for an IC for a specific application.
Very suitable as. Conventionally, the user has selected and used a CPU having a specification similar to the desired specification from the existing CPUs. However, according to the extended CPU of the present invention, the user can determine not only whether or not the register file is used but also the register file. There is also an advantage that the memory size configuration of the file memory can be freely selected and a CPU having desired specifications can be obtained.

As described above, the register file RAM may not be provided in the extended CPU. However, the register file RAM is provided in the extended CPU, and the control bus 211 shown in FIG. Each of the bus 212, the data bus 213a, and the data bus 213b is provided with a switch for connecting and disconnecting the CPU and the register file RAM, and the on / off operation of the switch is performed by a control signal transmitted from the control unit 243. Alternatively, a conventional general-purpose register type CPU and a register file type CPU may be selectively used.

In each of the above embodiments, it is assumed that the number of register sets is one. However, the number of register sets is not limited to this, and a plurality of sets may be provided.

[0089]

As described in detail above, the extended CPU of the present invention
According to the method, the same data as the data stored in the register set in the basic CPU is always held in the register file memory by copying. There is no need to save, and only the return operation needs to be performed, and data switching of the register set in the basic CPU can be performed at high speed. According to the extended CPU of the present invention, the register set in the basic CPU is a dual port or triple port, and the register file memory is a single port, so that the conventional dual port or triple port register / register is used. The hardware for the file memory can be reduced without reducing the processing speed of the CPU.

Further, according to the extended CPU of the present invention, the global local register set is provided in the basic CPU, and the same data as the data stored in the local register set is always retained in the register file memory by copying. By doing so, it is not necessary to save the data stored in the local register set at the time of data switching of the local register set, it is only necessary to perform a return operation, and the data of the register set can be switched at high speed.

In the extended CPU of the present invention, the basic CPU
The register set can be switched only by restoring the data to the local register set, instead of saving and restoring the data stored in all the registers within the register, so that the register set can be switched more quickly.

According to the extended CPU of the present invention, the basic C
By setting the local register set and global register set in the PU as dual ports or triple ports and the register file memory as a single port, the conventional dual port or triple port register file memory can be used. , CPU
Hardware can be reduced without lowering the processing speed of.

According to the extended CPU of the present invention, since the register file memory includes the first memory and the second memory, for example, constant data commonly used in each program processing is stored in the second memory. By doing so, it is not necessary to save the constant data even when rewriting the data stored in the register set in the basic CPU, so that unnecessary data saving can be omitted, and the data stored in the register set in the basic CPU can be omitted. Can be switched at high speed. Further, since the respective registers constituting the register set in the basic CPU and the memory area in the register file memory are connected by a dedicated bus, the return operation can be performed on each of the registers at the same time. Can be performed at high speed.

Further, according to the extended CPU of the present invention, the basic CPU is provided with a collective register set having two register sets, and the basic CPU and the register file memory are used for double-size register files for external access. By connecting via a dedicated bus for memory access, the data transfer speed at the time of recovery is doubled, and it is possible to select whether or not to provide a memory for register files in the extended CPU. Of the CPU used for the IC can be easily designed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of one embodiment of an extended CPU of the present invention.

FIG. 2 is a diagram for explaining an operation of the extended CPU shown in FIG.

FIG. 3 is a diagram for explaining an operation of the extended CPU shown in FIG. 1;

FIG. 4 is a block diagram showing a configuration of a second embodiment in the extended CPU of the present invention.

FIG. 5 is a diagram for explaining the operation of the extended CPU shown in FIG.

FIG. 6 is a diagram for explaining an operation of the extended CPU shown in FIG. 4;

FIG. 7 is a block diagram showing a configuration of a third embodiment in the extended CPU of the present invention.

FIG. 8 is a diagram for explaining the operation of the extended CPU shown in FIG. 7;

FIG. 9 is a diagram for explaining an operation of the extended CPU shown in FIG. 7;

FIG. 10 is a block diagram showing a configuration of a fourth embodiment in the extended CPU of the present invention.

11 is a diagram for explaining the operation of the extended CPU shown in FIG.

FIG. 12 is a block diagram showing a configuration of a fifth embodiment in the extended CPU of the present invention.

FIG. 13 is a diagram for explaining the operation of the extended CPU shown in FIG.

FIGS. 14A and 14B are diagrams for explaining operations in a conventional general-purpose register type CPU.

FIG. 15 is a diagram for explaining an operation in a conventional register file type CPU.

FIG. 16 is a block diagram showing an example of a configuration of a conventional register file type CPU.

FIG. 17 is a block diagram showing another example of the configuration of a conventional register file type CPU.

[Explanation of symbols]

4 CBNR, 5 RAM for register file, 7
... Basic CPU, 8, 9 ... Bus, 10 ... Register set, 107 ... Basic CPU, 108,109 ... Bus,
110a: Global register, 110b: Local register, 113: CBNR, 115a: RAM for register file, 115b: ROM for register file,
206 ... Extended CPU, 207 ... Basic CPU, 211 ...
Control bus, 212 ... address bus, 213a
... data bus, 213b ... data bus, 221 ... control bus, 222 ... address bus, 223 ... data bus, 241 ... register set, 242 ... execution unit, 243 ... control unit, 245 ... switch, 24
6,247 ... Bus.

Continued on the front page (31) Priority claim number Japanese Patent Application No. 4-10080 (32) Priority date January 23, 1992 (199.2.1.23) (33) Priority claim country Japan (JP) (72) Inventor Takashi Yasui Ricoh Co., Ltd. 1-3-6 Nakamagome, Ota-ku, Tokyo (56) References JP-A-58-225443 (JP, A) JP-A-57-212551 (JP, A) 61-75444 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 9/30-9/42 G06F 9/46 G06F 12/00

Claims (8)

(57) [Claims] 1. Different data in each execution program
Stored by the memory and accessible local register area for register files, and common to each execution program
Stores data global with global register area of the register file memory and inaccessible
A basic central processing unit having a local register set; and an extended register set provided in the integrated circuit device having the basic central processing unit and having a plurality of register sets having the same data amount as the amount of data stored in the local register area. A register file memory comprising a single-port type RAM; and a register set provided in the basic central processing unit and constituting an extended register set of the register file memory from the register set to the local register area . An address data storage register for storing address pointer data indicating a head address of a register set from which data is read in the extension register set; and the basic central processing unit and the register file memory. the connect The global local register cell
A dedicated bus for internal connection having the same number of bits as the bit length of the unit, a component provided outside the integrated circuit device provided with the basic central processing unit, and the basic central processing unit connected to the global central processing unit; Local register set
A dedicated bus for external connection having a bit number of half of the bit length, and when executing an operation using data stored in the global register area, data is read from or written to the global register area and stored in the local register area. When performing an operation using data and writing data to the local register area, the data is also written to the register set of the register file memory. When reading data, the local register area is stored. When the data is read out and the register set constituting the extension register set is changed, the address pointer data of the address data storage register is rewritten and specified on the basis of the rewritten address pointer data in the register file memory. An extended central processing unit, comprising: a control unit in the basic central processing unit that performs operation control so as to perform only an operation of restoring data from a register set to the local register area. 2. The globle in the basic central processing unit.
Global local register set consists of dual port type or triple port type.
The extended central processing unit according to claim 1. The basic central processing unit 3. A with a basic central processing unit in the register set, equipped with the basic central processing unit facilities integrated circuit device, it is possible to read and write the register set and data each A first memory for storing different data in the execution program; and a second memory for storing common data in each execution program and dedicated to reading the register set, and dedicated to the read operation, wherein the register in the basic central processing unit is provided. the register set having the same data amount as the amount of stored data sets comprises a plurality, a memory for Relais <br/> register file having a extended register set, and a memory for the basic central processing unit and said register file Connect the above registers in the basic central processing unit
A bus dedicated for internal connection having the same number of bits as the bit length of the set, a component provided outside the integrated circuit device provided with the basic central processing unit, and the basic central processing unit connected to the basic central processing unit, Of the register set in the processor
When storing data in the register set in the basic central processing unit and the external connection dedicated bus having a bit number of half the bit length , the data is also written in the first memory, and the register file memory is formed. When changing the register set, the data is not saved from the register set in the basic central processing unit to the first memory of the register file memory, but the data is not transferred from the first and second memories of the register file memory. An extended central processing unit, comprising: a control unit in the basic central processing unit that performs an operation control so that only data is restored to the register set in the basic central processing unit. 4. A first address data storage register for storing an address pointer data indicating a head address of an area from which data is read from the first memory, and an address pointer indicating a head address of an area for reading data from the second memory. A second address data storage register for storing data, wherein the control means changes the register set in the basic central processing unit from the register set in the basic central processing unit when changing the register set constituting the register file memory. The first and second memory of the register file memory specified by the address pointer data stored in the first and second address data storage registers without saving the data to the first memory of the memory. From the memory, the register set in the basic central processing unit Performing only return data to the bets, expanded central processing unit according to claim 3, wherein. 5. The extended central processing unit according to claim 3, wherein said register set in said basic central processing unit is of a dual port type or a triple port type. 6. A set register set having two register sets each having one or a plurality of registers,
A central port processing unit, and an extended register set provided in the integrated circuit device provided with the basic central processing unit and having a plurality of register sets having the same data amount as the storage data amount of the set register set, and a single port・ The register file memory composed of a type RAM, the two register sets of the set register set, and the extension register set are separately connected to each other ,
2 having the same number of bits as the bit length of the
When writing the same data as the data stored in each of the register sets of the set register set to the extended register set, and rewriting all the stored data of each of the register sets of the set register set, the extended register set is used. A switch provided on the dedicated bus to perform an on / off operation of data transmission on the dedicated bus so as to transfer data to each of the register sets via the dedicated bus, and an operation control in the basic central processing unit. Do and on
By controlling the on / off operation of the switches,
From the extension register set via the
Connects the control means to perform the data transfer to the static set and the basic central processing unit facilities integrated circuits other element and the base central processing unit provided outside the apparatus, the bit length of the set register set Half of the bi
And an external dedicated bus having a number of units. 7. An address data storage register provided in the basic central processing unit, connected to the control means, and storing address pointer data indicating a head address for reading data from the register file memory. 7. The extended central processing unit according to 6. 8. The extended central processing unit according to claim 6, wherein said set register set is constituted by a dual port type or a triple port type.