JP3206975B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device. More specifically, an FET having a metal film-ferroelectric film-semiconductor layer structure using a ferroelectric film (hereinafter referred to as MFS)
A non-volatile semiconductor memory device capable of selectively writing and non-destructively reading using an FET.

[0002]

2. Description of the Related Art As shown in FIG. 3, a ferroelectric film has a hysteresis. Therefore, once a voltage higher than an electric field (A in FIG. 3) at which sufficient polarization can be obtained is applied, the polarized electric charge becomes polarized. It remains even when the applied voltage becomes 0, and can retain the memory even when the power is turned off. Moreover, by arranging the ferroelectric film between the gate electrode and the channel region, even if a current flows between the source and the drain during reading,
The polarization in the ferroelectric film is not affected and can be read nondestructively, and a memory cell having an MFS-FET structure is being developed.

FIG. 4 shows an example of such an MFS-FET structure.
4 (a) to 4 (c), and FIG. 4 (d) shows the state of the channel when the ferroelectric film is polarized. FIG. 4A shows an example of the simplest structure of the MFS-FET. For example, a ferroelectric film 27 and a gate electrode are formed on the surface of a p-type semiconductor substrate 21.
28, an n ⁺ -type impurity region, for example, is formed on both sides of the channel region 26 on the surface of the semiconductor substrate 21 below the ferroelectric film 27 to form a source region 22 and a drain region 23. The FET is configured. Here, the ferroelectric film 27 is made of PZT having an oxide perovskite structure.
(Pb (Zr _1-x Ti _x ) O ₃ ), PLZT (Pb _1-x La _x (Zr
_1-y Ti _y ) _{1-x / 4} O ₃ ), PbTiO ₃ , BaTiO ₃
Is preferable because a film having good crystallinity can be obtained from the viewpoint of compatibility with the base. The gate electrode 28 is preferably made of platinum from the viewpoint of the orientation of the ferroelectric film 27.

The structure shown in FIG. 4B has an insulating film 25 such as CaF ₂ or SiO ₂ interposed between the ferroelectric film 27 and the semiconductor substrate 21. This is to prevent the Pb of PZT from melting into the semiconductor substrate 21.

In the structure shown in FIG. 4C, an electrode film 24 made of platinum or the like is further interposed between the ferroelectric film 27 and the insulating film 25 shown in FIG. Ferroelectric film 27
Is intended to improve the orientation. That is, SiO ₂
The insulating film 25 is amorphous, and the ferroelectric film 27 such as PZT is crystalline. When the ferroelectric film 27 is formed on the amorphous, the film has no orientation. However, this is because a platinum film having a <111> orientation is obtained, and PZT formed thereon is also a crystalline film having an orientation.

[0006] When a voltage is applied between the gate electrode 28 of the MFS-FET and the semiconductor substrate 21 so that the gate electrode 28 becomes a positive voltage, sufficient polarization is obtained. As shown, electrons are induced in the channel region 26 of the semiconductor substrate 21 to form a depletion layer. Therefore, even when the gate electrode is at 0 V, the voltage is applied to the source region 22 and the drain region 23 of the n ⁺ -type region so that the gate electrode becomes conductive and a sense amplifier (not shown) connected to the source region 22 Through this, the storage state of the ferroelectric film 27 can be read.

However, when the MFS-FETs are arranged as a memory cell in a matrix and used as a storage device, a selection circuit which can selectively perform writing and reading for each cell is required. A circuit conventionally considered as such a selection circuit is disclosed, for example, in Japanese Patent Laid-Open No. 2-6499.
As disclosed in Japanese Unexamined Patent Publication No. 3 (1993), there has been proposed a circuit in which two MOS transistors are connected in series on both sides of a memory MFS-FET.

FIG. 5 shows an equivalent circuit of such a memory cell MC. In this configuration, the writing is first with the transistors T ₁ to ON, the transistor T ₂ O
FF, and the data from the bit line BL is MFS-FET
And application of the memory transistor T _M, the gate electrode of the transistor T _M - voltage 1 / 2Vc of predetermined orientation between the substrates
Apply c. Thus, transistor T _M is the ferroelectric film becomes electric polarization state of the predetermined direction, the data can be written.

On the other hand, in a read operation is also turned on transistors T ₁ advance to turn on the transistor T _2. As a result, depending on the direction of the electric polarization of the ferroelectric film, the memory transistor _TM becomes conductive or non-conductive, corresponding to the storage states “1” and “0”,
Data can be read by detecting a potential change of the bit line BL.

[0010]

The above-mentioned MFS-FET
Is a memory cell structure using MFS-FE for memory.
Since it is composed of one T1 and two MOSFETs,
Since three transistors are formed in one cell, a large cell area is required. Therefore, there is a problem that high integration in which a large number of cells are formed on a chip having a small area cannot be achieved.

Further, in a memory cell using such a ferroelectric film, even if a voltage lower than the threshold voltage is applied to the gate electrode, the polarization state changes and a data error is likely to occur, and a parasitic capacitance and the like are generated. There is a problem that an unnecessary potential difference easily occurs due to the influence of the above.

The present invention solves such a problem and allows a cell to be selected with a simple structure, high integration can be achieved, and an unnecessary potential difference does not occur in the ferroelectric except at the time of writing and erasing. It is an object to provide a semiconductor memory device having a memory cell in which no error occurs.

[0013]

A semiconductor memory device according to the present invention comprises: a nonvolatile memory transistor having at least a ferroelectric film between a gate electrode and a semiconductor substrate;
It is connected to between the gate electrode and the semiconductor substrate of the memory transistor, the gate electrode and the semiconductor substrate
If a voltage is applied during this period, the voltage is maintained
Voltage is applied between the gate electrode and the semiconductor substrate.
If not applied, the floating charge of the gate electrode is discharged.
A potential equivalent means which act that is intended to have a memory cell consisting of the MOS transistors connected to the gate electrode.

Further, in the semiconductor memory device in a matrix according to the present invention, the memory cells are arranged in a matrix by connecting a diode to a source electrode or a drain electrode of the memory transistor of the cell.
Each memory cell is selectively switched by an OS transistor and the diode.

[0015]

According to the present invention, the gate electrode of the MFS-FET is connected to the semiconductor substrate via the potential equalizing means. Since a high resistance of, for example, about 1 G to 1 MΩ is used as the potential equalizing means, even if floating charge due to parasitic capacitance or the like is generated in the gate electrode, the floating charge is discharged through the potential equalizing means and adversely affects the polarization state. Has no effect. In addition, when a voltage is applied between the gate electrode and the semiconductor substrate at the time of writing, reading, or the like, the voltage is held at the gate electrode via the potential equalizing means, so that writing and reading can be performed.

Further, in order to selectively write, read and erase each cell, a MOS transistor connected to the gate electrode of the memory transistor and a diode connected to the source (drain) electrode side of the memory transistor are switched. Therefore, each cell can be selectively driven at a low voltage, and a semiconductor memory device can be configured with a small cell area.

[0017]

Next, a memory cell of a semiconductor memory device according to the present invention will be described with reference to the drawings. FIG. 1 is an equivalent circuit diagram of a main part of a memory cell section according to one embodiment of the present invention.

In FIG. 1, T _M is an MFS- for memory.
In FET, the gate electrode g of the memory transistor T _M is connected to one end of the resistor R of high resistance as a potential equivalent means, the other end of the resistor R is the memory transistor T _M drain (or source) electrode 3, It is connected with the substrate 1. The source of the memory transistor T _M (or drain) electrode 2 is drawn independently to be connected to the bit line. When writing to the memory transistors T _M in this configuration, by the terminal g and the electric field voltage above which sufficient polarization between the substrates will be obtained is applied, the resistor R as a potential equivalent means high resistance Therefore, a voltage is applied across both ends of the ferroelectric film with almost no current flowing, and polarization can be caused in the ferroelectric film. On this occasion,
When a positive voltage is applied to the gate electrode, positive charges are polarized on the semiconductor substrate side of the ferroelectric film, and electrons are induced on the semiconductor substrate surface (channel region) after the write voltage is removed. . Conversely, when a negative voltage is applied to the gate electrode side, negative charges are polarized on the semiconductor substrate side of the ferroelectric film, and holes are induced on the semiconductor substrate surface after the write voltage is removed. You. Therefore, writing or the like is performed by applying a positive or negative voltage to the gate electrode, that is, the terminal g, depending on whether the MFS-FET is the p-channel or the n-channel and according to the setting of the threshold voltage.

[0019] In this embodiment, between the gate electrode and the substrate of the memory transistors T _M, because the memory transistors T _M to the potential equivalent means in parallel (e.g. resistor R) is connected, the voltage on the terminal g is applied Otherwise, even if floating charges are generated, they are discharged through the potential equalizing means, the gate electrode g is kept at the same potential as the substrate, and adversely affects charges polarized in the ferroelectric film due to floating charges and the like. Has no effect.

In the present invention, for selectively applying a voltage to the aforementioned terminal g, and connect the MOS transistor T _S to the gate electrode of the memory transistor T _M to the substrate side terminals c of the MOS transistor T _S or a voltage is applied to the gate electrode of the memory transistor T _M by controlling a voltage applied, and performs switching action or not. Incidentally, by connecting the diode to the terminal b is the source (drain) side of the memory transistors T _M, the memory cell when the semiconductor memory device teamed a matrix, it is possible to read each memory transistor selectively. Side-by-side direction of each memory cell arranged in a matrix and the MOS transistor T second word line c ₁ by connecting the gate electrode e of the substrate c or MOS transistors of _S, c ₂ ... c _n, The The other end of the potential equalization means of each cell arranged in the horizontal direction, the memory transistor T
The connection between the drain (source) electrode of _M and the substrate of the memory transistor is connected to form second bit lines d ₁ , d
₂ ... and _{d n.} Also, the drain electrodes (source electrodes) of the MOS transistors arranged in the vertical direction of each memory cell arranged in a matrix are connected to each other to form a _first word line a ₁ ,
and a ₂ ... a _n, a first bit line by connecting the source (drain) electrode terminal of the memory transistor T _M b _1, b ₂ ... With b _n, memory cells arranged in a matrix Are connected by two word lines and two bit lines, so that each cell can be selectively written, read and erased. The horizontal and vertical connections of each cell described above can be reversed.

Next, writing and reading of a semiconductor memory device in which memory cells according to the present invention are arranged in a matrix,
An erasing driving method will be described.

FIG. 2 is a partial equivalent circuit diagram of a semiconductor memory device in which memory cells according to the present invention are arranged in a matrix. In the figure, M of memory cells in each row
By connecting the substrate of the OS transistor T _S is a second word line _{c 1, c 2 ... c n} , the resistor is a potential equivalent means other end of the memory transistor T _M source (drain) electrode and the substrate Second bit lines d ₁ and d ₂ connecting the connection points
... d _n is formed, in each column arranged in the longitudinal direction of the memory cell of the MOS transistor T _S drain (source) first the electrodes were connected word lines a _1, a ₂ ... a a _n and the memory transistors T _M A first bit line b ₁ , b ₂ ... B in which a terminal via a diode is connected to a drain (source) electrode
_The semiconductor memory device is formed by forming _n . Note that this configuration is the memory transistor T _M is p-channel, in case the MOS transistors T _S example of p-channel, the polarity of the diode if the n-channel also reversed,
The relationship between the drain and the source is also reversed.

[0023] Since the case of the first write to the cell Q ₁ in this configuration must negative voltage -Vcc is applied to the gate electrode g of the memory transistors T _M, the a ₁ -
Voltage of Vcc is applied, as MOS transistor _{T S} for switching is turned ON, the positive voltage Vcc is applied to the c _1, other _{b 1, d 1, a 2} ... a n, b 2 ... b _n ,
_{c 2 ... c n, d 2} ... d n is at 0V. Only between the gate electrode and the substrate of the memory transistors T _M of the cell Q ₁ By doing so, will be a voltage such as a gate electrode is negative is applied, for a ₂ in cell Q ₂ is 0V, M
Since OS transistor _{T S} gate electrode g of the memory transistor _{T M} be turned ON is writing 0V Sarezu and c ₂ in cell Q _3, Q ₄ is 0V, MOS transistor _{T S} is turned OFF no voltage is applied to the gate electrode g of the memory transistors T _M, and the gate electrode g and the substrate by the potential equivalent means R has the same potential, the write is not performed.

Next, reading will be described. Cell Q
_To read ₁ , b ₁ is connected to the measuring means of the sense amplifier SA, Vcc is applied to c ₁ and d ₁ , and a
Apply 0V to ₁ . Further, b ₂ ... it is applied to Vcc to b _n, the other _{a 2 ... a n, c 2} ... c n, d 2 ... d n is a 0V. In the result cell Q ₁ MOS transistor T _S is the gate electrode, the voltage of Vcc is applied to the substrate both to become OFF, the gate electrode and the substrate of the memory transistor T _M is the Vcc voltage of the same potential by the potential equivalent means. However, when a negative charge is polarized on the substrate side of the ferroelectric film by writing, holes are induced in the channel region to be in a conductive state, a current flows between the drain and the source, and the state of "1" is read. Can be. If writing is not performed, the state of “0” can be read out without conduction. In the cell Q ₂ d
_1, b ₂ is regardless drain in the storage state for a Vcc both - can not be read without current flows between the source.
In the cells Q ₃ and Q ₄ , the potentials of b ₁ and b ₂ are higher than the potential of d ₂ , and the diode D is in the opposite direction, so that no current flows between the drain and the source, and reading cannot be performed.

Next, erasure will be described. For erasing the Vcc is applied to the c _1, -V to d ₁ and a ₂ ... a _n
Other by applying cc can delete the cell Q ₁ by all 0V. That, MOS transistors _{T S} for switching the cells Q ₁ is a p-channel,
Since the potential of c ₁ is higher than the potential of d ₁ , it is turned ON,
The gate electrode of the memory transistor _{T M} is higher than -Vcc of the substrate potential (d ₁₎ at a potential i.e. 0V a _1.
Accordingly, the voltage relationship is opposite to that at the time of writing, and the written polarization state is canceled and erased. MOS transistor _{T S} is ON for still in the cell Q ₂ switching
But becomes, for -Vcc in a ₂ is applied, between the gate electrode and the substrate of the memory transistor T _M is the same potential, the erase is not performed. Further, in cells Q ₃ and Q ₄ , MO
Erase becomes S transistor T substrate the same potential of the gate electrode is also the memory transistor of the memory transistor becomes OFF because the gate electrode and the substrate are both 0V of _S is not performed.

The above-described switching MOS transistor T _S and memory transistor T _M are both formed of p-channel, and writing, reading, and erasing are performed on the cell Q _1. It looks like 1. Here, if Vcc is set to about 3 V, the voltage becomes higher than the voltage at which the polarization of the ferroelectric substance can be sufficiently obtained.
It is set in the range of ~ 12V.

[0027]

[Table 1]

[0028] Next, the memory transistor _{T M} remains of the p-channel, MOS transistor T for switching
A driving method when _S is n-channel will be described.

First, in the case of writing, a ₁ , c ₁ , c
₂ ... c _n, applied to -Vcc to d ₂ ... d _n, other b _1, d
_1, a ₂ ... to 0V to a _n and b ₂ ... b _n. That is, when viewed in cell Q _1, MOS transistor _{T S} is the substrate potential than the potential of the gate electrode (d ₁₎ for the n-channel (c ₁₎ is low, turned ON. As a result, the potential of a ₁ -V
cc is applied to the gate electrode of the memory transistor T _M,
Negative charges on the substrate side of the applied voltage ferroelectric between the substrate of the memory transistor T _M (d ₁ = 0) is polarized, the writing is performed. In contrast cell Q ₂ MOS transistor _{T S} for switching becomes the ON, a ₂
Is 0 V, the potential between the gate electrode of the memory transistor and the substrate is the same, and writing is not performed. Also, cells Q ₃ ,
Since Q ₄ In c _2, both -Vcc to d ₂ is applied, MOS transistor is turned OFF, the write no voltage is applied to the gate electrode of the memory transistor is not performed.

Next, reading will be described. In the case of reading, a ₁ , c ₁ , d ₁ and a ₂ ... _An , b ₂ .
Vcc is applied to each of b _n and b ₁ is applied to the sense amplifier SA.
Carried out to 0V c ₂ ... c _n and d ₂ ... d _n to. That is, looking at the cell Q _1, c ₁ and d ₁ are MOS transistors T _S for switching the same potential is OFF, the the gate electrode g and the substrate of the memory transistor T _M is the same potential, the ferroelectric Is stored and polarized, holes are induced in the channel region, and a current flows between the drain and the source, so that reading can be performed. On the other hand, the cell Q _2, the drain - current does not flow even if between the source becomes the channel region even if the conductive state at the same potential. Further, cells Q ₃ , Q
_4, the drain - source voltage of is reversed direction, does not flow through the diode D, not done reading, it can be read only cells Q _1.

[0031] Next, erase, Vcc to a _1, c
By applying -Vcc to ₁ and 0V for all others,
It can be erased only cell Q _1. That is, the switching transistor _{T S} is the substrate side of an n-channel potential (c ₁ = -
Vcc) is a MOS transistor _{T S} is turned ON for switching lower than the potential (d ₁ = 0) of the gate electrode,
Memory transistors T _M gate electrode g is a positive potential Vcc of
Then, the voltage relationship is opposite to that in the case of writing, and the data is erased. On the other hand, in the cell Q ₂ , the MOS transistor T
_S is turned ON similarly, the gate electrode g of the memory transistor _{T M} in a ₂ is 0V, the substrate and the same potential (d ₁ = 0) is not erased next. In addition cell Q _3, Q ₄ MOS transistor _{T S} is turned OFF, the memory transistor T
_No voltage is applied to the _M gate electrode, and no erasing is performed.

The above described, the memory transistor _{T M} is formed by p-channel switching MOS transistor _{T S} is an n-channel, writing, reading, erasing cell Q
Table 2 shows the relationship between the applied voltages in the case of ₁
Put together.

[0033]

[Table 2]

It should be noted in the foregoing examples, although the both memory transistors T _M described in example for p-channel, n
It goes without saying that a channel can be similarly formed.

[0035]

According to the present invention, a non-volatile memory cell using a ferroelectric film is connected to a potential equalizing means between a gate electrode of a memory transistor and a substrate, and a switching MOS transistor is connected to the gate electrode. Since they are connected and formed, and diodes are connected to the source electrode (drain electrode) side and arranged in a matrix, each memory cell can be selectively written, read, and erased. Since it can be formed with a small area, a nonvolatile semiconductor memory device using a ferroelectric film with a small cell area can be configured.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of a memory cell of a semiconductor memory device according to one embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram when memory cells according to an embodiment of the present invention are formed in a matrix.

FIG. 3 is a diagram showing a hysteresis characteristic of a ferroelectric material.

FIGS. 4A to 4C are diagrams showing examples of an MFS structure.
(D) is a diagram illustrating a state when the ferroelectric film is polarized.

FIG. 5 is an example of a circuit configuration of a memory cell of a semiconductor memory device using a conventional MFS-FET.

[Explanation of symbols]

g gate electrode T _M memory transistor _(MFS-FET) T S MOS transistor R resistor D diode

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/105 G11C 16/04 H01L 21/8247 H01L 29/788 H01L 29/792

Claims (2)

(57) [Claims] 1. A non-volatile memory transistor having at least a ferroelectric film between the gate electrode and the semiconductor substrate is connected to between the semiconductor substrate and the gate electrode of the memory transistor, the gate electrode and the semi Guidance
If a voltage is applied between the substrate and
Maintain a voltage between the gate electrode and the semiconductor substrate.
When no voltage is applied, the floating charge of the gate electrode is released.
A semiconductor memory device having a memory cell composed of potential equalizing means for supplying electricity and a MOS transistor connected to the gate electrode. 2. The memory cell according to claim 1, wherein a diode is connected to a source electrode or a drain electrode of said memory transistor of said cell and arranged in a matrix, and each memory cell is selected by said MOS transistor and said diode. A semiconductor memory device which performs switching in a dynamic manner.