JP3207446B2 - System stop method of controller system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a controller system for monitoring and controlling various plants, and in particular, to various data input / output to / from a controlled object without using a floppy disk (FD) or a hard disk (HD). And a system stop method of the controller system which is stored in the RAM backed up by a battery.

[0002]

2. Description of the Related Art Generally, in a controller system for monitoring and controlling various plants, a plurality of application tasks for executing various tasks are stored in a ROM or a hard disk ( HD ). Then, various data (control amount) indicating the operation state of the controlled object input from the controlled object such as a plant via the input / output device is written into a hard disk or the like which is once built in the device.
Each application task executes access to data written to the hard disk. Then, the control operation is executed, and the operation result is sent to the controlled object as an operation amount.

Here, since the amount of data input from the controlled object becomes enormous, the data input from the controlled object is stored in the hard disk as described above.

However, in recent years, semiconductor manufacturing technology has improved, and large-capacity ROMs and large-capacity RAMs can be manufactured at relatively low cost. Therefore, this large capacity ROM and RAM
Is incorporated in the controller system to eliminate the hard disk, thereby reducing the size of the entire system and the manufacturing cost.

[0005] In addition, RA for replacing data with a hard disk
By writing to a data file formed in a large-capacity RAM called an M disk, multitask processing for simultaneously executing a plurality of application tasks becomes possible. In this case, not only the data input / output to / from the controlled object but also the various application tasks described above are stored in the ROM or the RAM.

[0006]

In a controller system that does not use such a floppy disk (FD) or hard disk (HD) at all, the RAM in which the above-mentioned data file is formed retains its stored contents even when the power is turned off. Backed up by battery.

However, when the power of the controller system is cut off or the system is initialized, each application task may be in the process of accessing the data file in the RAM at the moment when the power is cut off or the system is initialized. If incorrect data is written,
Incorrect data is read. Therefore, the erroneous data is stored and held during the power-off period. Then, when the power is turned on next and the interrupted control operation is restarted, there is a problem that the control operation is executed using incorrect data.

Since a floppy disk (FD) or a hard disk (HD) is provided with a control circuit dedicated to the disk, the operation does not stop during access to one piece of data.

The present invention has been made in view of the circumstances as described above. By providing a monitoring task for monitoring the operation state of each application task, the present invention can be applied to a RAM.
Even if a system stop request occurs during data access to the system, the actual system stop is executed after the access processing for the data is completed, and the contents stored in the RAM can be reliably protected, improving the reliability of the entire system. It is an object of the present invention to provide a system stop method of a controller system which can be performed.

[0010]

According to the present invention, a plurality of application tasks are set in a ROM, and data input from a controlled object is temporarily stored in a RAM.
Stored in RAM according to application tasks
In the system stop method of the controller system for performing various accesses to the data stored in the controller and transmitting the result to the controlled object,

A system stop request detecting means for detecting a system stop request such as a power shutoff request or an initialization request, and a monitoring task for monitoring the execution state of each application task are provided. The monitoring task detects the system stop request. And a notification of a system stop request to each application task, each application task receiving the system stop request terminates the corresponding access process when executing access to the RAM, and the monitoring task executes the RAM stop processing in all the application tasks. At the point when the access process for
Issue a system reset command when the specified allowable time has elapsed.
The monitoring task is reset when the allowed time has elapsed.
When a set command is output, information on forced stop
Is written in the RAM.

[0012]

In the system stop method of the controller system configured as described above, when a power switch is turned off or an initialization command is input using a keyboard or the like, a monitoring task is started and each application task is started. A system stop request is sent. If the application task is currently accessing the data to the RAM at that time, the application task executes only the access to the corresponding one of the data, and shifts to the stop state. If the access to the RAM has not been executed, the operation shifts to the stop state. The monitoring task outputs a system reset command when confirming the end of the access state of each application task. Therefore, RA
Since the access operation does not stop during data access to M, erroneous data is not stored and held in the RAM. In addition, all
If some application tasks do not end,
System reset command is output and each application
The disk is forcibly stopped.
Is stored. So restart this system
At that point, it is possible to check the history of forced suspension.
You.

[0013]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the entire controller system employing the system stop method of the embodiment.

The AC power output from the AC power supply 1 is converted by the power supply circuit 3 into a DC control voltage Vc of, for example, 5V. The power supply circuit 2 is provided with a power switch 3 operated by an operator. The control voltage Vc output from the power supply circuit 2 is supplied to a controller 4 composed of, for example, a microcomputer or the like.

In the controller 4, a bus line 5
CPU 6 for executing various arithmetic processing, ROM 7 for storing fixed data such as programs for each task, RAM 9 backed up by battery 8 for temporarily storing variable data such as various data, and connected to controlled objects such as plants. An input / output interface 10, an input / output device 12 to which various commands and data are input from a keyboard 11, a reset signal generation circuit 13 that outputs a reset signal c, and the like are connected. The reset signal c is supplied to the power supply circuit 2 or the CPU 6
And transmitted to the controlled object.

When the power switch 3 is turned on in the power circuit 2, A power supply monitoring circuit 14 for monitoring a cutoff state is connected,
The power cutoff request signal a output from the power supply monitoring circuit 14 is input to the interrupt signal generation circuit 15. The interrupt signal generation circuit 15 also receives an initialization request signal b output from the keyboard 11. Interrupt signal generation circuit 15
Sends an interrupt signal to the interrupt terminal INT of the CPU 6 when the power-off request a or the initialization request signal b is input.

In the power supply circuit 3, when the power switch 3 is turned on, the control voltage Vc is immediately supplied to the controller 4. However, when the power switch 3 is turned off, the reset signal generation circuit 13 Reset signal c
Is inputted, the control voltage Vc is actually cut off.
When the reset signal c is input while the power switch 3 is turned on, the control voltage Vc is not cut off.

In the ROM 7, as shown in FIG.
One monitoring task 16 and a plurality of application tasks 17 are stored. Further, in the RAM 9 in which the stored contents are held by the battery 8 even during the power-off period, a large number of data files 18 are formed as shown in FIG.

In the controller 4 configured as described above, when the power switch 3 of the power supply circuit 2 is turned on and the control voltage Vc is supplied to each electronic component of the controller 4, the reset state is released and the controller 4 is released. Is in an operating state, and each application task 17 is started by an OS task (not shown). Then, the state shifts to the normal operation operation state.

In the normal operation state, various data (control amount) indicating the operation state of the controlled object inputted from the controlled object via the input / output interface 10 at regular intervals are allocated to the corresponding data in the RAM 9. Data file 1
8 is written in a predetermined area. The written data is read and a predetermined control operation is performed. The calculation result is written into the data file 18 again and sent to the controlled object via the input / output interface 10 as an operation amount for the controlled object. Various processes executed in such a normal operation state are executed sequentially or simultaneously by the above-described application tasks.

In such a normal operation state, for example, when the operator turns on the power switch 3, a power cutoff request signal a is input from the power supply monitoring circuit 14 to the interrupt new word generation circuit 15. Similarly, when the operator inputs an initialization command on the keyboard 11 or the like, an initialization request signal b is input from the keyboard 11 to the interrupt signal generation circuit 15. The interrupt signal generating circuit 15 includes a power-off request signal a and an initialization request signal b
When one request signal either is input, it applies an interrupt signal to the CPU6 interrupt terminal INT.

When an interrupt signal is input to the interrupt terminal INT, the CPU 6 activates the monitoring task 16 stored in the ROM 7. When the monitoring task 16 is started, the monitoring task 16 executes a monitoring process for each application task 17 in accordance with the flowchart of FIG.

In FIG. 3, when a monitoring task is started, a system stop request is notified to all application tasks 17 in P (program step) 1. Then, in P2, the operation states of all the application tasks 17 are checked to determine whether all the application tasks 17 are in the stopped state. If it is not in the stop state, the process proceeds to P3, and it is confirmed that the predetermined allowable time Tmax has not elapsed from the system stop request output time in P1. If the allowable time Tmax has not elapsed, the process returns to P2, and it is checked again whether or not all the application tasks 17 are stopped.

When all the application tasks 17 shift to the stop state at P2, a reset request command is output to the reset signal generation circuit 13 at P4. And
This monitoring process ends and the system enters the stopped state. If the allowable time Tmax has elapsed in P3, the process proceeds to P4 and outputs a reset request even if there is an application task 17 in operation.

When a reset request is forcibly output even when the application task 17 is not in the halt state, a forcible halt message is written to a specific data file 18 in the RAM 9.

Each of the application tasks 17 receiving the system stop request from the monitoring task 16 executes a stop process of its own processing job according to the flowchart of FIG.
That is, when the system stop request is received, it is determined in Q1 whether or not data is currently being accessed for the data file 18 of the RAM 9. If the data is being accessed, in Q2, the currently accessed data file 18 is being accessed. The access to one piece of the corresponding data is executed to the end and the processing is terminated. Then, the process proceeds to Q3, where all processing operations are stopped.

If another processing operation such as a control operation other than the data access to the data file 18 in the RAM 9 is currently being executed in Q1, the process immediately proceeds to Q3 and all the processing operations are stopped.

The reset signal generating circuit 13 which has received the reset request command sends a reset signal c to the power supply circuit 2 and the CPU 6. Then, the CPU 6 is reset, and the operation is completely stopped.

The power supply circuit 2 which has received the reset signal c stops supplying the control voltage Vc to the controller 4. Then, the storage contents of each data file 18 in the RAM 9 are stored and held in the battery 8.

If the power switch 3 is turned on when the reset signal c is output, the control voltage V
c is not blocked. In this case, since the initialization request from the keyboard 11 is input, the initialization task is activated, it intends rows predetermined initialization such as the input and output ports.

According to the system stop method of the controller system configured as described above, when the operator turns off the power switch 3 or inputs an initialization request from the keyboard 11, each application task 17 immediately starts. Instead of stopping the operation, it is checked whether or not the data access process to the RAM 9 is currently being executed. If not, the operation is immediately stopped.
After ending the access to the pieces of data, the operation is stopped.

That is, at the time of transition to the operation stop state, data access processing to the RAM 9 is not executed. Therefore, even if the power is turned off or the initialization process is executed in this state, writing of erroneous data to the RAM 9 is prevented beforehand.

Therefore, even if the power is turned on again and the monitoring control work for the controlled object is resumed, the control arithmetic processing can be continued using the correct data stored in the data file 18 of the RAM 9. Further, even after performing the initialization processing, the control calculation processing can be continued using the correct data before the stop. As a result, the reliability of the entire system can be greatly improved.

In the embodiment, the allowable time T
If the application task has not yet reached the end state after elapse of max, the reset signal is forcibly output without waiting for the end. Therefore, it is possible to avoid a situation in which the reset signal is not output by any time and the controller does not stop. In this case, since an abnormal message is stored in the RAM 9, it is possible to grasp that an abnormality has occurred by reading the abnormal message after restarting the operation.

[0035]

As described above, in the system stop method of the controller system according to the present invention, a monitoring task for monitoring the operation state of each application task is provided, and when a system stop request occurs, each application task is executed. Operation stopped after data access was completed. Therefore, even if a system stop request occurs during data access to the RAM, the actual system stop is executed after the access processing for the data is completed, and the storage contents of the RAM can be reliably protected, and the entire system can be protected. Reliability can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a controller system employing a system stop method according to an embodiment of the present invention;

FIG. 2 is a diagram showing storage contents of a ROM and a RAM of the system of the embodiment;

FIG. 3 is a flowchart showing an operation of a monitoring task of the system according to the embodiment;

FIG. 4 is a flowchart showing the operation of each application task of the system of the embodiment.

[Explanation of symbols]

1 AC power supply 2 Power circuit 3 Power switch 4
Controller, 6 CPU, 7 ROM, 8 battery, 9 RAM, 10 input / output interface, 13
Reset signal generation circuit, 14: power supply monitoring circuit, 15: interrupt signal generation circuit.

Claims (1)

(57) [Claims] A plurality of application tasks are set in a ROM, and data input from a controlled object is temporarily stored in an RA.
M and according to the application task,
A system for detecting a system stop request, such as a power-off request or an initialization request, in a system stop method of a controller system for executing various accesses to the data stored in the RAM and sending the results to the controlled object. A stop request detecting unit and a monitoring task for monitoring an execution state of each of the application tasks are provided. When the system stop request is detected, the monitoring task notifies each of the application tasks of a system stop request. Each application task that has received the system stop request terminates the corresponding access process when executing access to the RAM, and the monitoring task terminates the access process to the RAM in all the application tasks ,
Has passed a predetermined allowable time since the system stop request notification
At the time when the system reset command is output, and the monitoring task
When outputting a reset command, force stop
And writing a report to the RAM .