JP3207802B2 - Non-volatile semiconductor memory card - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to relates to a charge storage layer and the control gate can electrically rewritable constructed using the memory cell of a MOS transistor structure having a non-volatile semiconductor (E ² PROM), in particular E ² The present invention relates to a nonvolatile semiconductor memory card in which a plurality of EEPROM chips are integrated on the same substrate.

[0002]

^2. Description of the Related Art In the field of E ² PROM, a memory cell having a MOS transistor structure having a charge storage layer (for example, a floating gate) and a control gate is widely known. This E ² PR
The OM memory cell array is configured by arranging memory cells at intersections of row lines and column lines that intersect each other. In an actual pattern, the drains of two memory cells are made common and a column line is connected here, so that the cell occupation area is made as small as possible. But even so,
A contact portion with a column line is required for each common drain of the two memory cells, and this contact portion occupies a large area of the cell.

As a promising solution to this problem, the present applicant has previously proposed an E ² PROM having a NAND cell configuration (Japanese Patent Application No. 62-233944). This NAND cell is constituted by directly connecting a plurality of memory cells each having a floating gate and a control gate so as to share a source and a drain. The NAND cells are arranged in a matrix, and the drain at one end is connected to a bit line, and the control gate of each memory cell is connected to a word line. The data erasing and writing operations of the NAND cell utilize the tunneling of electrons between the floating gate and the drain layer or the substrate.

The erasing / writing operation will be described specifically.
For data erasing, an "H" level potential of about 20 V is applied to word lines of all memory cells, and an "L" level potential, for example, 0 V, is applied to bit lines. As a result, all the memory cells conduct, and electrons are injected from the substrate into the floating gate by tunneling, so that an erased state (for example, a threshold value of 2 V) in which the threshold value moves in the positive direction. This is collective erasure.

[0005] Data writing is performed sequentially from the memory cell farthest from the bit line among the NAND cells. At this time, for example, an “H” level potential of 23 V is applied to the bit line, and 0 is applied to the word line connected to the selected memory cell.
V is applied, and a 23V "H" level potential is applied to unselected word lines. The word line connected to the already written memory cell is set to 0V. As a result, the "H" level potential of the bit line is transmitted to the drain of the selected memory cell, and in this memory cell, the electrons of the floating gate are discharged to the drain and the threshold value moves in the negative direction "1". (For example, a threshold value of −2 V) is written. At this time, in the memory cell on the bit line side from the selected memory cell, no electric field is applied between the control gate and the substrate,
Keep the erased state.

In the case of "0" writing, an intermediate potential, for example, 11.5 V is applied to the bit line. At this time, the memory cells on the bit line side with respect to the selected memory cell enter a weak erase mode, but these have not been written yet, and
Also, since the electric field is weak, there is no possibility of over-erasing. Data read is performed by applying 0 V to the selected word line and, for example, 5 V to the other word lines, and detecting the presence or absence of a current. If "1", current flows, and if "0", no current flows.

E ² PRO having such a NAND cell configuration
M needs only to provide one contact portion with a bit line for a plurality of memory cells constituting a NAND cell.
It has the advantage that the cell occupied area is smaller than that of a conventional general E ² PROM, but on the other hand, there is a problem that the cell current at the time of reading is small because of the NAND configuration, so that it takes time to read. . This is especially true for NA
This is a serious problem when the number of memory cells constituting the ND cell is increased. To replace a conventional floppy disk or the like with this E ² PROM in the future, the data read time must first be reduced, and at the same time the data write time must be reduced.

[0008]

As described above, conventionally, in an E ² PROM using a nonvolatile semiconductor memory cell, it is important how to write and read data at a high speed when the EEPROM is enlarged. This is a problem to be solved.

The present invention has been made in view of the above circumstances, and an object of the present invention is to enable high-speed data writing and data reading when using a nonvolatile memory cell, and to provide a large-scale memory. An object of the present invention is to provide a nonvolatile semiconductor memory card capable of sufficiently increasing the speed even when the size is increased.

[0010]

To solve the above-mentioned problems, the present invention employs the following configuration.

[0011]

[0012]

[0013]

[0014]

[0015]

[0016]

[0017]

[0018]

[0019]

That is, the present invention is a non-volatile semiconductor memory card comprising an external connection terminal, a non-volatile semiconductor memory chip, and an external interface and a control chip for controlling the non-volatile semiconductor memory chip. A memory cell array including a plurality of memory cell groups each including a plurality of nonvolatile memory cells; a unit for temporarily storing an address signal for selecting the memory cell group; and a memory cell group. And a plurality of data circuits for temporarily storing read data from a plurality of memory cells constituting the memory cell, wherein the address signal is input to the memory chip from the control chip in advance in a first period, and After a second period, the memory chip issues a busy signal to automatically transfer data from the automatically selected memory cell group. Temporarily stored in the read plurality of data circuits, and outputs a plurality of read data continuously in a predetermined order in the third period after the second period to the control chip.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the illustrated embodiments.

FIG. 1 is a block diagram showing the overall configuration of an E ² PROM according to one embodiment. 11 is an E ² PROM array, 12 is a sense amplifier, 13 is a row decoder, 1
4 is a row address buffer, 15 is a column decoder, 17 is a data-in buffer, and 18 is a data-out buffer. A shift register 16 for temporarily storing input data and output data is provided between the row decoder 15 and the data-in buffer 17 and the data-out buffer 18. These circuits are integrated on one chip substrate.

FIG. 2 is an equivalent circuit diagram of the E ² PROM array 11 of FIG. In this embodiment, four memory cells M _{1 to} M ₄ are directly connected to form a NAND cell, and such NAND cells are arranged in a matrix. The drain of the NAND cell is connected to the bit line BL via the first selection MOS transistor S1n (n = 1 to 512), and the source is the second selection MOS transistor S2n.
(N = 1 to 512). The control gate of each memory cell is connected to a word line WL crossing the bit line BL.

FIG. 3 is a plan view showing one NAND cell, and FIGS. 4A and 4B are cross-sectional views taken along the lines AA 'and BB'. As described above, four memory cells and two select transistors are formed in a region defined by the element isolation insulating film 2 of the p ⁻ type silicon substrate 1. Each memory cell has a floating gate 4 (4) made of a first polycrystalline silicon film via a first gate insulating film 3 made of a thermal oxide film on a substrate 1.
_{1-4 8)} is formed, the second layer polycrystalline silicon film according to the control gate 6 through a second gate insulating film 5 thereon (6
And it is configured to form a _{1-6 8).} The control gate 6 of each memory cell is connected to a word line WL (WL _{1 to} W
L ₈ ).

N ^{+ serving as} the source and drain of the memory cell
Four memory cells are connected in series so that the mold layer 9 is shared by adjacent ones. And in this embodiment,
The selection transistors S ₁ and S ₃ are connected to the drain side and the source side to form one NAND cell.

The patterned first layer gate electrode 4 _9, 6 ₉ and 4 _10, 6 ₁₀ of the selection transistors S _1, S ₃ is to constitute the floating gates and the control gates of the memory cells, a second layer polycrystalline silicon film at the same time And electrodes ₄₉ and 6
Contact between the electrodes ₉ and between the electrodes 4 ₁₀ and 6 ₁₀ is at a predetermined interval in the word line direction. The whole is covered with a CVD insulating film 7, and an Al wiring 8 is arranged as a bit line BL for contacting the memory cell with an n ⁺ -type layer that is the drain of the selection transistor S ₁ .

The coupling capacitance C ₁ between the floating gate 4 and the substrate 1 in each memory cell is set smaller than the coupling capacitance C ₂ between the floating gate 4 control gate 6. Explaining specific shapes and dimensions, the floating gate 4 and the control gate 6
Both have a pattern width of 1 μm, and therefore the channel length of the memory cell is 1 μm, and the floating gate 4 extends 1 μm on both sides of the field region as shown in FIG. 4B. The first gate insulating film 3 is a 20 nm thermal oxide film, and the second gate insulating film 5 is a 35 nm thermal oxide film.

As shown in FIG. 2, such NAND cells are repeatedly arranged in a bit line direction while sharing a bit line contact and a source diffusion layer. FIG.
FIG. 9 is a timing chart for explaining an erasing and writing operation when focusing on a NAND cell composed of memory cells M _{1 to} M ₈ .

First, the memory cells M _{1 to} M ₄ constituting the NAND cell are erased collectively. Therefore, in this embodiment, an “H” level (for example, a boosted potential Vpp = 20 V) is applied to the gate electrode SG ₁ of the selection transistor S ₁ ,
A gate electrode SG ₂ also "H" level of the selection transistors S ₂ (e.g., Vcc = 5V), keeping the drain of all the memory cells in the NAND cell, the source to 0V, and the word lines WL ₁ to WL ₄ "H" Level (for example, Vpp = 20V)
give.

As a result, an electric field is applied between the control gates of the memory cells M _{1 to} M ₄ , the source, the drain, and the substrate, and electrons are injected into the floating gate by a tunnel effect. As a result, the threshold value of the memory cells M _{1 to} M ₄ moves in the positive direction, and the memory cells M _{1 to} M ₄ enter the “0” state. Thus, the word line WL
All of the NAND cells along ₁ to WL ₄ are collectively erased.

Next, data is written to the NAND cell. Data writing is performed in order from the memory cell M ₄ distant from the bit line BL. This is because at the time of writing, a memory cell located on the bit line side of the selected memory cell is in the erase mode.

[0032] First writing to the memory cell M ₄ is (threshold of the erase state of the memory cell) boosted potential Vpp + Vth to the gate SG ₁ and the word lines WL ₁ to WL ₃ of the selection transistors S _1, as shown in FIG. 5 The above “H” level (for example, 23 V) is applied. The gate electrode SG ₂ of the word line WL ₄ connected to the control gate select transistor S ₂ of the selected memory cell M ₄ is at "L" level. In this case the bit line BL give "H" level which is transmitted to the drain of the memory cell M ₄ through the channel of the select transistors S ₁ and the memory cell M ₁ ~M _3, the memory cell M ₄ the control gate And a high electric field is applied between the substrates.

As a result, the electrons of the floating gate are emitted to the substrate by the tunnel effect, and the threshold value moves in the negative direction, for example, to the state "1" of the threshold value -2V. At this time keeping the erase state not applied electric field between the memory cells M ₁ ~M ₃ the control gate and the substrate. In the case of “0” writing, an intermediate potential (for example, 10 V) is applied to the bit line BL.

[0034] Turning now to the writing of the memory cell M _3. That remains the select gate SG _1, SG ₂ was maintained at "H" level, the word line WL ₃ "L" level. If this time the bit line BL "H" level is given, the memory cell M ₃ "1" write is performed. Hereinafter, similarly, writing is sequentially performed on the memory cells M ₂ and M ₁ .

The configuration and operation of the basic NAND cell constituting the E ² PROM according to the embodiment have been described above. Next, the operation of the entire configuration of FIG. 1 including the memory array using such NAND cells and its peripheral circuits will be described. In this embodiment, the E ² PROM array 11
, The number of bit lines is 512, and the shift register 16
Has a capacity four times the number of bit lines.

[0036] FIG. 6 is a timing diagram illustrating the data erasing and writing operation by the E ² PROM page mode. When the chip enable signal / CE goes low, the E ² PROM chip becomes active. / OE is an output enable signal which is in a write mode when it is at "H" level. / WE is a write enable signal which takes in an address when it changes from "H" level to "L" level. The address specifies one block of the memory array shown in FIG. SIC is a serial input counter, which takes in input data when it goes from "L" level to "H" level.

R./B is a Ready./Busy signal, which becomes "L" level during writing to notify the outside that writing is in progress. By repeating the cycle of “H” level → “L” level → “H” level of the serial input counter SIC for one page (in this embodiment, four times the number of bit lines 512 of the memory array), The data for one page is stored in the shift register 16.
It is taken in at high speed. The data temporarily stored in the shift register 16 is simultaneously transferred to the bit lines of the memory array 11 and written to the memory cell specified by the address.

Therefore, according to this embodiment, the time required to write 512.times.4 bits of data in the page mode is the time taken to capture 512.times.4 data, with 1 microsecond as the time to take in one piece of external data. (= 1μsec
× 512 × 4) + erase time (10 msec) + write time (10 msec) ≒ 22 msec. By the way,
In the case where there is no shift register 16 and data of the same number of bits is written without using the page mode, the write time and the erase time are both set to 10 msec and 512 × 2
0 msec ≒ 41 sec. Thus, according to this embodiment, high-speed writing of about 1850 times becomes possible.

FIG. 7 is a timing chart for explaining a read operation. When the chip enable / CE changes from "H" level to "L" level, an address is fetched. The data written to the E ² PROM at the time of writing is such that the serial output counter SOC changes from “L” level to “H” in the same order as input at the time of writing.
It is output one by one when the level is reached. R / B stores 512 × 4 data from the memory cells in the shift register 16
To the "L" level during the transfer, and notifies the output wait to the outside. Since a large number of bits of data are fetched into the shift register 16 in parallel at the same time and are read out serially, data reading is performed at a much higher speed than when no shift register is provided.

FIGS. 14A and 14B show the shift register 1.
6 and a flip-flop F used for the same.
It is a configuration example of F (FF ₁ , FF ₂ ,...). Flip-flop FF includes p-channel MOS transistors Q ₁ and n
Channel MOS transistor Q ₂ is on, serves as a flip-flop when the p-channel MOS transistor Q ₃ and n-channel MOS transistor Q ₄ is turned off, the Conversely state is two-stage inverter column.

FIG. 15 is a timing chart showing an operation of inputting data from the data-in buffer of the shift register. φ and / φ are clock signals generated inside the chip from the serial input counter signal SIC.
For example phi is "L" level, / phi is data from the data-in buffer in the first-stage flip-flop FF ₁ of the shift register when at the "H" level is transferred. Next, φ becomes “H”
Level, / when φ is "L" level, the flip-flop data FF ₁ is transferred to the flip-flop FF _2. Thereafter, data is sequentially transferred in a similar manner.

FIG. 16 is a timing chart showing an operation of transferring data from the shift register to the data out buffer. The clocks φ and / φ in this case are generated inside the chip from the serial output counter signal SOC.

Thus, according to this embodiment, E ² PR
By incorporating a shift register in the OM, data writing and reading can be performed at high speed.

FIG. 8 shows an E ² PR according to another embodiment of the present invention.
It is a block diagram showing OM. This embodiment uses a magnetic recording medium such as a floppy disk or the like as an E ² PROM.
The first E ² PROM array 19 composed of NAND cells for recording the first type of information, and the second type of information using the conventional memory cell configuration are assumed. A second E ² PROM array 27 for recording is integrally formed on the same substrate.

The configuration of the first E ² PROM array 19 is the same as in the previous embodiment. The first E ² sense amplifier 20 around the PROM array 19 for detecting an output, a row decoder 23, row address buffer 22, column decoder 2
3 and the like, and a shift register 24 for temporarily storing input / output data as in the previous embodiment is provided. Around the ^second EEPROM array 27, a sense amplifier 28, a column address buffer 31, a row decoder 29
Etc. are arranged. 25 is a data-in buffer and 26 is a data-out buffer.

FIG. 9 shows the E ² PRO thus constructed.
FIG. 9 is a timing chart for explaining data erasing and writing operations in M. The E ² PROM is active when the chip enable signal / CE is at "L" level. / OE is an output enable signal, and when this signal is at "H" level, it is in the write mode. / DIRE is a directory memory enable signal, which accesses the second E ² PROM array 27 when it is at “L” level.

When / DIRE is at "L" level, an address is fetched when the write enable / WE changes from "H" level to "L" level, and when the write enable / WE is changed from "L" level to "H" level, input data is fetched. Put in. Second E ² PROM
The array 27 is erased and written one byte at a time.
When / DIRE is at “H” level, the first E ² PRO
The M array 19 is accessed. The operation at this time is the same as in the previous embodiment.

FIG. 10 is a timing chart for explaining a read operation. / When DIRE is at the "L" level, the second E ² PROM array 27 is accessed when / CE becomes "L" level from "H" level, or the read operation when the address is changed. The output data is read one byte at a time. / When DIRE is at the "H" level, the first E ² PROM array 19 is accessed.
The operation of the first E ² PROM array 19 at this time is the same as that described in the previous embodiment.

The E ² PROM according to this embodiment can be applied to, for example, storing and holding software of a computer. The second E ² PROM array 27 that performs erasing, writing, and reading operations byte by byte includes a file A memory area (directory memory area) for storing information, for example, storing contents as shown in FIG. First E ² PRO for batch erase / write / read
The M array 19 is a memory area (data area) for storing the contents of a file.
It is 56 bytes.

Thus, the E ² PROM according to this embodiment
By replacing a floppy disk with a disk drive, a disk drive device, a disk drive interface, and the like are not required, and high speed, light weight, small size, and power saving can be achieved.

FIGS. 12A and 12B are a perspective view and a plan view of an embodiment in which the present invention is applied to an LSI memory card. Reference numeral 32 denotes the E ² PROM chip described in the embodiment of FIG. 1, and here, the E ² PROM chip 32 is mounted. With respect to these E ² PROM chips 32, E ² PRO as a directory memory area corresponding to the E ² PROM array 27 shown in the embodiment of FIG.
A control LSI which mounts one M chip 33 and functions as an interface between these memory chips and the outside.
The chip 34 is mounted. 35 is a connection terminal. FIG. 13 shows the system configuration of this LSI memory card.

Thus, according to the present embodiment, a high-speed, compact, lightweight, and power-saving memory card can be obtained.

[0053]

As described above in detail, according to the present invention, data writing and data reading can be performed at a high speed when a nonvolatile memory cell is used, and a sufficiently high speed can be obtained even when the scale is increased. Can be changed. Also, by using a plurality of memory chips as a memory area for storing file contents and a different memory chip as a memory area for managing file information, a disk drive device and a disk drive interface are not required. ,
It can be used as a substitute for a floppy disk, and can achieve high speed, light weight, and low power.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an E ² PROM according to an embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram showing a memory array configuration of the E ² PROM of FIG. 1;

FIG. 3 is a plan view showing one NAND cell of the E ² PROM of FIG. 1;

FIG. 4 is a sectional view taken along line AA ′ and BB ′ of FIG. 3;

FIG. 5 is a timing chart for explaining an erase operation and a write operation of a NAND cell.

FIG. 6 is a timing chart for explaining an erase / write operation of the E ² PROM of the embodiment.

FIG. 7 is a timing chart for explaining a read operation of the E ² PROM of the embodiment.

FIG. 8 is a block diagram showing an E ² PROM according to another embodiment.

FIG. 9 is a timing chart for explaining an erase / write operation of the E ² PROM of FIG. 8;

FIG. 10 is a timing chart for explaining a read operation of the E ² PORO of FIG. 8;

FIG. 11 is a diagram showing a configuration example of a directory memory area.

FIG. 12 is a perspective view and a plan view showing a memory card according to still another embodiment of the present invention.

FIG. 13 is a system configuration diagram of the memory card in FIG. 12;

FIG. 14 is a diagram showing a specific configuration example of a shift register used in the present invention and components thereof.

15 is a timing chart for explaining a data input operation to the shift register of FIG. 14;

FIG. 16 is a timing chart for explaining a data output operation to the shift register in FIG. 14;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor substrate 2 element isolation insulating film 3 5 gate insulating film 4 floating gate 6 control gate 7 CVD insulating film 8 bit line 9 n ⁺ type layer 11 NAND cell type memory cell array 12 sense Amplifier 13 Row decoder 14 Row address buffer 15 Column decoder 16 Shift register 17 Data in buffer 18 Data out buffer 19 First E ² PROM array 20 Sense amplifier 21 Row decoder 22 Row address buffer 23 column decoder 24 shift register 25 data in buffer 26 data out buffer 27 second E ² PROM array 28 sense amplifier 29 row decoder 30 column decoder 31 column address buffer

Continuation of the front page (72) Inventor Yasuo Ito 1 Toshiba-cho, Komukai-shi, Kawasaki-shi, Kanagawa Prefecture Inside the Toshiba Research Institute Co., Ltd. Inside Toshiba Research Institute (72) Inventor Fujio Masuzuoka 1st place, Komukai Toshiba-cho, Saiwai-ku, Kawasaki City, Kanagawa Prefecture Inside Toshiba Research Institute, Inc. (56) References JP-A-59-217293 (JP, A) 124298 (JP, A) JP-A-57-53899 (JP, A) JP-A-61-216520 (JP, A) JP-A-62-18698 (JP, A) (58) Fields investigated (Int. ^7, DB name) G11C 16/00 - 16/34 G11C 17/18

Claims (1)

(57) [Claims] 1. A non-volatile semiconductor memory card comprising an external connection terminal, a non-volatile semiconductor memory chip, and an external interface and a control chip for controlling the non-volatile semiconductor memory chip. The nonvolatile semiconductor memory chip comprises a memory cell array including a plurality of memory cell groups each including a plurality of nonvolatile memory cells, a unit for temporarily storing an address signal for selecting the memory cell group, and the memory cell group. A plurality of data circuits for temporarily storing read data from a plurality of memory cells, wherein the address signal is input to the memory chip from the control chip in advance during a first period, and In a second period after the period, the memory chip issues a busy signal to read data from the automatically selected memory cell group. A method of temporarily storing the read data in the plurality of data circuits and outputting a plurality of read data to the control chip continuously in a predetermined order in a third period after the second period. Semiconductor memory card.