JP3208292B2 - Composite PIN semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a composite P which is formed by combining three PIN semiconductor elements and connecting them in a .pi. Type or a T type.
It relates to an IN semiconductor device.

[0002]

2. Description of the Related Art An attenuator using a PIN diode has a constant input / output impedance characteristic of, for example, 50Ω or 75Ω. Therefore, an AGC (auto gain control) is provided before and after various high-frequency matching circuits and RF amplifier circuits. ) Used as a circuit. FIG. 4 (A)
An example is shown in which the anode side and the cathode side of one PIN diode 1a are connected to the cathode sides of two other PIN diodes 1b and 1c to form a π-type attenuator.
FIG. 1B shows an example in which the cathode sides of two PIN diodes 2a and 2b and the anode side of one PIN diode 2c are connected to form a T-type attenuator.

The above-described PIN diode is provided in a state of being built in a surface-mount type package. FIG. 5 shows an example of the package. In this example, three leads 3a,
3b, 3c, one of the leads 3a has a PIN
The cathode side of the diode 4 is die-bonded, and the anode side of the PIN diode 4 is wire-bonded to another lead 3b. The leads 3a, 3b, 3c and the PIN diode chip 4 are
Covered with. The reason why three leads are provided in spite of being a diode is to consider sharing with a surface mounting package of another semiconductor device such as a transistor. The resin package 5 is vertical,
The width and height are 1.5 mm, 2.9 mm, and 1.1 mm, respectively.

[0004]

Conventionally, as shown in FIG. 5, only one PIN diode is built in one package. Therefore, FIG.
When a circuit composed of three elements is configured like the attenuator shown in FIG. 3B, it is necessary to mount three independent packages on the substrate, and the mounting area increases. In particular, when the package is shared as shown in FIG. 5, the package is larger than the built-in semiconductor chip, and the wasteful mounting area is likely to increase. In addition, when one package is used for one element, both the connection between the semiconductor element and its peripheral circuit and the connection between the elements must be performed on the substrate, which complicates the wiring design on the substrate. .

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and can reduce the mounting area of a π-type or T-type attenuator circuit using three PIN semiconductor elements, and can reduce the wiring load. It is an object to provide a composite PIN semiconductor device.

[0006]

SUMMARY OF THE INVENTION The present invention provides three PINs.
A composite PIN semiconductor device in which semiconductor elements are connected in a π-type or a T-type, wherein the three PIN semiconductor elements are incorporated in a single package having four leads, and the first lead is provided in the package. On the other hand, the cathode sides of two PIN semiconductor elements are connected to the cathode side of another PIN semiconductor element with respect to the second lead, and the anode side of one PIN semiconductor element whose cathode side is connected to the first lead. The third lead and the fourth lead are connected to each other, and the anode side of one PIN semiconductor element is connected to each of the third lead and the fourth lead.

According to the above configuration, since three PIN semiconductor elements are connected in one package in a π-type or T-type and built in, a desired area can be reduced with a smaller area than a combination of three single PIN semiconductor element packages. Can be configured. Further, since it is not necessary to connect a single PIN semiconductor element to each other on the substrate, for example, the design of the circuit board of the attenuator becomes easy and the number of design steps can be reduced.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS.

FIG. 1A is a diagram showing the internal structure of the semiconductor device according to the first embodiment of the present invention. This device comprises three PIN diodes 11, 12, 13 and four leads 14, 15, 16, 17. Two PIN diodes 11 and 12 are attached to a lead 14 at the upper left in the figure. The cathode sides of the diodes 11 and 12 are die-bonded and electrically connected to the leads 14. The anode side of one PIN diode 11 is connected to a lead 15 on the upper right, and the other PIN diode 12
Is connected to the lower left lead 17 via bonding wires 11a and 12a, respectively. Although the lead 14 is provided with an enlarged portion 14a capable of wire bonding, the enlarged portion 14a is not used in this example.

Another PIN diode 13 is attached to the upper right lead 15. The cathode side of the PIN diode 13 is die-bonded to the lead 15 and is electrically connected. The anode side is electrically connected to a lower right lead 16 via a bonding wire 13a.

As described above, the PIN diodes 11 to 13
After the leads 14 to 17 are connected, the leads 14 to 1
The entirety except for the terminal portion 7 is molded in a resin package 18 and then lead-processed. FIG. 1B schematically shows the internal wiring of the packaged semiconductor device. As apparent from this figure, the three PIN diodes 11 to 13 are connected so as to form a π-type attenuator. This semiconductor device can be used, for example, in a portion surrounded by a broken line La in the circuit in FIG.

FIG. 2A is a diagram showing an internal structure of a semiconductor device according to a second embodiment of the present invention. In addition,
The same reference numerals are used for common parts with FIG. In this device, the anode side of the PIN diode 11 on the lead 14 is connected to the lower left lead 17, and the anode side of the PIN diode 12 is connected to the lower right lead 16. The PIN diode 13 is attached to the lower right lead 16. The cathode side of the PIN diode 13 is a lead 16 and the anode side is a lead 15 on the upper right.
And are connected respectively.

FIG. 2B schematically shows the inside of the semiconductor device shown in FIG. As is clear from the figure, also in this example, the three PIN diodes 11 to 13
Connected to form a mold attenuator. However, as compared with the case of FIG. 1, the electrical connection to the upper right lead 15 and the lower right lead 16 has been switched.
That is, in this connection, the terminals 16 to 14 of the diode 12 are connected.
Corresponds to a horizontal character of π, and the diodes 13 and 11 correspond to a foot portion of π.

Which of the devices shown in FIG. 1 and FIG. 2 should be used may be selected according to the connection state of the peripheral circuits of the device. As described above, the package 1 according to the state of the peripheral circuit
Since the connection mode between the semiconductor diodes 11 to 13 in the device 8 can be changed, the circuit wiring on the substrate on which the package 18 is mounted can be easily designed.

FIG. 3A is a diagram showing an internal structure of a semiconductor device according to a third embodiment of the present invention. In addition,
1 and 2 are denoted by the same reference numerals. In this device, a PIN diode 13 is die-bonded to a lead 15 at the upper right, and the cathode side is connected to the lead 15.
The anode side is connected to the upper left lead 14, respectively. Other points are the same as FIG. When connecting the PIN diode 13 to the lead 14, the bonding wire 13a is joined using the enlarged portion 14a.

FIG. 3B schematically shows the inside of the semiconductor device shown in FIG. As is apparent from the figure, in this example, the three PIN diodes 11 to 13 are T
Connected to form a mold attenuator. This semiconductor device can be used, for example, in a portion surrounded by a broken line Lb in the circuit in FIG.

In the embodiment of FIGS. 1, 2 and 3,
The chip sizes of the used PIN diodes 11 to 13 are all substantially the same, for example, 0.3 mm ×
A chip having an area of 0.3 mm is used. It is housed in a resin package 18 having the same size as a conventional package and measuring 1.5 mm, 2.9 mm, and 1.1 mm in height, width, and height, respectively.

FIGS. 1 to 3 show the lead frame.
Are designed so that they can be shared by all of the embodiments. In other words, of the four leads, the lead 14 has two regions (die bond areas) for mounting the two PIN diodes 11 and 12, and the wire 13a used in the embodiment of FIG. One region (wire bond area) is formed, one of the two die bond areas is brought close to the lead 17, and the other is placed in the middle of the leads 16,17. The wire bond area is constituted by an enlarged portion 14a. Leads 14 and 16 are PI
One die bond area for mounting the N diode 13 and one wire bond area used in the embodiment of FIG. 1 are formed. Since no chip is mounted on the lead 17, one wire bond area is formed.

The die bond area requires an area equivalent to the chip size, and the wire bond area depends on the size of the capillary at the time of wire bonding. A region having an area of about 3 mm is required. As described above, by forming two die bond areas and one wire bond area on one lead, both the T-type and the π-type can be shared by lead frames having the same pattern.

In the above, the case where the attenuator circuit is configured using the PIN diode has been described. However, the present invention is not limited to such an embodiment, and is applicable to various circuit devices using a combination of three PIN semiconductor elements. Of course you can.

[0021]

As described above, according to the present invention, three PIN semiconductor elements are packaged in one package by a π-type or a T-type.
Since it is connected and built into the mold, a desired circuit can be configured with a smaller area than combining a plurality of packages of PIN semiconductor elements, and thus the circuit can be downsized. Also, according to the connection mode between the four leads and the three elements,
Since the connection mode between the PIN semiconductor elements can be variously changed to the π-type or the T-type, the design of a circuit in which the semiconductor device is incorporated can be facilitated. This makes it possible to economically provide an attenuator using a PIN diode.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention, and FIG.
3A is a diagram showing the internal structure of the package, and FIG. 3B is a diagram schematically showing the connection mode of FIG.

FIG. 2 is a diagram showing a second embodiment of the present invention, and FIG.
3A is a diagram showing the internal structure of the package, and FIG. 3B is a diagram schematically showing the connection mode of FIG.

FIG. 3 is a diagram showing a third embodiment of the present invention, and FIG.
3A is a diagram showing the internal structure of the package, and FIG. 3B is a diagram schematically showing the connection mode of FIG.

4A and 4B are diagrams illustrating an example of a circuit in which PIN semiconductor elements are combined, in which FIG. 4A illustrates an example in which a π-type attenuator is configured, and FIG. 4B illustrates an example in which a T-type attenuator is configured;

FIG. 5 is a diagram showing an example of a surface mount type package.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-56-6024 (JP, A) JP-A-61-7712 (JP, A) JP-A-1-156562 (JP, U) JP-A 55- 40559 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03H 7/25 H01L 23/48 H01L 25/07

Claims (1)

(57) [Claims] 1. A composite PIN semiconductor device in which three PIN semiconductor elements are connected in a π or T type, wherein said three PIN semiconductor elements are incorporated in a single package having first to fourth leads, The first lead has two die bond areas and one wire bond area; the second and third leads have one die bond area and one wire bond area; One of the die bond areas is third
When extends to substantially intermediate fourth lead, in the package, two PIN semiconductor element whose mosquitoes for two die-bonding area of the first lead
One PIN semiconductor element is die-bonded so as to connect the sword side, and another PIN semiconductor element is placed in the die-bonding area of one of the second and third leads.
It is die-bonded so as to connect the over de side, characterized in that the anode of the PIN semiconductor device to perform the connection of the π type or T type is connected to the wire bond area of one of the lead by a bonding wire Composite PIN semiconductor device.