JP3208601B2 - High efficiency coding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal recording / reproducing apparatus such as a video tape recorder (hereinafter abbreviated as VTR) for digitally recording and reproducing a video signal and an audio signal, and a digital signal recording / reproducing apparatus such as a video disc player. The present invention relates to an apparatus for transmitting and storing data using encoding.

[0002]

2. Description of the Related Art In a digital signal recording / reproducing apparatus, it is necessary to compress and record an enormous amount of information of a digital video signal in order to downsize the apparatus. Methods for compressing digital video signals include motion compensated prediction, orthogonal transform, and in particular, discrete cosine transform (D).
Variable Length Coding (VL) such as Huffman coding in addition to a method based on CT, band division, etc.
C), compress by arithmetic coding, etc., and transmit and store. For example, FIG. 8 shows a conventional digital video signal encoding apparatus using motion compensation prediction.

In FIG. 8, 1 is an input terminal for an analog video signal, 2 is an A / D converter for converting the analog video signal into a digital video signal, and 3 is a digital video signal which is divided into blocks of a predetermined size and shape. It is a block circuit. Reference numeral 4 denotes a subtracter that performs a block-by-block subtraction between an input block and a prediction block generated by motion-compensated prediction from a past video when coding a prediction frame or a prediction field, and generates an error block. 5, a DCT circuit for performing discrete cosine transform of an input block if a refresh frame or a refresh field is not performed and an error block of a predicted frame or a predictive field; and 6 a DCT circuit based on a signal from a buffer memory described later. A quantization circuit 7 for quantizing the coefficient, and a VLC circuit 7 for performing variable length coding on the quantized data.

[0004] Numeral 8 stores a variable-length codeword in order to keep the transmission rate constant, and transmits a signal for controlling the quantization step size to be changed to a quantization circuit in accordance with the empty state of the buffer memory at that time. A buffer memory 9 is an output terminal. Reference numeral 10 denotes a local decoder unit that performs inverse quantization on the quantized data, performs inverse DCT, and performs motion compensation prediction, and is an MC circuit.

Next, the operation of FIG. 8 will be described. An analog video signal is input to an input terminal 1, and the analog video signal is converted into a digital video signal by an A / D converter 2.
The digital video signal is input to the blocking circuit 3 and is blocked into a predetermined size and a predetermined shape. For example, 8
Blocking is performed such that [pixels] × 8 [lines] constitute one block. Assuming that the block data is an input block, this input block is sent to the DCT circuit 5 as it is if the input block is included in a refresh frame or a refresh field that is not subjected to prediction processing.

The input block is also sent to the MC circuit 10 and used for motion compensation prediction processing. And MC circuit 10
And the input block described above are subtracted by the subtractor 4 to form an error block. However, the error block is calculated when the input block used to calculate the error block belongs to a prediction frame to be subjected to a prediction process. Then, the calculated error block is applied to the DCT circuit 5.
Sent to

The DCT circuit 5 applies a DCT to an input block if the frame or field being processed is a refresh frame or a refresh field, and an error block if the frame or field being processed is a predicted frame or a predicted field. Is applied. The DCT coefficient output from the DCT circuit 5 is quantized by a quantization circuit 6 in a quantization step set based on a signal from a buffer memory 8 described later.
The variable length coding is performed by the LC circuit 7. The block output from the quantization circuit 6 has a quantized DCT coefficient as its internal data, and is divided into a sequence as shown in FIG. In this sequence, it is generally said that useful information for image information is concentrated in the low-frequency component, and that the distribution of data becomes smaller in the higher-frequency component, and that the usefulness for the image information is reduced.

In the high-frequency component, the sequence in which the data is 0 increases, and when the data is arranged in the order shown in FIG. 9, the higher the high-frequency component, the more the 0 continues. Utilizing this property, a length as shown in FIG. 10 is combined with a non-zero data value generated thereafter and replaced with a code as shown in FIG. Figure
Numeral 10 is an example of a VLC code, and the zero run length is the number of consecutive zeros until the next non-zero data appears. The data is the actual data in the sequence. The zero run length and the data are set as one set to correspond to one code.

For example, assuming that data as shown in FIG. 11 is distributed, if the data is arranged in the order as shown in FIG. 9, the DC, DC component, 10, 15, 4, 0,
.., 3, 1, 0, 1, 1, 0, 0,... This is replaced with the code shown in FIG. For example, after the value of DC, the combination of (zero run length, data) is (0, 10), (0, 15),
(0, 4), (1, 3), (0, 1), (1, 1),
.. Are replaced with codes as combinations such as (0, 1). When 0 continues to the end of the block and when the end of the block is indicated, the EOB code (END of
BLOCK) is added to end the encoding of the block.

In this case, by assigning a shorter code to an object having a higher occurrence probability and assigning a longer code to an object having a lower occurrence probability, the number of necessary bits is reduced as a whole, and the amount of information can be compressed.

[0011] Such a VLC code is stored in the buffer memory 8 as a code word. The buffer memory 8 accumulates the length of the input VLC code, that is, the length of the generated code word, calculates the remaining amount of the buffer memory 8, controls the amount of data generated later, and sets the data amount within the processing unit. Is transmitted to the quantization circuit 6 so that is constant.

For example, the buffer memory amount for one frame processing (when the processing unit is one frame) is held, the generated data amount is accumulated, and the remaining amount of the buffer memory and the number of blocks in the processing unit requiring processing are stored. The remaining steps are compared to determine the quantization step of the next block to be subjected to the quantization process.

FIG. 12 illustrates the operation in detail. FIG. 12 shows the number of processing blocks / the total number of blocks on the horizontal axis.
The vertical axis indicates the sum of the generated code amounts / the total amount of the buffer memory. Now, assuming that the processing of 20% of the total number of blocks has been completed and the code amount exceeding 20% of the total amount of the buffer memory is accumulated in the buffer memory (point A in FIG. 12), the quantization step must be increased. As shown at point B in FIG. 12, the buffer memory total amount overflows. Therefore, it is necessary to increase the quantization step of the block for which quantization processing is to be performed next at point A, reduce the generated code amount, and control the generated code amount. If there is room in the buffer memory, control is performed so as to reduce the quantization step and increase the generated code amount.

The code word thus controlled is output from the output terminal 9 when the processing unit including a plurality of blocks ends.

In order to perform the motion compensation prediction process, the output of the quantization circuit 6 is output to the MC circuit 10. In the MC circuit 10, the output from the quantization circuit 6 is inversely quantized to perform an inverse discrete cosine transform (IDCT). Then, a motion compensation prediction process is performed, and a data and a prediction block to be subtracted from the input block by the subtractor 4 are generated.

[0016]

In such processing, it is necessary to strictly control the code amount of the buffer memory, and the capacity of the buffer memory cannot be fully utilized. Further, when the encoding process is performed over a plurality of frames or a plurality of fields, the amount of information suddenly increases due to a scene change or the like, and the generated code amount overflows the predetermined code amount. In this case, the overflowed code word cannot be transmitted or stored and is truncated. No consideration is given to how the reproduced image is affected by the truncated codeword.

For example, if data for a plurality of blocks has been truncated, the data for the plurality of blocks does not exist during reproduction, and the block cannot be reproduced.
It is necessary to correct it by interpolation from surrounding blocks.

In view of the above, in the present invention, when the generated code amount overflows the predetermined code amount, the transmission rate is maintained by truncating codes having little effect on the reproduced image, and the buffer memory can be fully utilized. It is an object to provide a code amount control device.

[0019]

According to the present invention, an address memory provided when a code word to be stored is recorded in the buffer memory and its code word length are recorded in an address memory provided separately from the buffer memory. When the code amount in the buffer memory exceeds the predetermined code amount, the code word immediately before the EOB code generated in the block is deleted by referring to the address memory. By doing so, the overflow from the predetermined code amount of the buffer memory caused by the imperfect code amount control is eliminated.

[0020]

According to the present invention, the generated variable-length code word is stored in a buffer memory, and the address of the stored code word in the buffer memory and the code word length are recorded in an address memory provided separately from the buffer memory. I do. When the code amount stored in the buffer memory exceeds the predetermined code amount of the buffer memory, the address memory is referred to,
The codeword immediately before the EOB code in the block is deleted.
By deleting codewords in this way, it is possible to eliminate overflow from the default code amount of the buffer memory, which is caused by imperfect code amount control. Since the code word deleted at this time is a code immediately before the EOB code generated in the block, it is considered to be a high-frequency component in the recorded data. When a component or a low-frequency component is missing, there is no serious visual effect such as appears in a reproduced image.

[0021]

[Embodiment 1] FIG. 1 shows a configuration diagram of the present embodiment. Reference numerals 1 to 7, 9, and 10 are the same as those in the conventional drawings. 20 is VLC
An address memory for storing the address of the buffer memory I22 storing the codeword immediately before the EOB code among the generated codewords generated by the circuit 7, and the codeword length. A CTL 21 detects how much the generated code amount exceeds the predetermined code amount in the buffer memory I22, and controls the address memory 20 so as to remove only the excess code amount.
Circuit. Reference numeral 22 denotes a buffer memory I for storing the VLC code from the VLC circuit 7. 23 is buffer memory I
A buffer memory II for storing the VLC code output from 22.

FIG. 3 is a block diagram showing a configuration example of the address memory 20 shown in FIG. Numeral 31 denotes an address adder I for incrementing the address of the memory, and numeral 32 denotes an address adder II for incrementing the data to be recorded in the memory so as to indicate the address of the buffer memory I. 33
Is a memory for recording the address from the address adder II and the VLC code length from the VLC circuit 7 at the address indicated by the address adder I31. Reference numeral 34 denotes a gate circuit that opens a gate for each code amount control unit and transmits data to the CTL circuit.

FIG. 4 is a block diagram showing a configuration example of the CTL circuit 21 shown in FIG. Reference numeral 40 denotes a subtracter for subtracting an address predetermined value indicating a predetermined code amount of the buffer memory I from data input through a gate of the address memory circuit. 41 is a comparison circuit I for detecting whether or not an overflow has occurred in the buffer memory I based on the result of the subtractor.
Is an adder that accumulates the number of bits deleted from the data in the buffer memory I. 43 compares the number of bits that have been deleted with the number of bits that overflow, and selects whether to delete the data in the buffer memory I or not. This is a comparison circuit II to be performed.

Next, the operation of FIG. 1 will be described. The output of the quantization circuit 6 is input to the VLC circuit 7 to generate a VLC code based on each data. The VLC circuit 7 outputs the VLC code (generated code word) to the buffer memory I22, and outputs the length of the generated code word to the address memory 20. For example, if the VLC circuit generates a code “1011” as a VLC code, the VLC code “1011” is used as a generated code word in the buffer memory I.
22 and outputs the length “4” of the VLC code “1011” to the address memory 20 as a generated codeword length. When the EOB code is transmitted from the VLC circuit 7 to the buffer memory I22, an EOB code detection signal is transmitted to the address memory 20.

The address memory 20 has one address per block.
It has one address storage area and a code word length storage area, and stores the head address of the code word (VLC code) recorded in the buffer memory I22 and the length of the code word (VLC code). However, since each processing block has only one pair of storage areas, the latest codeword is stored for a codeword generated in the same block. Therefore, the area storing the address and the code word length is overwritten one after another as long as the code word is generated from the same block.

At the end of the block processing, the EOB code is always output from the VLC circuit 7. When the EOB code is output, the address memory 20 stores the address and the code word length stored immediately before the generation of the EOB code in the data of the block. And a new address storage area and a code word length storage area are prepared for the next block processing, and the same processing as described above is repeated.

With respect to the address memory 20 shown in FIG.
The operation will be described. EO sent from VLC circuit
The B code detection signal is input to the address adder I31 to generate an address of the memory 33 in the address memory. In this case, each time the EOB code detection signal comes, the address of the memory 33 is updated. Therefore, one storage area is allocated to the memory 33 for each processing block. As long as the codewords in the same block continue to be processed, only one storage area is allocated, so that they are overwritten one after another.

The codeword length (VLC code length) sent from the VLC circuit 7 is input to the address adder II32, and the data corresponding to a pair with the address where each codeword is stored in the buffer memory I22. Is generated.
Here, the data means, for example, each V of the buffer memory I.
The LC code is each head address to be written. The start address and the code word length recorded from the address are regarded as one data, and the address adder I31 of the memory 33 is used.
Is stored at the address indicated by.

The output of the address adder II32 is sent to the gate circuit 34. The gate circuit 34 is provided for each unit for performing the code amount control, that is, for every 30 blocks when performing the code amount control for every 30 blocks, and for each field when performing the code amount control for each field. The output of the address adder II32 is sent to the CTL circuit 21. Therefore, the CTL circuit 21
The output of the address adder II32, for example, the address at which the buffer memory I stores the next codeword, is sent when the unit for controlling the code amount ends. However, since the code amount control unit has been completed, this address has a one-to-one correspondence with the generated code amount in the buffer memory I.
Therefore, the data sent to the CTL circuit 21 through the gate circuit 34 indicates the generated code amount.

The memory 33 stores the codeword length and the output of the address adder II32 at the address indicated by the address adder 31. When a signal indicating that the code amount in the buffer memory I overflows from the predetermined code amount is sent from the CTL circuit 21, the stored data is sent to the buffer memory I22 and the CTL circuit 21.

The address memory 20 has a buffer memory I
EOB in the block of the codeword stored in 22
The data corresponding to the address where the code word generated immediately before the code is stored, and the length of the code word stored from the address are output. The CTL circuit 21 outputs only the code word length.

The buffer memory I22 has more memory than the amount of memory corresponding to the transmission rate, and performs the same code amount control as in the conventional example with the memory amount corresponding to the transmission rate as a default value. However, after the processing unit ends, the buffer memory I22
When the generated code amount overflows the predetermined code amount defined in the above, the CTL circuit 21 sends the address memory 20
To inform the buffer memory I22 that an overflow has occurred.

FIG. 4 illustrates the operation of the CTL circuit 21 shown in FIG. The data input through the gate circuit 34 in the address memory 20, that is, the buffer memory I22
The data corresponding to the generated code amount in the memory 1 in a one-to-one correspondence with a default value indicating the default code amount of the buffer memory I22 and a subtractor.
It is input to 40 and subtracted. The result is a comparison circuit I41
When the default value is larger than the data from the address memory 20, the buffer memory I22 determines that the predetermined code amount has not overflown, ends a series of operations, and terminates the buffer memory I22. The data is sent to the buffer memory II23 as it is and output from the output terminal 9.

However, when the data from the address memory 20 is larger than the predetermined value, the amount of generated code in the buffer memory I22 is smaller than the predetermined code amount in the buffer memory I22 with respect to the address memory 20 and the buffer memory I22. Is transmitted to notify that overflow has occurred. Next, the CTL circuit 21 receives the codeword length of the codeword to be deleted in the buffer memory I22 from the address memory 20. This codeword length is input to the adder 42 and is added.

The output of the subtractor 40, that is, the number of bits in which the generated code amount in the buffer memory I22 overflows from the predetermined code amount, is compared with the total bit number of the codeword to be deleted from the buffer memory I22. It is sequentially monitored whether the generated code amount in the memory I22 overflows from the predetermined code amount. When the overflow state is resolved, the series of operations is terminated, the deletion of the codeword in the buffer memory I22 is stopped, and the data in the buffer memory I22 is sent to the buffer memory II23. At this time, the codeword of the address designated to be deleted from the address memory 20 is not transmitted.

In this manner, the buffer memory II23 stores the codewords within the predetermined code amount in the buffer memory I22 from which an arbitrary number of codewords have been deleted from the buffer memory I22.

By performing such control, the code word that has occurred last in the block is removed, and overflow from the predetermined code amount in the buffer memory I22 is eliminated.

Therefore, when a block having data in a block as shown in FIG. 11 is removed from the VLC code by the above-described method, if the block is to be reproduced, the block is replaced with DCT coefficients as shown in FIG. And inverse DCT.

In FIG. 2, compared to FIG. 11, data close to high-frequency components has been lost. Therefore, although the reproduced image quality is deteriorated, the data of all the blocks in the screen is held in the buffer memory II23, and the data of all the blocks in the image can be transmitted and accumulated.

Embodiment 2 FIG. In the first embodiment, the block for removing the code word is not selected when the generated code word amount overflows the predetermined code word amount in the buffer memory. However, in the second embodiment, the generated code word amount is not stored in the buffer memory. When the amount of codewords overflows, the blocks located at the left and right ends or the upper and lower ends forming the image are removed from the codewords that occurred last in the blocks.

Embodiment 2 will be described with reference to FIG. 1 to 10 are the same as in the conventional example. Also, 20, 21, and 22 are the first embodiment.
Is the same as Reference numeral 30 denotes a shuffling memory for performing shuffling in block units.

Next, the operation of the second embodiment will be described. The data in block units from the quantization circuit 6 is stored in the shuffling memory 30 for shuffling. In the output from the shuffling memory 30, data of a block near the center in the image configuration and data of a block including the upper end point of the image are divided in time series and read.

FIGS. 6 and 7 show the state. FIG. 6 shows that one frame or one field is divided into an area A including a block near the center of the screen and an area B including a block at the edge of the screen. Shuffling is performed in each area, and an edge is read at the beginning of reading. Blocks (region B), blocks near the center near the end of reading (region A), etc. are extracted and apparently encoded with a screen configuration as shown in FIG. The reading order may be reversed.

The read blocks are arranged in the order of VLC.
A VLC code (code word) is generated in a circuit 7, and thereafter, a buffer memory I22, an address memory 20, a CTL circuit 2
1. The buffer memory II23 operates in the same manner as in the first embodiment.

By performing the shuffling process in this manner, when the generated code amount overflows the predetermined code amount in the buffer memory I22, a block generated at the end of the screen which is hard to be seen by humans is generated in the block. By removing the last code word, it is possible to prevent the image quality from deteriorating at the center of the screen and eliminate the overflow from the predetermined code amount in the buffer memory due to the sudden occurrence of the code amount.

Embodiment 3 FIG. In the first and second embodiments, one code word and the code word length are recorded as one pair for one block in the address memory. However, a plurality of code words and the storage area of the code word length are stored for one block. It is also possible to prepare and remove multiple codewords per block.

Embodiment 4 FIG. In the first and second embodiments, the luminance signal and the chrominance signal are not distinguished. However, when the total generated code amount of the luminance signal and the chrominance signal exceeds the predetermined code amount in the buffer memory, the chrominance signal is not changed. The codeword immediately before the EOB code of the block is deleted in order, and if the overflow state continues, the EO of the luminance signal block is deleted.
The codeword immediately before the B code is deleted.

[0048]

Since the present invention is configured as described above, it has the following effects.

According to the present invention, when the length of a code word such as variable-length coding differs depending on the processing block and is not constant, even if the generated code amount overflows the predetermined code amount in the buffer memory, the size of the block in the image is reduced. Since data can be transmitted and stored, blocks that cannot be reproduced do not occur, and blocks on the entire screen can be reproduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a reproduced DCT block when the processing of the present invention is performed.

FIG. 3 is a block diagram showing one embodiment of an address memory circuit of the present invention.

FIG. 4 is a block diagram showing one embodiment of a CTL circuit of the present invention.

FIG. 5 is a block diagram showing one embodiment of the present invention.

FIG. 6 is a diagram showing a configuration of an area before shuffling in one frame or one field.

FIG. 7 is a diagram showing a configuration of an area after shuffling in one frame or one field.

FIG. 8 is a block diagram showing a conventional encoding device.

FIG. 9 is a diagram showing a sequence in a block after DCT.

FIG. 10 is a diagram showing an example of a variable length code.

FIG. 11 is a diagram showing an example of DCT coefficients in a block after DCT.

FIG. 12 is a diagram showing one method of code amount control;

[Explanation of symbols]

 7 VLC circuit 20 Address memory 21 CTL circuit 22 Buffer memory I 23 Buffer memory II

────────────────────────────────────────────────── (5) References JP-A-3-192878 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N ⁷ /24-7/68 H04N 11 / 04 H04N 1/41-1/419

Claims (3)

(57) [Claims] 1. A dividing a digitized video signal into blocks of a predetermined size, a device for encoding or less already definite amount by using the variable length coding for each block, the <br / > a buffer memory for storing the generated codeword generated by variable length coding, the written in the buffer memory
Address of generated code word immediately before EOB code of block
Comprising a luer dress memory to store pre-generated code word length, if the generated code amount is larger than the predetermined code amount by referring to the address memory, the EOB code straight
A high-efficiency coding apparatus characterized by deleting a previous generated codeword. 2. A high-efficiency encoding apparatus according to claim 1, wherein a block from which the generated code word according to claim 1 is deleted is selected in the order of a chrominance signal block and a luminance signal block. 3. A high-efficiency coding apparatus according to claim 1, wherein the blocks from which the generated code word is to be deleted are selected in the order of blocks at the upper, lower, left and right ends of the image, and then at the center block of the image. .