JP3208604B2 - Thin film transistor and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and a method for manufacturing the same.

[0002]

2. Description of the Related Art Thin film transistors, particularly, for example, thin film transistors having a polysilicon active layer, have begun to be used in liquid crystal display devices, static random access memories (SRAMs), and the like, and their technical importance has increased in recent years.

A polysilicon thin film transistor (hereinafter sometimes simply referred to as a TFT) has undesirable characteristics of a small on-current and a large off-current due to the influence of traps existing on the grain boundary of polysilicon. Improvement is desired.

[0004] In particular, in consideration of application to an SRAM, it is very important to reduce the off current, that is, the leak current of the TFT, in order to keep the data holding current small.

[0005] Conventionally, the leak current of a TFT is considered to be mainly a tunnel current via a grain boundary trap as described in the IEICE technical report SDM90-141 (Kato, 1990). Efforts have been made to reduce this grain boundary trap. For this purpose, for example, a method of enlarging the grain to substantially reduce the number of grain boundaries included in a single TFT, thereby reducing traps, or utilizing hydrogen contained in plasma SiN And a method of inactivating the traps.

However, even with these methods, it cannot be said that satisfactory characteristics have yet been obtained, and the guideline for improving the characteristics is not clear at present. .

[0007]

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems, to provide a thin film transistor having good characteristics by reducing a leak current, and to provide a method of manufacturing a thin film transistor capable of obtaining such a thin film transistor. The purpose is to provide.

[0008]

Means for Solving the Problems and Functions The present inventors have paid particular attention to the cause of the leakage current of the TFT, and have conducted intensive analysis and examination. As a result, the above-mentioned objects have been achieved by each invention of the present application. I found something.

That is, the invention of claim 1 of the present application provides a gate
Thin film with active polysilicon layer formed on insulating film
In the transistor, the front surface and the back surface of the polysilicon layer
Surfaces and side surfaces are formed by oxidation of the polysilicon layer
Characterized by covered silicon dioxide
A thin film transistor , which achieves the above object.

[0010] The invention of claim 2 of the present application provides a gate insulating film.
A thin-film transistor with a polysilicon layer serving as an active layer
In the transistor, the polysilicon layer includes a source drain.
Having an in region, a front surface, a back surface, and
Side surfaces formed by oxidation of the polysilicon layer
Thin film transistor characterized by being covered with silicon dioxide
A transistor , which achieves the above object.

[0011] The invention according to claim 3 of the present application is based on a semiconductor substrate.
The gate electrode, gate insulating film, and polysilicon
In a thin film transistor in which a capacitor layer is sequentially formed,
The front, back and side surfaces of the polysilicon layer are
Covered with silicon dioxide formed by oxidation of the
A thin film transistor characterized by having achieved the above object.

According to a fourth aspect of the present invention, a gate insulating film is provided.
The width of the channel region of the thin film transistor is 1 μm or less.
Formed polysilicon layer patterned below
And by thermally oxidizing the polysilicon layer,
The front, back and side surfaces of the polysilicon layer are made of silicon dioxide.
A method of manufacturing a thin film transistor characterized by covering with a thin film , thereby achieving the above object. Book
The invention of claim 5 of the application is to provide a thin film transistor on a gate insulating film.
The size should be at least 1/5 of the channel length (L) of the transistor.
1/3 or more of the channel width (W) of the thin film transistor
Forming a polysilicon layer having a grain size of
By thermally oxidizing the polysilicon layer, the polysilicon
Cover the top, back and sides of the silicon layer with silicon dioxide
A method for manufacturing a thin film transistor, comprising:
This achieves the above object.

The operation of the present invention will be described below with the background of the present invention. First, the analysis of the leak current will be described.

FIG. 1 is a schematic sectional view showing a structural example of a TFT according to the present invention. The TFT illustrated in FIG.
3 is a thin film transistor having an active layer of an element formed thereon (FIG. 1)
Reference numeral 14 denotes a policy to be an active layer in this structural example.
In the figure, an interface state density existing at the interface between the polysilicon layer 14 and the insulating film 13 is 1 × 10 11 /
cm2 or less.

In the structural example shown in FIG. 1, a gate electrode 1 is formed on an upper surface of a substrate 11 having at least an insulating surface.
2, the substrate 11 is made of, for example, a silicon oxide substrate, and the gate electrode 12 is made of, for example, polycrystalline silicon doped with a p-type impurity. In addition, a gate insulating film 13 made of a silicon oxide film is formed so as to cover the gate electrode 12. On the gate insulating film 13, a polysilicon layer 14 to be an active layer of the thin film transistor 10 to be formed is formed. On the surface of the polysilicon layer 14, the silicon dioxide film 1 is formed.
5 are formed. The gate electrode 12 on both sides of the gate electrode 12
The polysilicon layer 14 includes source / drain regions 16,
17 are formed. Source / drain region 1
The polysilicon layer 14 between 6 and 17 becomes the channel region 18. With this configuration, the thin film transistor 10 is formed.

FIG. 2 shows the leakage current characteristics of such a PMOS TFT. The horizontal axis is the drain voltage Vd, the vertical axis is the drain current Id, and the gate voltage is 0V. Therefore, the drain current indicates the leak current of the TFT. FIG.
As a result of detailed examination of the characteristics shown in the above, the present inventors have obtained the following new findings.

(1) The absolute value of the drain voltage Vd is 0.3
Below V, there is a relationship between Id and Vd, Id∝Vd, which indicates that Id is a generated recombination current based on the classic Shockley-Read-Hall model.

(2) In a region where | Vd | is about 0.3 to 3 V, Id is an electric field acceleration type (field enhancement type) generated current.

(3) When | Vd | becomes 3 V or more, a band-to-band tunnel type leak current starts to appear. At 6 V or more, this component becomes a main component of the leak.

Further, it is known that the above (2) is theoretically expressed as I _FE = I ₀ exp (α√E). Here, I _FE is an electric field acceleration type generated current, I ₀ is a low electric field, that is, a generated current corresponding to the above (1), α is a coefficient related to a material constant, and E is an electric field intensity. Therefore, it can be seen that it is necessary to reduce I ₀ in order to suppress the leak currents (1) and (2).

According to the Shockley-Lead-Hole model, carrier generation speed (amount corresponding to leak current)
Is It is expressed as Where A is a constant determined by the substance, Nt
Is the trap density or generated recombination center density, Et is the energy level of the trap, Ei is the intrinsic energy level, k is the Boltzmann constant, and T is the absolute temperature. From this relationship, it can be seen that Nt must be reduced in order to reduce U.

Considering Nt, Nt can be expressed as Nt = Nb · t _poly + Nsf + Nsb. Here, Nb is the trap volume density of the polysilicon layer, t _poly is the thickness of the polysilicon layer, Ns
b and Nsf indicate the interface state densities at the back and front of the polysilicon, respectively. FIG. 3 schematically shows this state, in which the vicinity of the drain of the TFT is shown.

As shown in FIG. 3, near the end of the drain region 17 of the TFT, a depletion layer 40 extends toward the channel region 18, and a leak current occurs in the depletion layer.

Although a Si bulk trap (corresponding to Nb) has mainly been considered as a center of generation of a leak current in the depletion layer, the interface state densities Nsf and Nsb are also considered to be important generation centers. Can be

It is well known that the interface state density between Si and an oxide film varies depending on the method of forming the interface.
Is the smallest when directly thermally oxidized, approximately 10 ¹⁰ / cm
^{About 2} . On the other hand, SiO _{2 is} deposited on Si by CVD or the like.
In the case where is formed, although it depends on the conditions, 10 ¹² / cm ²
Generally, the value is of the order of magnitude.

Conventionally, when a TFT is formed, a method of forming a Si layer on SiO ₂ by a CVD method or the like is employed, and the interface state density here is 10 ¹² / cm ² (10
^-12 / cm ² or slightly smaller. The same in the present specification). This was an unavoidable problem as long as a general process was used. This is because it is difficult to lower the interface state density of the lower surface (interface side) of the deposited Si layer by thermal oxidation or the like.

On the other hand, since it is easy to oxidize the surface of the deposited Si layer, Nsb can be easily reduced in FIG. On the other hand, Nsf is usually about 10 ¹² / cm ² .

The trap density in the bulk, although various analyzes have been attempted so far, which is also substantially to 10 ¹² / cm
It is considered to be about ² (Nb × t _poly ) or less.

In order to investigate the influence of the interface state density, a polysilicon active layer prepared by thermally oxidizing both sides, a single side oxidized only, or a non-oxidized side is prepared.
_NT was determined from the analysis of the generated current in the low electric field region.

As a result, the result was 2.5 × 10 ¹² / cm ² single-sided oxidation 9 × 10 ¹¹ / cm ² double-sided oxidation 1 × 10 ¹⁰ / cm ² without oxidation. According to the results of transmission electron microscope observation, it is not recognized that the grains of the polysilicon are particularly affected by the oxidation, and Nb is almost constant.

As is apparent from these results, reducing the interface state density by oxidation has a direct effect on remarkably reducing _NT . Therefore, this gives TF
T leakage current can be reduced.

The present invention has been made as a result of detailed studies as described above. In particular, in order to reduce the leak current, it is very important to keep the interface state density of the TFT low as described above. It was completed as a result of finding it important.

[0033]

Embodiments of the present invention will be described below with reference to the drawings. However, needless to say, the present invention is not limited to the embodiments described below.

Embodiment 1 FIGS. 4A and 4B are cross-sectional views showing the structure of a TFT according to the present embodiment. FIG. 4A is a cross-sectional view in a direction parallel to a channel, and FIG.

The TFT of this embodiment has a gate insulating film of 13
And 13 '. Insulation film 1
3 'is formed by oxidation of the channel region of the TFT.

That is, the TFT of the present embodiment has a gate insulating film
A thin-film transistor with a polysilicon layer serving as an active layer
In a transistor, the front, back and side surfaces of the polysilicon layer
Is formed by oxidation of the polysilicon layer.
It is covered with silicon .

Next, a method of manufacturing the thin film transistor 10 of this embodiment will be described with reference to FIGS. 5A and 5B showing a manufacturing process (No. 1) and FIGS.

First, the first step shown in FIG. 5A is performed. In this step, for example, a silicon oxide substrate is used as the substrate 11 having at least a surface having an insulating property.

Chemical vapor deposition (hereinafter referred to as CVD)
As a result, the polycrystalline silicon film 21
Is formed to a thickness of, for example, 50 nm. Thereafter, portions of the polycrystalline silicon film 21 shown by two-dot chain lines in FIG. 5A are removed by ordinary photolithography and etching to form polycrystalline silicon patterns 22, 23, and 24.

Subsequently, as shown in FIG. 5B, the polycrystalline silicon patterns 22 to 2 are formed by, for example, ion implantation.
4 is introduced with boron difluoride (BF ₂ ⁺ ). As the ion implantation conditions at this time, for example, the ion implantation energy is set to 20 keV and the dose is set to 1 × 10 ¹⁵ / cm ² . Then, the gate electrode 12 is formed by converting the polycrystalline silicon pattern 22 into a p-type. In the same way as above,
The polycrystalline silicon patterns 23 and 24 are made p-type, and p ⁺ source / drain extraction electrodes 25 and 26 are formed.

Next, a silicon oxide film having a thickness of, for example, 35 nm is formed on the surface of the gate electrode 12 and the surfaces of the p ⁺ source / drain extraction electrodes 25 and 26 by, for example, a low pressure CVD method using silane as a reaction gas. Formed. In order to further improve the insulating property, dry oxidation at 850 ° C. is performed to further increase the thickness of the silicon oxide film to about 5 nm. Therefore, a silicon oxide film 27 having a thickness of 40 nm is formed. The silicon oxide film 27 on the gate electrode 12 becomes the gate insulating film 13.

Thereafter, the silicon oxide film 27 on the p ⁺ source / drain extraction electrodes 25, 26 is partially removed by ordinary photolithography and etching to form contact holes 28, 29. As a result, FIG.
(B) structure is obtained.

Next, the second step is performed. In this step,
As shown in FIG. 5C, the inside of the contact holes 28 and 29 and the gate insulating film 1 are formed by low-pressure CVD.
An amorphous silicon film 30 is formed on the surface of the silicon oxide film 27 and the surface of the silicon oxide film 27 to a thickness of, for example, 30 nm. As the film forming conditions, for example, the film forming temperature is set to 450 ° C., and the pressure of the film forming atmosphere is set to 0.67 kPa.

Thereafter, an annealing process (low-temperature solid-phase crystallization process) at 600 ° C. for 30 hours is performed to crystallize the amorphous silicon film 30 and form the polysilicon layer 14. this
The crystal grain size of the polysilicon layer 14 is, for example, about 2 μm.

Next, as shown in FIG. 6D, the above-mentioned policy is performed by ordinary photolithography and etching.
Removing the portion indicated by two-dot chain line in silicon layer 14, the remainder of the port
The active region forming part 19 is formed by the silicon layer 14.

Thereafter, the third step is performed. In this step,
First, as shown in FIG. 6E, dry oxidation at 850 ° C. is performed to oxidize the active region forming portion 19,
A silicon oxide film 15 having a thickness of 20 nm is formed. Therefore, due to this oxidation, the film thickness of the active region forming portion 19 becomes 1
0 nm to 20 nm. Here, dry oxidation is used, but oxidation may be performed by, for example, wet oxidation.

By this oxidation, oxygen diffuses in the gate oxide film 13 and oxidizes the lower surface of the channel polysilicon. As shown in FIG. 6E, the second gate oxide film 13 '
Is formed. The oxidation of the lower surface is determined by the correlation between the initial thickness of the gate oxide film, the amount of oxidation of the active layer, and the width of the active layer. If the width of the active layer is 1 μm or less, the interface state is almost the same under the above conditions. Oxidation sufficient to reduce

If the thickness of the active region forming portion 19 is too small (for example, if it is set to about 5 nm or less),
Since the ON resistance becomes very large, the ON current becomes very difficult to flow. For this reason, the ON / OFF ratio is significantly reduced. Therefore, the active region forming portion 19 made of the polysilicon layer 14 is finally formed to a thickness of, for example, about 10 nm.

Next, as shown in FIG. 6F, source / drain regions 16 and 17 are formed in the active region forming portion 19 on both sides of the gate electrode 12. Source / drain region 1
To form 6 and 17, first, an ion implantation mask (not shown) is formed on the gate electrode 12 by ordinary photolithography. Thereafter, the source / drain regions 16 and 17 are formed by introducing, for example, a p-type impurity into the active region forming portion 19 by a normal ion implantation method. As the ion implantation conditions, for example, boron difluoride (BF ₂ ⁺ ) is used as a p-type impurity, and the ion implantation energy is 1
0 keV, dose amount 1 × 10 ¹⁴ / cm ^{2 to} 5 × 10 ¹⁴
/ Cm ² . The source / drain regions 16,
The active region forming portion 19 between the 17 becomes the channel region 18.

Thereafter, a wiring step is performed as shown in FIG. In the wiring step, first, as shown in FIG. 7A, an interlayer insulating film 31 is formed on the entire surface on the silicon oxide film 15 side by, for example, a CVD method. This interlayer insulating film 31 is made of, for example, silicon oxide.

Next, the source / drain extraction electrodes 25, 25 are formed by ordinary photolithography and etching.
Contact holes 32 and 33 are formed in interlayer insulating film 31 and silicon oxide film 27 on 26.

Subsequently, boron difluoride (BF ₂ ⁺ ) is ion-implanted over the entire surface by, for example, an ion implantation method.
A rapid thermal annealing (RTA) process for 10 seconds in a temperature atmosphere of 050 ° C.
Activate 17.

Next, as shown in FIG. 7B, for example, a metal film 34 for wiring is formed on the inside of the contact holes 32 and 33 and the surface of the interlayer insulating film 31 by sputtering.
To form The wiring metal film 34 is formed of, for example, aluminum or an aluminum alloy.

Subsequently, the portion of the wiring metal film 34 indicated by the two-dot chain line is removed by ordinary photolithography and etching, and the p ⁺ source / drain extraction electrode 2 is removed.
Metal wirings 35, 36 connected to 5, 26 are formed.

Thereafter, as shown in FIG. 7C, for example, a plasma silicon nitride (p-SiN) film is formed as a passivation film 37 on the entire surface of the metal wirings 35 and 36 by, for example, a plasma CVD method. Further, the metal wirings 35 and 36 are sintered.

In the above manufacturing method, the thin film transistor 10
After forming a polysilicon layer 14 having a size of at least 1/5 of the channel length (L) of the above and a size of at least 1/3 of the channel width (W) of the thin film transistor 10,
The surface of the polysilicon layer 14 is oxidized, the policy
Since the thickness of the recon layer 14 is reduced, a polycrystalline silicon film 14 having a large grain size and a small thickness can be obtained.

Further, since the lower surface of the polysilicon layer 14 is also thermally oxidized, the interface state density can be sufficiently reduced.

By forming the active region forming portion 19 with the polysilicon layer 14, the TFT can be reduced in the off-state current, and the TFT having a large mobility and excellent characteristics can be realized.

FIG. 8 shows a PMOSTF formed by the above method.
The example of the characteristic of T is shown. The channel width W and channel length L of the TFT are 0.5 and 0.7 μm, respectively, and show a comparison between the case where the active layer is oxidized (indicated by I) and the case where the active layer is not oxidized (indicated by II). I have.

As is clear from FIG. 8, in the TFT in which the active layer is oxidized to reduce the interface state density, the off-state current (Vg = 0 V) can be reduced by two digits or more as shown in Graph I. . The switching characteristics are also steep.

FIG. 9 shows an example of the characteristics of two types of TFTs formed by the above method. In this case, W
= 10 µm (Graph Ia) and W = 0.5 µm (Graph Ib). When W = 10 µm, the off-current tends not to be sufficiently reduced as shown by Ia. is there. This is probably because the width of W was so large that the lower surface of the active layer was not sufficiently oxidized.

This is shown more systematically in FIG.
0. FIG. 10 shows the ON current and the OFF current of the TFT,
The graph shows the amount of oxidation of the polysilicon layer. The thickness of the polysilicon layer before oxidation is 30 nm, and the film thickness after being reduced by oxidation is shown in the lower part of the horizontal axis, and the oxidation amount is shown in the upper part.

Ion is the drain voltage and the gate voltage−
It is a value at 3.3V. Ioff is-
The values are at 3.3V and 0V.

As is evident from the above, when W = 10 μm, the decrease in Ioff is gradual with respect to the oxidation amount, and is not significantly improved. At W = 0.5 μm, Iof
f decreases greatly with oxidation. However, when the oxidation amount was too large (oxidized by 24 nm), the channel poly-Si partially disappeared, and the Ion was reduced and the variation was increased.

Considering the above results and the oxidation mechanism together, the following can be said.

The SiO 3 on the substrate 103 as shown in FIG.
_When oxidizing the polysilicon 101 formed on the silicon dioxide 102, the oxidation of the lower surface of the polysilicon 101 is performed using SiO ₂ 10
Since the oxygen diffused in 2 reaches the lower surface of the poly-Si layer 101, the oxidation proceeds more easily near the polysilicon pattern edge. As shown in FIG. 12, which shows the middle of the oxidation, the oxidation occurs in a wedge shape as generally known, and this wedge-shaped region 105 is called a bird's beak.
The structure after sufficient oxidation is shown in FIG.

Assuming that the length of the bird's beak is x (see FIG. 12), x is a function of the thickness t ₁₀₂ of the oxide film ₁₀₂ , the oxidation temperature, the oxidation time, and the like.

In order to obtain the effect of the present invention well, the length x of the bird's beak 105 should be １ ／ of the width W of the poly-Si active layer.
It is desirable that this is the case.

For example, when t ₁₀₂ is 35 nm, 800 ° C.
Is approximately 0.4 μm in the oxidation of (20 nm on Si substrate)
About. Therefore, W is about 0.8 μm or less. If t ₁₀₂ is 10 nm, x is 0.1
Since it is about μm, W = 0.2 μm.

Although t ₁₀₂ , oxidation conditions, and W are problems determined by the design of the device and the process, in an LSI process in which heat treatment at a high temperature for a long time is to be minimized,
In particular, it is desirable to reduce the width of W so that the lower surface of the poly-Si layer is oxidized with less oxidation.
It can be said that m or less is a practically used range.

Therefore, as shown in FIG. 10, although the TFT with W = 10 μm, which is much larger than x, does not sufficiently improve the characteristics, when W = 0.5 μm, the characteristics are greatly improved.

The effect of further reducing W is as follows.
Hydrogen that inactivates interface states and bulk traps is
It is conceivable that hydrogen is more easily diffused in SiO ₂ than in the inside, so that hydrogen having a smaller W becomes easier to reach in poly Si and the lower layer interface through the lower SiO ₂ . Therefore W
It is considered that in the case of a TFT having a small size, traps are more effectively inactivated by hydrogen.

[0073]

According to the present invention, it is possible to provide a thin film transistor having reduced leakage current and excellent characteristics, and a method for manufacturing the same.

[Brief description of the drawings]

FIG. 1 is a diagram for describing a configuration of the present invention, and is a schematic configuration cross-sectional view of a thin film transistor.

FIG. 2 is a diagram showing a leakage current characteristic (a relationship between a drain current and a leakage current).

FIG. 3 is a schematic explanatory diagram of an interface state density.

FIG. 4 is a cross-sectional view showing the TFT of Example 1.

FIG. 5 is a diagram illustrating a manufacturing process (part 1) of the TFT according to the first embodiment;

FIG. 6 is a diagram illustrating a manufacturing process (part 2) of the TFT according to the first embodiment;

FIG. 7 is a diagram illustrating a manufacturing process of the wiring according to the first embodiment.

FIG. 8 is a diagram illustrating a characteristic example of the TFT according to the first embodiment.

FIG. 9 is a diagram illustrating a characteristic example of the TFT according to the first embodiment.

FIG. 10 is a diagram showing the relationship between the amount of polysilicon oxidation and the on-current and off-current.

FIG. 11 is an explanatory diagram of an action of an oxidation mechanism.

FIG. 12 is an explanatory diagram of an action of an oxidation mechanism.

FIG. 13 is an explanatory diagram of an action of an oxidation mechanism.

[Explanation of symbols]

Reference Signs List 10 thin film transistor 13 insulating film (gate insulating film) 13 'silicon oxide formed by oxidation of active layer 14 polysilicon layer

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) H01L 29/786 H01L 21/316 H01L 21/336

Claims (5)

(57) [Claims] 1. A polysilicon, which becomes an active layer on a gate insulating film.
In the thin film transistor forming the emission layer, the surface of the polysilicon layer, a thin film transistor backside and side, characterized in that it is covered with silicon dioxide formed by oxidation of the polysilicon layer. 2. A polysilicon, which becomes an active layer on a gate insulating film.
In the thin film transistor forming the emission layer, wherein the polysilicon layer has a source-drain region, the surface of the polysilicon layer, the back surface and side, are covered with silicon dioxide formed by oxidation of said polysilicon layer A thin film transistor. 3. A gate electrode and a gate insulating film on a semiconductor substrate.
Film, the thin preparative <br/> transistor having a polysilicon layer serving as an active layer are sequentially formed, the surface of the polysilicon layer, the back surface and side, are covered with silicon dioxide formed by oxidation of said polysilicon layer A thin film transistor. 4. A thin film transistor thin film transistor on a gate insulating film.
Patterning so that the width of the channel region is 1 μm or less
Forming a polysilicon layer, and thermally oxidizing the polysilicon layer to form the polysilicon layer.
Silicon dioxide on the front, back and side of the silicon layer
A method for manufacturing a thin film transistor, comprising: 5. A thin film transistor thin film transistor on a gate insulating film.
The thickness of the thin film traverse is 1/5 or more of the channel length (L).
Grains with a size of 1/3 or more of the channel width (W) of transistor
Forming a polysilicon layer having a diameter, and thermally oxidizing the polysilicon layer to form the polysilicon layer.
Silicon dioxide on the front, back and side of the silicon layer
A method for manufacturing a thin film transistor, comprising: