JP3208790B2 - Video camera equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video camera device, and more particularly, to a video camera device having a plurality of camera heads and selectively connecting one of the plurality of camera heads to a camera body. The present invention relates to a video camera device.

[0002]

2. Description of the Related Art In a video camera device, for example, a camera head having an optical system and an image pickup device can be separated and detached from a camera body which performs signal processing for converting an image pickup output signal from the image pickup device into a video signal. There is something. By separating the camera head from the camera body in this way,
It is possible to attach a light camera head to various positions while leaving a heavy camera body.

In such a video camera apparatus capable of separating the camera body and the camera head, the camera body and the camera head usually have oscillators for generating clocks having the same frequency. The camera body forms a horizontal (H) and vertical (V) synchronization signal SYNC based on a clock of an oscillator in the camera body, and sends the synchronization signal SYNC to the camera head. In addition, the camera head, for example, based on a synchronization signal SYNC from the camera body and a clock of an oscillator in the camera head, for example, a charge-coupled device (CC)
D) and the like (horizontal drive pulse HD and vertical drive pulse VD) for the image pickup device.

By the way, in a video camera device in which the camera head can be separated as described above, for example, a plurality of camera heads are prepared, and the camera heads are arranged at different positions, so that the subject can be photographed from various angles. It is possible to do. In this case, the signal sent to the camera body is only a signal from one camera head selectively switched and connected among a plurality of camera heads.

[0005]

However, when a plurality of camera heads are used, the oscillator in each camera head is not limited to one that generates a clock having the same frequency as the oscillator in the camera body. May not be.

As described above, when the clocks of the oscillator in the camera body and the clock of the oscillator in the camera head are connected to each other, for example, a video signal and ground (GND) are caused by the different clocks. Different frequency components (clock components) will be loaded. In other words, the clock of the camera body and the clock of the camera head generate a so-called beat, and a stripe pattern appears on a reproduced screen. This beat is
This occurs because the frequencies of the clock of the camera body and the clock of the camera head are close to each other. In order to eliminate this beat, measures such as providing a shield or improving the area around the ground are usually taken. However, none of them is effective, and the beat cannot be completely eliminated.

Accordingly, the present invention has been proposed in view of the above-described circumstances. For example, a case where one camera head is selectively selected from a plurality of camera heads and connected to the camera body side However, an object of the present invention is to provide a video camera device that can be connected well without generating a beat.

[0008]

SUMMARY OF THE INVENTION A video camera apparatus according to the present invention has been proposed to achieve the above-mentioned object, and comprises a plurality of camera heads each operating with clocks of different frequencies, and a plurality of the camera heads. An output signal from any one of the camera heads selectively switched and connected from among the heads is supplied, the signal processing for converting the output signal from the camera head into a video signal is performed, and a synchronizing signal is formed to form the synchronization signal. A video camera device comprising: a camera body for sending to a head; wherein the plurality of camera heads each include identification information generating means for generating corresponding identification information; Identification information detecting means for detecting each identification information from the plurality of camera heads, and a clock corresponding to each clock frequency of the plurality of camera heads. A plurality of oscillators that generate a clock, and selectively operate any one of the plurality of oscillators in accordance with the identification information detection output detected by the identification information detection means. A synchronizing signal based on a clock from an oscillator is formed and sent to the camera head connected to the selection switching. Further, in the video camera device of the present invention, the identification information from the identification information generating means of the camera head is superimposed on an output signal sent from the camera head to the camera body.

[0009]

According to the video camera device of the present invention, the camera body has built-in means for detecting identification information corresponding to each camera head and an oscillator for generating a clock having a frequency corresponding to each camera head. In addition to recognizing which camera head the connected camera head is, an oscillator corresponding to the detected identification information is operated. The identification information is transmitted by being superimposed on an output signal from the camera head.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a video camera device according to the present invention will be described below with reference to the drawings. FIG. 1 is a block circuit diagram showing a schematic configuration of a video camera device according to an embodiment of the present invention. FIG. 1 shows an example of a video camera device applied to a so-called PAL system of a television broadcasting system.

The camera head 30 of the video camera apparatus shown in FIG. 1 has an image pickup device, a voltage controlled oscillator (VCO) 35 which is a clock generating means for generating a clock for operating the image pickup device, and identification information indicating itself. An identification information generating circuit 39 for generating a high-level or low-level DC component signal as an ID; A plurality of camera heads 30 are provided, and the clock frequencies of the VCOs 35 of the plurality of camera heads 30 are different from each other.

Further, the camera body 10 of the video camera apparatus of the present embodiment is provided with any one of the plurality of camera heads 30 selectively switched and connected.
Are transmitted, and signal processing for converting the output signal from the connected camera head 30 into a video signal is performed. Further, the camera body 10
Is the identification information I from the plurality of camera heads 30.
It comprises an identification information detection circuit 15 for detecting D, and a plurality of oscillators (22, 23) for generating clocks corresponding to the respective clock frequencies of the plurality of camera heads 30. In the camera body 10, the identification information ID corresponding to the camera head 30 sent from the selected camera head 30 is detected by the identification information detection circuit 15, and in response to the identification information detection output, Any one of the plurality of oscillators (22, 23)
The two oscillators are selectively operated to form horizontal (H) and vertical (V) synchronization signals SYNC based on the clocks from the selected oscillators, and send them to the camera head 30 selectively connected. I have.

Further, in the video camera apparatus according to the embodiment of the present invention, the identification information ID from the identification information generating circuit 39 is superimposed on the output signal from the camera head 30 (added by the adder 32). The output signal from the camera head 30 and the synchronization signal SYNC from the camera body 10 are transmitted via a transmission line (cable CV).

That is, in FIG. 1, the synchronization signal SYNC from the camera body 10 is supplied to the terminal 31 of the camera head 30 via the cable CV.
This synchronization signal SYNC is supplied to a separation circuit 33 that separates a horizontal component and a vertical component. In the separation circuit 33, only the horizontal component Hsep is separated from the synchronization signal SYNC.
The signal is sent to a phase comparison circuit 34 forming an LL (phase locked loop). In the phase comparison circuit 34,
Horizontal drive pulse HD from a synchronizing signal generation circuit 36 described later
Is compared with the phase of the horizontal component Hsep, and the output is transmitted to the VCO 35. The VCO 35 generates the clock for the camera head 30 based on the output of the phase comparison circuit 34. This clock has a different frequency for each of the plurality of camera heads.

The clock is, for example, a charge coupled device (C
CD) or the like, and is sent to a CCD drive circuit 37 for driving the image pickup device, and the synchronization signal generation circuit 36
Is supplied to the clock input terminal CL. In the synchronization signal generating circuit 36, based on the clock from the VCO 35, the driving pulse (horizontal driving pulse HD)
And a vertical drive pulse VD). These drive pulses HD and VD are also sent to the CCD drive circuit 37. A signal for driving the image sensor from the CCD drive circuit 37 is sent to the image sensor via a terminal 38.

In this embodiment, the case where two camera heads are used is taken as an example. For this reason, as the identification information IDs of the two camera heads, for example, as described above, two types of levels, that is, a high level and a low level of the DC component are used, and the two levels are used for the two levels. Each camera head is identified. That is, for example, a high-level signal of the identification signal ID is output from the identification information generating circuit 39 of one camera head (for example, the camera head 30a), and the other camera head (for example, the camera head 30b). The identification information generating circuit 39 outputs, for example, a low-level signal of the identification signal ID. The identification information ID from the identification information generating circuit 39 is sent to the adder 32. Note that this 2
In this embodiment using two video cameras, the VCO 35 of the camera head 30a outputs, for example, a clock of a frequency fx2 to the VC of the camera head 30b.
For example, a clock having a frequency fx1 is output from O35.

Although not shown, the adder 32 is also supplied with an imaging output signal from the imaging device. Therefore, in the adder 32, the identification information ID is added, that is, superimposed on the imaging output signal. The imaging output signal on which the identification information ID is superimposed is transmitted to the terminal 11 of the camera body 10 via the terminal 31 and the cable CV.

Among the signals supplied via the cable CV, the imaging output signal is sent to a signal processing circuit (not shown), and the signal processing circuit converts the imaging output signal into a video signal. Processing is performed.

The signal transmitted through the cable CV is
It is also sent to the identification information detection circuit 15. The identification information detection circuit 15 detects the identification information ID of the superimposed DC component from the signal. For example, the identification information I
If D is the high-level component, it is detected that the camera head 30 is the identification information ID from the one of the two camera heads 30a. That is, in the identification information detection circuit 15, the identification information ID
Is detected to be the high level, it is determined that the camera head connected to the camera body 10 via the cable CV is the camera head 30a. Also,
If the identification information ID is the low-level component, the identification information ID from the other camera head 30b
Is detected. That is, when the identification information ID is detected to be at the low level, the camera body 10
It is determined that the camera head connected via the cable CV is the camera head 30b. More specifically, the identification information detection circuit 15 uses the cable C
Only the identification information ID of the DC component is extracted from the signal passing through V, so that the output from the identification information detection circuit 15 is the DC component of the high level or the low level. The identification information detection outputs (high level, low level) are sent to an oscillating circuit (VCO) 20 having a plurality of oscillators for generating clocks corresponding to the respective clock frequencies of the plurality of camera heads.

Here, the oscillation circuit 20 of this embodiment is
As described above, since the clocks according to the clocks of the two camera heads 30a and 30b are oscillated, for example, two oscillators 22 and 23 are incorporated.
That is, the oscillation frequency of the oscillator 23 is the same as the clock frequency fx2 of the VCO 35 of the camera head 30a, and the oscillation frequency of the oscillator 22 is
The clock frequency is the same as the clock frequency fx1 of the VCO 35 of 0b. The oscillation circuit 20 includes an inverter 21
Is also built-in. The output of the identification information detection circuit 15 is supplied to the inverter 21. Therefore, when the output of the identification information detection circuit 15 is at the high level, the output of the inverter 21 is at the low level, and when a low level is input, the output of the inverter 21 is at the high level. Further, the input terminal of the inverter 21 and one end of the oscillator 22 are connected, and the output terminal of the inverter 21 and the oscillator 23
Are connected to one end. Furthermore, these oscillators 2
Numerals 2 and 23 start the oscillation operation at a high level. Therefore, the oscillator 22 operates when the input of the inverter 21 is at a high level, that is, when the identification information detection output indicates the connection between the camera head 30a and the camera body 10. Get started. Conversely, when the output of the inverter 21 is at a high level (input is at a low level), that is, when the identification information detection output indicates the connection between the camera head 30a and the camera body 10, It starts to operate.

The other ends of the oscillators 22 and 23 are commonly connected and connected to the clock input terminal CL of the synchronization signal generating circuit 12 of the camera body 10. The synchronizing signal generation circuit 12 generates the synchronizing signal SYNC based on the supplied clock. That is, the synchronization signal generation circuit 12 generates the synchronization signal SYNC based on a clock from one oscillator selected according to the identification information ID. The synchronizing signal SYNC generated by the synchronizing signal generation circuit 12 is transmitted to the camera head 30 via the capacitor C and further via the terminal 11 and the cable 31.

As described above, the camera body 10 of this embodiment can detect which camera head is connected and oscillates a clock having the same frequency as the clock frequency of the connected camera head. Only those oscillators that can do so can be operated. In other words, although the camera body 10 has a plurality of oscillators,
Since only one oscillator is operated, the clock output from the oscillation circuit 20 is not affected by the other oscillator. As described above, in the video camera apparatus of the present embodiment, the clock of the oscillation circuit 20 of the camera body 10 and the connected camera head 30
Since the clock frequency of the VCO 35 is the same, the above-mentioned beat does not occur. Further, in this embodiment, since the identification information ID is superimposed on the imaging output signal as described above, the identification information ID can be transmitted through the cable CV for transmitting the imaging output signal and the synchronization signal. There is no need to provide a separate transmission line for use. Of course, it is also possible to transmit only the identification information ID using another transmission line.

Since the video camera apparatus of this embodiment is applied to the PAL system as described above, the synchronization signal generating circuit 12 of the camera body 14 is provided with a high-precision oscillator 14. ing. The synchronizing signal generation circuit 12 also outputs an adjustment signal for finely adjusting the oscillation frequency of each of the oscillators 22 and 23 of the oscillation circuit 20. This adjustment signal is sent to the oscillation circuit 20 via a low-pass filter (LPF) 13. That is, the output of the LPF 13 is the voltage control signal Vcon for fine adjustment of the oscillation frequency in the oscillation circuit 20 in which the VCO is the VCO. Since the oscillation frequency of the oscillator 14 is farther from the oscillation frequencies of the oscillators 22 and 23 and the oscillation frequency of the VCO 35 in the camera head 30, there is almost no problem regarding the beat.

The video camera apparatus of the present invention is applicable not only to the above-described PAL system but also to the so-called NTSC system.

The video camera device of the present invention can be used with the NTSC
FIG. 2 shows a block circuit diagram of another embodiment applied to the system. In FIG. 2, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

That is, in the block diagram of FIG.
A voltage supply means 16 composed of a resistor or the like for supplying a predetermined voltage (for example, 2.5 V) is provided with a voltage control signal Vco for fine adjustment of the oscillation frequency in the oscillation circuit 20.
This is provided as a means for supplying n, so that the synchronization signal generating circuit 12 and the oscillation circuit 20 do not form a loop as shown in FIG. This is because the oscillation circuit 20 has higher accuracy than that for the PAL system. Further, the oscillator 14 is not required in the synchronization signal generating circuit 12. This figure 2
Of course, the NTSC video camera apparatus shown in FIG. 1 has the same effect as that of FIG.

Further, the synchronization signal generating circuit 12 shown in FIGS. 1 and 2 has, for example, a circuit configuration as shown in FIG. 3, for example. In FIG. 3, terminal 121
Is supplied with the clock from the oscillation circuit 20, the terminal 126 outputs the synchronization signal SYNC, and the terminal 1
27 is supplied with the identification information detection output. The output from the terminal 128 is the output signal to the LPF 13 in the example of FIG.

That is, in FIG.
Reference numeral 21 is connected to a switched terminal b of the changeover switch 122 and a switched terminal a of the changeover switch 124. Also,
The switched terminal a of the changeover switch 122 is opened,
The common terminal of the changeover switch 122 is connected to the input terminal of the clock counter 123. The output terminal of the clock counter 123 is connected to the switched terminal b of the changeover switch 124. These changeover switches 12
2, 124 are switched in accordance with the identification information detection output supplied via the terminal 127.
The common terminal of the changeover switch 124 is connected to a synchronization signal generation counter 125 for generating a synchronization signal. The synchronization signal generation counter 125 counts the clock supplied to the clock input terminal CL and outputs the synchronization signal SYNC. The above PA
When applied to the L system, this synchronization signal generation counter 1
25 is provided with the oscillator 14.

Here, it is assumed that, for example, the clock frequency fx1 of the oscillator 23 is higher than the clock frequency fx2 of the oscillator 22. In other words, it is assumed that the clock frequency at the camera head 30b is higher than the clock frequency at the camera head 30a.

In this case, when the identification information detection output is, for example, at a high level (when the camera head 30a is connected), the switch-over terminal a is selected for both the changeover switches 122 and 124. Therefore, the terminal 121
The clock from the oscillator 22 via the above is sent directly to the synchronization signal generation counter 125.

On the other hand, the identification information detection output is, for example, low level (when the camera head 30b is connected).
In this case, the terminal b to be switched is selected for both the changeover switches 122 and 124. Therefore, the clock from the oscillator 23 via the terminal 121 is sent to the clock counter 123 via the changeover switch 122. The clock counter 123 counts the number of supplied clocks and outputs a clock having the same frequency as the clock frequency fx2 of the oscillator 22. For this reason, the clock counter 12
3 is supplied to the clock input terminal CL of the synchronization signal generation counter 125 through the changeover switch 124, so that the synchronization signal SYNC can be obtained from the synchronization signal generation counter 125.

[0032]

As described above, in the video camera apparatus of the present invention, the identification information of each camera head is detected by the camera body, and any one of the plurality of oscillators is used in accordance with the identification information detection output. By selectively operating one oscillator to obtain a clock, forming a synchronization signal based on the clock, and sending it to the camera head, one camera head can be selectively selected from a plurality of camera heads. , The connection can be made well without generating a beat. Further, since the identification information is superimposed on the output signal of the camera head and sent, there is no need to provide a new transmission line for transmitting the identification information.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing a video camera device applied to a PAL system according to an embodiment of the present invention.

FIG. 2 is a block circuit diagram showing a video camera device applied to the NTSC system according to another embodiment of the present invention.

FIG. 3 is a block circuit diagram showing a specific configuration of a synchronization signal generation circuit on the camera body side of the present invention.

[Explanation of symbols]

 10 Camera body 12, 36 Synchronization signal generation circuit 15 Identification information detection circuit 20 Oscillation circuit 21 · Inverters 22, 23 ··· Oscillator 30 ··· Camera head 32 ····· Adder 33 ····· Separation circuit 34 ···· Phase comparison Circuit 35 VCO 37 CCD drive circuit 39 Identification information generation circuit

Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04N 5/222-5/253 H04N 5/04-5/073

Claims (2)

(57) [Claims] An output signal is supplied from a plurality of camera heads, each operating with a clock having a different frequency, and any one of the plurality of camera heads selectively switched between the plurality of camera heads. And a camera main body that performs signal processing for converting an output signal from the video signal into a video signal, forms a synchronization signal, and sends the synchronization signal to the camera head, wherein the plurality of camera heads correspond to each other. The camera body includes identification information detection means for detecting each piece of identification information from the plurality of camera heads, and a clock for each of the plurality of camera heads. A plurality of oscillators for generating a clock corresponding to a frequency, and One of the plurality of oscillators is selectively operated to form a synchronizing signal based on a clock from the selected oscillator, and to send the synchronizing signal to the camera head connected to the selection switching. Video camera device. 2. The video camera apparatus according to claim 1, wherein the identification information from the identification information generating means of the camera head is superimposed on an output signal sent from the camera head to the camera body. .