JP3208952B2 - Manufacturing method of high voltage transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a high breakdown voltage transistor having an offset drain structure and a gate electrode having a side wall.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional example of a method for manufacturing an N-channel high breakdown voltage transistor. In this conventional example, as shown in FIG. 2A, an SiO ₂ film 12 is selectively formed on the surface of a P-type Si substrate 11 to partition an element isolation region, and is surrounded by the SiO ₂ film 12. An SiO ₂ film 13 as a gate oxide film is formed on the surface of the element active region.

Then, a polycrystalline Si film 14 or a polycide film is deposited, and the polycrystalline Si film 14 and the like are patterned to form a gate electrode. Then, using the polycrystalline Si film 14 and the SiO ₂ film 12 as masks,
The impurity 15 of the mold is ion-implanted at a low concentration into the Si substrate 11 at an energy of about 50 keV.

Next, a SiO ₂ film 16 is deposited on the entire surface,
Performing RIE on the entire surface of the SiO ₂ film 16, as shown in FIG. 2 (b), to form the sidewall of SiO ₂ film 16 on the polycrystalline Si film 14.

[0005] Next, as shown in FIG.
A resist 17 having a pattern exposing a region where a source and a drain are to be formed on the surface of the first substrate is formed. Then, the resist 17, the polycrystalline Si film 14, and the SiO ₂
Using the films 12 and 16 as a mask, the N-type impurity 21 is
Ions are implanted into the substrate 11 at a high concentration.

Next, by performing a heat treatment, as shown in FIG. 2D, an N ^- diffusion layer 22 as an offset portion or the like is formed with the impurities 15, and N ^- diffusion layers 22 as a source and a drain are formed.
⁺ Diffusion layers 23 and 24 are formed with impurity 21. And
An interlayer insulating film such as a BPSG film 25 is formed on the entire surface.
As shown in (e), the BPSG film 25 is reflowed.

[0007]

However, polycrystalline Si
In general, RIE is performed on the SiO ₂ film 16 for forming the side wall of the film 14, but at this time, the amount of the Si substrate 11 dug is not stable. For this reason, the concentration profile of the impurity 15 already ion-implanted is not stable.

As a result, the impurity concentration profile of the N ⁻ diffusion layer 22 is not stable, and the drain current I _ds and the junction breakdown voltage BV _{ds of the} drain are not stable. That is, in the conventional example shown in FIG. 2, it was difficult to manufacture a high breakdown voltage transistor having stable characteristics.

[0009]

According to a first aspect of the present invention, there is provided a method of manufacturing a high withstand voltage transistor, comprising the steps of: forming a first impurity for forming offset portions between a gate electrode and a drain; Introducing the semiconductor substrate 11 into the semiconductor substrate 11 by using the gate electrode 14 as a mask;
6, a step of removing the introduction portion of the first impurity 15 in the semiconductor substrate 11 other than under the side wall 16 and a second impurity 26 for forming the offset portions 22 and 27. With the gate electrode 14
And introducing into the semiconductor substrate 11 using the side wall 16 as a mask.

According to a second aspect of the present invention, there is provided a method of manufacturing a high breakdown voltage transistor, wherein the second impurity is introduced at a higher concentration than the first impurity.

[0011]

According to the method of manufacturing a high breakdown voltage transistor of the first aspect, the offset portions 22 and 27 having a desired impurity concentration profile can be formed despite the formation of the side wall 16 on the gate electrode 14.

In the method of manufacturing a high-breakdown-voltage transistor according to the second aspect, the offset portions 22 and 27 and the drain 24 may have three levels of impurity concentration in the offset portions 22 and 27 and the drain 24, and may have a gentle concentration gradient. it can.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention applied to the manufacture of an N-channel high breakdown voltage transistor will be described below with reference to FIG. Components corresponding to those in the conventional example shown in FIG. 2 are denoted by the same reference numerals.

Also in this embodiment, the N-type impurity 15 is
Until ion implantation at a low concentration into the Si substrate 11 with energy of about eV and the SiO ₂ film 16 is deposited on the entire surface, FIG.
The steps substantially the same as those of the conventional example shown in FIG. However, in this embodiment, as shown in FIG.
At the time of RIE of the SiO ₂ film 16 for forming the side wall of the i film 14, over-etching is performed until the implanted portion of the impurity 15 in the Si substrate 11 other than under the side wall is removed.

Next, as shown in FIG. 1B, an N-type impurity 2 is formed by using a resist 17, a polycrystalline Si film 14, and SiO ₂ films 12 and 16 having the same pattern as in the conventional example as a mask.
1 is implanted into the Si substrate 11 at a high concentration.

Next, a heat treatment is performed to form an N ⁻ diffusion layer 22 as a part of the offset portion or the like under the SiO ₂ film 16 with the impurity 15 as shown in FIG. N ⁺ diffusion layers 23 and 24 as drains are formed with impurities 21. Then, an interlayer insulating film such as the BPSG film 25 is formed on the entire surface.

Next, as shown in FIG. 1D, an N-type impurity 26 is ion-implanted into the Si substrate 11 from the BPSG film 25 at an energy of about 100 keV. At this time, the energy of about 100 keV is applied to the BPSG film 2.
5 penetrates, but the polycrystalline Si film 14, the SiO ₂ film 12,
Numeral 16 denotes energy that does not penetrate. Thereafter, a heat treatment at a temperature of about 850 ° C. is performed, and as shown in FIG.
At the same time as the PSG film 25 is reflowed, an N ^* diffusion layer 27 as the remaining part of the offset portion is formed between the N ⁻ diffusion layer 22 and the N ⁺ diffusion layer 24 with the impurity 26.

Although the BPSG film 25 is used as the interlayer insulating film in the above embodiment, the PSG film and the P-SiN
Film, P-TEOS film, AsSG film, etc.
May be used instead of In the above embodiment, BP
Although the impurity 26 is ion-implanted after the SG film 25 is formed, the impurity 26 may be ion-implanted before the ion 21 is ion-implanted after forming the side wall with the SiO ₂ film 16.

[0019]

According to the method of manufacturing a high breakdown voltage transistor of the first aspect, since an offset portion having a desired impurity concentration profile can be formed, a high breakdown voltage transistor having stable characteristics can be manufactured.

According to the method of manufacturing a high-breakdown-voltage transistor according to the second aspect, since the offset portion and the drain having a gentle concentration gradient can be formed, a high-breakdown-voltage transistor having an extremely high junction withstand voltage at the drain can be manufactured.

[Brief description of the drawings]

FIG. 1 is a side sectional view showing an embodiment of the present invention in the order of steps.

FIG. 2 is a side sectional view showing a conventional example of the present invention in the order of steps.

[Explanation of symbols]

Reference Signs List 11 Si substrate 14 Polycrystalline Si film 15 Impurity 16 SiO ₂ film 22 N ⁻ diffusion layer 24 N ⁺ diffusion layer 26 Impurity 27 N ^* diffusion layer

Claims (2)

(57) [Claims] A step of introducing a first impurity for forming an offset portion between a gate electrode and a drain into a semiconductor substrate using the gate electrode as a mask; Removing a portion of the semiconductor substrate where the first impurity is introduced other than below the sidewall; and removing a second impurity for forming the offset portion using the gate electrode and the sidewall as a mask. And introducing the substrate into a substrate. 2. The method according to claim 1, wherein said second impurity is introduced at a higher concentration than said first impurity.