JP3209017B2 - Pseudo halftone processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel (PDP) and a liquid crystal display panel (LCD).
The present invention relates to a pseudo-halftone processing circuit in which a display device such as P) does not cause a deterioration in image quality even when the number of bits of a drive signal is reduced to increase light emission luminance.

[0002]

2. Description of the Related Art Recently, as a thin and lightweight display device, P
Attention has been paid to DP display devices. The drive system of this PDP display device is completely different from the conventional CRT drive system, and is a direct drive system using digitized video input signals. Therefore, the luminance gradation emitted from the panel surface is determined by the number of bits of the signal to be handled. PDPs are classified into two types, AC type and DC type, which have different basic characteristics. Among them, the AC type PDP has sufficient characteristics in terms of luminance and life, but for gradation display, it has a prototype level. Reported only up to 64 gradation display.
Recently, a 256-gray scale method using a separate address / display driving method (ADS subfield method) has been proposed.

[0003] This is because one frame has a relative luminance ratio of 1,
It consists of eight subfields of 2, 4, 8, 16, 32, 64, and 128, and 25 combinations of luminance of eight screens
Display of 6 gradations is performed. Each subfield includes an address period in which data for one refreshed screen is written, and a sustain period for determining a luminance level of the subfield. In the address period, first, wall charges are initially formed on each pixel at the same time for the entire screen, and then a sustain pulse is applied to the entire screen to perform display.
The brightness of the subfield is proportional to the number of sustain pulses and is set to a predetermined brightness. In this way, 256 gradation display is realized.

In the above-described AC driving method, as the number of gradations increases, the number of bits in an address period as a preparation period for lighting and emitting a panel within one frame period increases. The period becomes relatively short, and the maximum luminance decreases. In this way, if the number of bits of the signal to be handled is increased, the image quality is improved, but the light emission luminance is reduced. Conversely, if the number of bits of the signal to be handled is reduced, the light emission luminance is increased, but the gradation display is reduced, This leads to lower image quality.

The present applicant solves the above-mentioned problems and prevents the appearance of a pseudo pattern which is a regular repetitive pattern when the original pixel video signals are continuously input at the same level. An error diffusion circuit 28 of a pseudo-halftone display device to which an error detection circuit 35 as shown in FIG. 4 is added and a pseudo-random pulse generation circuit 52 is added has been proposed (Japanese Patent Application No. 5-288636). The error detecting circuit 35 outputs an error signal by calculating the difference between the setting data of the ROM 38 by the subtracting circuit 39 and the diffusion output signal from the horizontal direction adding circuit 32, and weights the weighted signals by the weighting circuits 40 and 41. And outputs an error load signal.

[0006] A diffusion output signal obtained by incorporating and diffusing an error by the vertical addition circuit 31 and the horizontal addition circuit 32 is sent to a bit conversion circuit 33, and the diffusion output signal quantized to n bits by the bit conversion circuit 33. Signal m
(≦ n−1) bits and output from the video output terminal 34 to P
Output to DP as drive signal. In this way, the original video input signal is diffused by incorporating errors, and a signal having a smaller number of bits than the original video input signal can obtain a smooth response without lowering the light emission luminance.

A pseudo-random pulse signal is generated by a pseudo-random pulse generation circuit 52, and a correction coefficient circuit 60
Is multiplied by ± k and added to the signal in the error diffusion circuit 28 by the correction addition circuit 50. Therefore, even if the levels of the input original pixel video signals are continuous and the same value, the display panel (for example, PDP) ) Does not have the same continuous value. Therefore, it is possible to prevent (suppress) the occurrence of a pseudo pattern on the display panel.

Here, a pseudo-random pulse generation circuit 52
When the consecutive number of “1” or “0” exceeds the set value, the correction amount monitoring circuit 56 of the correction amount control circuit 54 detects it, and the inversion circuit 58 outputs an inversion signal, The period in which the pseudo-random pulse signal appears continuously is shortened to reduce noticeable noise.

[0009]

However, for example, FIG.
As shown in (a), when "1" continues 20 times, the number of consecutive times is counted by the correction amount monitoring circuit 56, and when the value reaches a set value, for example, 4, the inversion circuit 58 , The output after the inversion processing is such that, as shown in FIG.
It becomes a signal repeated four times of “11110”.
As described above, even if the same pseudo-random pulse signal appears continuously even in the circuit shown in FIG. 4, there is a problem that the signal becomes a regular repetition and is not a completely random signal.

The present invention provides a circuit capable of generating a complete random signal and uniformly dispersing a pseudo pattern on a screen even if the same pseudo random pulse signal appears continuously from a pseudo random pulse generating circuit. The purpose is to provide.

[0011]

According to the present invention, a reproduced output signal is obtained by adding a reproduction error to an input video signal of an n-bit original pixel, and this diffused output signal is converted into m (≤n-1) bits. In the circuit which converts to the signal of
A pseudo-random pulse generator 17 for generating a pseudo-random pulse signal at a dot or line unit timing is provided. The pseudo-random pulse generator 17 includes a P-order pseudo-random pulse generator 12 and a Q (P （Q) -order. A pseudo-random pulse generator 13; and a continuous signal detecting circuit 14 for detecting whether the number of consecutive occurrences of “1” or “0” of the pseudo-random pulse signal of the P-order pseudo-random pulse generator 12 exceeds a set value. And a synthesizing circuit 15 that outputs the signal of the P-order pseudo-random pulse generator 12 when the set value is not exceeded, and synthesizes and outputs the signal of the Q-order pseudo-random pulse generator 13 when the set value is exceeded. This is a pseudo halftone processing circuit which is a feature.

[0012]

[Function] "1" of the P-order pseudo random pulse generator 12
When the number of consecutive occurrences of (or “0”) becomes a predetermined number of consecutive times, for example, four consecutive times, the continuous signal detecting circuit 14 detects this and the synthesizing circuit 15 outputs the P-order pseudo random pulse generator 1
2 and the Q-order pseudo-random pulse generator 13. As long as the output of the P-order pseudo-random pulse generator 12 is continuous, the continuous signal detection circuit 14 detects it, and the combining circuit 15 combines the output from the Q-order pseudo-random pulse generator 13 during that period. In this manner, a combined output of the P-order pseudo-random pulse generator 12 and the Q-order pseudo-random pulse generator 13 is obtained, and there is no regular repetitive signal, thereby making noise less noticeable.

[0013]

An embodiment of the present invention will be described below with reference to FIG. In FIG. 1, the same parts as those in FIG. First, a part of the error diffusion circuit 28 already proposed will be described. Reference numeral 30 denotes a video signal input terminal of an n-bit original pixel A (i, j). The video signal input terminal 30 passes through a vertical addition circuit 31, a correction addition circuit 50, a horizontal addition circuit 32, and The conversion circuit 33 performs processing for reducing the number of bits, and is connected to the video output terminal 34. The vertical direction adding circuit 31 and the horizontal direction adding circuit 32 constitute a reproduction error adding circuit.

An error detection circuit 35 is connected to the output side of the horizontal addition circuit 32. This error detection circuit 3
Reference numeral 5 denotes a ROM 38 in which data of a correction luminance level for luminance gradation correction is previously set and stored, and a difference between the correction luminance level set in the ROM 38 and a diffusion output signal output from the horizontal direction addition circuit 32 is calculated. A subtraction circuit 39 for outputting an error detection signal, and load circuits 40 and 41 for outputting an error load signal obtained by weighting the error detection signal output from the subtraction circuit 39 with a predetermined weight.

The load circuits 40 and 4 of the error detection circuit 35
The output side of 1 is connected to the vertical direction addition circuit 31 and the horizontal direction addition circuit 32 via an h line delay circuit 36 and a d dot delay circuit 37, respectively. The h-line delay circuit 36 delays the error load output signal output from the load circuit 40 by h lines, and outputs the original pixel A (i,
j), a reproduction error (eg, a reproduction error E (i, j-1) generated in the past by one line when h = 1) for a pixel h lines before is output to the d-dot delay circuit 3.
Numeral 7 is a signal for delaying the error load output signal output from the load circuit 41 by d dots.
The reproduction error for the pixel before the dot (for example, when d = 1, the reproduction error E (i−1,
j)) is output.

Next, the pseudo random pulse generation circuit 17 added according to the present invention will be described. Reference numeral 12 denotes a P-order pseudo-random pulse generator 12 that generates a pseudo-random pulse signal at a dot or line unit timing. The P-order pseudo-random pulse generator 12 includes a primitive polynomial circuit and a P-sequence code generation circuit. In the case of the primitive polynomial circuit, the primitive polynomial circuit includes, for example, a 19th-order primitive polynomial circuit mainly composed of 19 flip-flop circuits and 3 addition circuits, and has a period (2 ¹⁹ -1) (that is, a period of 5).
24, 287) to output random pulse signals of "1" and "0".

Here, the periods 524 and 287 indicate that the length of one period is 524,287 times (period) the unit pulse period. Such a pseudo-random pulse signal has a repetition of a period, but since the period is sufficiently long, it can be regarded as a random pulse signal.

A Q-order pseudo-random pulse generator 13 is connected in parallel with the P-order pseudo-random pulse generator 12. The Q-order pseudo-random pulse generator 13 has a sufficiently lower order (P≫Q) than the P-order pseudo-random pulse generator 12.

The P-order pseudo random pulse generator 12 checks whether the number of consecutive occurrences of "1" and "0" of the pseudo random pulse signal of the P-order pseudo random pulse generator 12 exceeds a set value (for example, 4). It is connected to a synthesizing circuit 15 via a continuous signal detecting circuit 14 for detecting whether or not the signal is present. Also,
The P-order pseudo-random pulse generator 12 and the Q-order pseudo-random pulse generator 13 are connected to the synthesizing circuit 15, and “1” and “0” of the P-order pseudo-random pulse generator 12 are connected.
When the number of consecutive appearances exceeds the set value, the pseudo-random pulse signal from the Q-order pseudo-random pulse generator 13 is synthesized and output to the random pulse output terminal 16, and when the number of continuous appearances does not exceed the set value. The pseudo random pulse signal from the P-order pseudo random pulse generator 12 is output as it is.

The P-order pseudo-random pulse generator 12
And the Q-order pseudo-random pulse generator 13Each different
ToGenerate a random pulse signal with a period of a predetermined length,P order
Pseudo random pulse generator 12 and Q-order pseudo random pulse
When the combined output result of the source generator 13 has a predetermined length,
Number of occurrences of "1" and "0"ButSince they are equal,
When the sum of data at the time of
Is equal to the sum of the data of
The amount is ± 0. The random pulse output terminal 16 is
Multiplied by a factor of ± k (| k | <1) as necessary and output
To the correction addition circuit 50 via the correction coefficient circuit 60
Are combined. 10 is a vertical synchronization signal input terminal
Reference numeral 11 denotes a clock signal input terminal.

Next, the operation of the embodiment shown in FIG. 1 will be described. It is possible that the error detection circuit 35 diffuses the original video input signal by incorporating an error, and that a signal having a smaller number of bits than the original video input signal does not lower the light emission luminance and obtain a smooth response. As described above.

Next, the operation of the pseudo random pulse generation circuit 17 according to the present invention will be described with reference to FIG. FIG.
As shown in (a), a P-order pseudo-random pulse generator 1
It is assumed that there is a period in which the number of consecutive appearances of 2 “1” (or “0”) is 20 consecutive times. When the continuous signal detection circuit 14 first detects that the output of the P-order pseudo-random pulse generator 12 is continuous for a predetermined number, for example, four, the synthesizing circuit 15 outputs the P-order pseudo-random pulse as shown in FIG. An output as shown in FIG. 2C obtained by combining the pulse generator 12 and the Q-order pseudo-random pulse generator 13 as shown in FIG. 2B. Note that the synthesis result shown in FIG.
The output of the P-order pseudo random pulse generator 12 and the Q-order pseudo random pulse
The output of the random pulse generator 13 and the exclusive OR
This is the transfer output result. However, in the present invention, the synthesis
The operation for calculation is not limited to this.
When the dam pulse has the same value continuously, the Qth order pseudo
Combine with a random pulse to make a random pulse
For example, an exclusive OR may be used. Since the continuous signal detection circuit 14 further detects that the output of the P-order pseudo random pulse generator 12 is continuous, the synthesis circuit 15 is sequentially synthesized with the Q-order pseudo random pulse generator 13.

Similarly, in this example, since the output of the P-order pseudo-random pulse generator 12 is detected to be continuous 20 times, the synthesizing circuit 15 outputs the signal from the Q-order pseudo-random pulse generator 13 during that period. Combine the output. In this way, a combined output of the P-order pseudo-random pulse generator 12 and the Q-order pseudo-random pulse generator 13 as shown in FIG. 2C is obtained, and there is no regular repetitive signal.
Noise can be made inconspicuous.

In the above embodiment, the case where the display panel is a PDP has been described. However, the present invention is not limited to this, and can be applied to a case where a display panel other than the PDP (for example, a liquid crystal display panel) is used.

[0025]

According to the present invention, the pseudo-random pulse generation circuit 17 includes a P-order pseudo-random pulse generator 12, a Q-order pseudo-random pulse generator 13, and a pseudo-random pulse of the P-order pseudo-random pulse generator 12. A continuous signal detection circuit 14 for detecting whether the number of consecutive occurrences of a signal "1" or "0" exceeds a set value, and outputs a signal of the P-order pseudo-random pulse generator 12 when the set value is not exceeded. And a synthesizing circuit 15 for synthesizing and outputting the signal of the Q-order pseudo-random pulse generator 13 when the signal exceeds the threshold.
Even if the P-order pseudo-random pulse generator 12 has the same continuous value, by switching to the Q-order pseudo-random pulse generator 13 and outputting the same value, the P-order pseudo-random pulse generator 12 does not have the same continuous value and has a randomness that is not completely regular. Signal can be generated. Thereby, pseudo patterns on the screen can be scattered uniformly.

Further, according to the present invention, the difference signal between the setting data in the ROM 38 and the diffusion output signal from the reproduction error addition circuit is output by the subtraction circuit 39 of the error detection circuit 35 to output an error signal. Since the error weighting signal is output by weighting at 40 and 41, the original video input signal is diffused by incorporating errors, and the light emission luminance is reduced by a signal having a smaller number of bits than the original video input signal. And a smooth response can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a pseudo halftone processing circuit according to the present invention.

FIG. 2 is an explanatory diagram of an operation by the circuit of the present invention.

FIG. 3 is an explanatory diagram of an operation by the circuit of FIG. 4;

FIG. 4 is a block diagram of a pseudo halftone processing circuit already proposed by the present applicant.

[Explanation of symbols]

10 vertical sync signal input terminal, 11 clock signal input terminal, 12 P-order pseudo-random pulse generator, 13 Q
Next pseudorandom pulse generator, 14 continuous signal detection circuit, 15 synthesis circuit, 16 random pulse output terminal,
17 pseudo random pulse generation circuit, 28 error diffusion circuit, 30 video signal input terminal, 31 vertical addition circuit (an example of a reproduction error addition circuit), 32 horizontal addition circuit (an example of a reproduction error addition circuit) , 33 ... bit conversion circuit,
34 video output terminal, 35 error detection circuit, 36 h line delay circuit, 37 d dot delay circuit, 38 RO
M, 39: subtraction circuit, 40, 41: load circuit, 50: correction addition circuit, 52: primitive polynomial circuit (an example of a pseudo random pulse generation circuit), 54: correction amount control circuit, 56: correction amount monitoring circuit, 58 ... inversion circuit, 60 ... correction coefficient circuit.

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Junichi Onodera 1116 Suenaga, Takatsu-ku, Kawasaki, Kanagawa Prefecture Inside of Fujitsu General Limited (72) Inventor Hayato Denda 1116, Suenaga, Takatsu-ku, Kawasaki, Kanagawa Fujitsu General Limited (56) References JP-A-5-22588 (JP, A) JP-A-6-284275 (JP, A) JP-A-7-143339 (JP, A) JP-A-7-121136 (JP, A) JP-A-2-90320 (JP, A) JP-A-3-226002 (JP, A) JP-A-6-86161 (JP, A) JP-A-5-327427 (JP, A) (58) (Int.Cl. ⁷ , DB name) G09G 3/20 641 G09G 5/00 G06T 5/00 H04N 1/40

Claims (3)

(57) [Claims] 1. A diffused output signal is obtained by adding a reproduction error to an input n-bit original pixel video signal, and the diffused output signal is converted into an m (≦ n−1) -bit signal. A pseudo random pulse generating circuit 17 for generating a pseudo random pulse signal at a dot or line unit timing. The pseudo random pulse generating circuit 17 includes a P-order pseudo random pulse generator 12, A next pseudo-random pulse generator 13; and a continuous signal detecting circuit 14 for detecting whether the number of consecutive occurrences of "1" or "0" of the pseudo random pulse signal of the P-th pseudo random pulse generator 12 exceeds a set value. And outputs the signal of the P-order pseudo-random pulse generator 12 when the set value is not exceeded, and outputs the signal of the Q-order pseudo-random pulse generator 13 when the set value is exceeded. 15 for synthesizing and outputting
And a pseudo halftone processing circuit. 2. The P-order pseudo-random pulse generator 12 and Q
2. The pseudo halftone processing circuit according to claim 1, wherein P≫Q in the next pseudorandom pulse generator. 3. The reproduction error is obtained by taking the difference between the set data in the ROM 38 and the diffusion output signal from the reproduction error addition circuit by a subtraction circuit 39 of an error detection circuit 35, and outputting an error signal. 3. The pseudo halftone processing circuit according to claim 1, wherein weights are output at 40 and 41 to output an error load signal.