JP3209632B2 - Weight averaging circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-window information processing apparatus, which is provided in an image blending circuit which is window-managed so that a translucent composite image can be displayed in a window overlapping portion on a display screen. The present invention relates to an improvement of a weighted average circuit having a function of actually blending.

[0002]

2. Description of the Related Art In recent years, in information processing apparatuses such as personal computers and workstations, information such as a plurality of documents is displayed on a rectangular display screen by using a plurality of windows, each of which is a rectangular area, so that an operator can obtain sufficient information. Information is provided. Recently, a moving image signal such as a video signal is input to an information processing apparatus and displayed on a window.

In the above-mentioned conventional information processing apparatus, when two windows overlap, a vertical relationship between the windows is set, and the contents of the upper window are displayed in the overlapping area. Therefore, the contents of the lower window are hidden and invisible, and the amount of information that can be displayed is limited by the size of the screen. In addition, in order to view the contents of the lower window, a complicated operation such as changing the setting of the vertical relationship of the windows or moving one of the windows is required.

In order to solve this problem, for example, it is conceivable to introduce a conventional semi-transparent image synthesis method in the field of television broadcasting into a multi-window type information processing apparatus. That is, the blend ratio α (0 ≦ α ≦ 1) is stored in the blend ratio buffer for each pixel over the entire display screen, the blend ratio α is read from the blend ratio buffer for each pixel of the display screen, and two A configuration is adopted in which pixels A and B of the window are blended by a pixel blending device according to α × A + (1−α) × B. If an image blending circuit including such a blend ratio buffer and a pixel blending device is introduced into a multi-window information processing device, a translucent composite image can be displayed in a window overlapping portion on a display screen. In addition, since the blend ratio can be arbitrarily set for each pixel, the flexibility of setting the blend ratio is high.

A specific configuration of a circuit for blending two pixels in the image blending apparatus, that is, a weighted average circuit will be described. Conventionally, there are three types of this load averaging circuit.

In the first method, as shown in FIG. 46, two multipliers 632, 63
This is a system in which the image is blended by using three and one adder 634.

In the second method, as shown in FIG. 47, the above equation is transformed into α × (AB) + B, and a subtractor 635, a multiplier 636 and an adder 63 are used to calculate the equation.
7 are provided one by one, and the image is blended.

In the third system, as shown in FIG. 48, one adder circuit 638 and n (four in FIG.
39 to 642, and weights for the adder circuit 638 are set to 1/2, 1/4,...
/ N 2, n are set so as to form a geometric progression with a common ratio of 1/2, and either one of the inputs A and B expressed in binary is selected by n selectors 639 to 642. rear,
In the addition circuit, the selected n values are multiplied by the weights of the corresponding addition circuits (hereinafter, multiplication with this weight is referred to as weighting), the n multiplication results are added, and the sum is calculated. Then, the image is blended.

[0009]

However, in the conventional image blending circuit, a blending ratio is set for each pixel constituting the entire screen of the display screen. Image type can be set to many, and the flexibility of image display is high,
When updating the blend ratio, it is necessary to update each blend ratio one by one from the first one to the last one in the window, and there is a problem that the blend ratio cannot be changed at a high speed. As a result, there is a disadvantage that a response to an operation such as moving a window is delayed. The drawback is that the blend ratio is expressed as a binary number when the number of steps of the change of the blend ratio is increased and the width of the change is reduced so that the change of the translucent image when the blend ratio is changed progresses smoothly. Since the number of bits required to perform this operation increases, the number of bits increases, and the responsiveness of updating the blend ratio further decreases.

In the above-mentioned conventional load averaging circuit,
In the first method, since two multipliers are used, there is a disadvantage that the circuit scale becomes large.

Furthermore, in the second method, the circuit scale is slightly smaller because only one multiplier is required, but a negative number is expressed and transmitted in the middle of the circuit because of the use of a subtractor. When a power point is generated and an operation corresponding to a negative number is performed at this point, the circuit becomes slightly complicated, and the number of stages of the operation circuit is large, so that the calculation time is long (specifically, the signal propagation delay is large). ), There is a disadvantage that the operation speed is slow.

In addition, in the third method, although a selector and a multi-input adder are used, the combined circuit scale and operating speed are almost the same as that of a single multiplier. Although very good, the output value does not actually exactly match α × A + (1−α) × B, and K × ｛α × A +
Since (1−α) × B｝ (K = (2 n −1) / 2 n, a value slightly smaller than 1), the video signal has a serious drawback in that the brightness decreases.

In any of the above methods, when the blend ratio α is α = 1 or α = 0, that is, when it is not necessary to blend a plurality of input signals, any one of the input signals is used. The calculation based on the blend ratio is performed despite the fact that it is only necessary to select and output the data as it is, so that there is a disadvantage that wasteful power consumption is consumed and power consumption is increased.

Further, in the third method, when the number of bits of the blend ratio α is increased so that the value of the blend ratio α can be specified at fine intervals, and the number of bits of the adder circuit is increased accordingly, When the blending ratio of the multi-bit number expression is specified, the same blending operation may be performed even with the blending ratio of the actually smaller bit number expression. There is a drawback that wasteful power is consumed.

The present invention has been made in view of such a point, and an object of the weighted averaging circuit of the present invention is to relatively blend a plurality of input signals at a predetermined blend ratio with an addition circuit. If the calculation can be performed with a small number of bits, the additional redundant portion of the adder circuit is not operated, and the power consumption is reduced accordingly.

[0016]

In order to achieve the above object of the weighted average circuit, the present invention provides two adder circuits,
When a blend of a plurality of input signals at a predetermined blending ratio can be calculated by a portion having a relatively small number of bits in an adding circuit, the blending is performed by only one adding circuit.

Specifically, the solution taken by the invention of claim 1 will be described. In the weighted average circuit of the invention of claim 1 , i, j, m, n are integers of 2 or more, and k Is a natural number, and a first set of signals composed of k signals expressed in i-ary and a second set of signals composed of jk (j> k) signals expressed in i-ary are j , The j signals are multiplied by weights corresponding to the respective j inputs, the respective multiplication results are added, and the addition result is output as a signal expressed in i-ary. first comprises adding means, a k-number of first selecting means for selecting one of the i-adic representation is the m digital input signal,
K signals selected by the k first selecting means are input to the first adding means as the first set of signals, and n signals expressed in i-ary are input, Each of the n signals is multiplied by a weight corresponding to each of the n inputs, the respective multiplication results are added, and the addition result is output as jk signals expressed in i-ary. A second adding means, and j-
k pieces provided, comprising a second selecting means for selecting one from among the output signal and the m digital input signal of the second addition means its corresponding selection of the j-k-number of second The jk signals selected by the means are input to the first adding means as the second set of signals, and
It includes n pieces of the third selection means for selecting one of the number of digital input signals and the i-adic representation constants value signal, which is respectively selected by the n third selection means n
Signals are input to the second adding means, a blending ratio is given, and control means for controlling the j selecting means so as to mix m digital input signals at the given blending ratio is provided. It is configured to be provided .

Furthermore, in the second aspect of the present invention, in weighted average circuit of claim 1 wherein, the number of signals belonging to a second set (j-k) is a structure 2.

In addition, according to the third aspect of the present invention, in the weighted average circuit according to the second aspect , the integer i is i = 2, and each weight of the first adder means the weights in descending order. Except for the last term of the first sequence, the arranged first sequence forms a geometric progression having a common ratio of 1/2, and the value of the first term of the first sequence is 1/2. , The value of the last term of the first sequence is equal to the value of the term immediately preceding the last term, and the weights of the last two terms of the first sequence are each a second set of 2
Are multiplied by each of the two signals, and the weights of the second addition means are represented by a second numerical sequence in which the respective weights are arranged in descending order, except for the last term of the second numerical sequence except for the common ratio of 1/2. And the value of the first term of the second sequence is equal to the value of the last term of the first sequence, and the value of the last term of the second sequence is the value of the immediately preceding term. The configuration is equal to the value.

According to a fourth aspect of the present invention, in the weighted average circuit according to the third aspect , the integers j, m, and n are j = 6, m = 2, and n = 5, respectively .

[0021]

[Action] More above configuration, according to claim 1, claim 2, with a load averaging circuit of the invention of claim 3 and claim 4, wherein, when can be realized by the sum of the blending ratios by a relatively large weight, the The first and second selecting means select and apply one of the m digital input signals to each input of the first adding circuit and add them, and all of the third selecting means select a constant value. The operation of the second addition circuit is stopped, and power consumption can be reduced. In contrast, in the case of requiring the addition of input of a small weight to achieve the blend given ratios, since all of the second selection means selects the output of the second adder circuit, first , And one selecting circuit is selected by the first selecting means and the third selecting means by selecting one of the m digital input signals. applied to each input of one summing circuit, since the addition operation in the single adder circuit equal to take place, it is possible to specify a finer granularity of the blend ratio.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

(First Circuit Example of Image Blending Circuit) FIG. 1 is a configuration diagram of a window-managed image blending circuit using a target weighted average circuit of the present invention. In the figure, reference numeral 100 denotes a pixel position information supply device;
03 is a first and a second image memory, 104 is the pixel blending device, 105 is a counter, 106 is a blend ratio buffer, 107 is a data selector, 108 is an attribute buffer, and 109 is a central processing unit. In FIG. 1, a thick solid line with a bit width indicates transfer of a pixel or information corresponding to the pixel, a dotted line indicates transfer of pixel position information including a pixel clock, and a thin solid line indicates transfer of other information. Represents FIG. 2 shows a function table of the data selector 107.

FIG. 3 shows a configuration diagram of the pixel blending device 4. In the figure, 111 to 113 are first to third load averaging circuits, and 114 is a D flip-flop (DF / F)
It is. FIG. 5 shows a configuration diagram of the load averaging circuits 111 to 113. Details of the configuration of FIG. 1 will be described later, and will be briefly described here. Reference numeral 201 denotes an addition circuit, reference numerals 202 to 206 denote selectors arranged on the input side of the addition circuit 201, and reference numeral 282 denotes a decoder.

The operation of the window blended image blending circuit configured as described above will be described.

In this circuit example, a screen having a size of 1152 pixels in the horizontal direction and 900 pixels in the vertical direction is used as a rectangular screen for display. However, a display device having this screen and its control device are not shown in the figure. A digital RGB pixel signal output from the pixel blending device 104 is converted into an analog video signal by a display control device including a D / A converter and sent to the display device.

The pixel position information supply device 101 generates and outputs pixel position information including a pixel clock for sequentially transferring digitized information of pixels displayed on the screen by a raster scan method. In the raster scan method, one row of 1152 pixels is displayed in the horizontal direction, for example, in order from left to right, and then, for example, one row below is displayed in the left to right direction. After displaying the bottom row,
Return to the top row and display. In this way, the sequential transfer of the pixels on the screen is repeated. In this raster scan method, since the display position is far from the display of the rightmost pixel of a certain column to the display of the leftmost pixel of the next column, the time for moving the display position of the display device is large. Is required, and is called a horizontal blank period. During this period, the information of the pixel is not transferred or is not displayed even if transferred. In addition, the period from when the lowermost column is displayed to when the uppermost column is displayed is also a break of data transfer of one screen, and is called a vertical blank period. The pixel position information supply device 101 outputs, as pixel position information, a signal indicating a horizontal blank period and a signal indicating a vertical blank period, in addition to the pixel clock. The frequency of the pixel clock is 20 MHz.

First and second image memories 102 and 10
3. The counter 105, the blend ratio buffer 106, and the attribute buffer 108 receive the pixel clock, the signal indicating the horizontal blanking period, and the signal indicating the vertical blanking period, and synchronously output information corresponding to the pixel at the same position. I do. The timing at which a pixel at a certain position is output is determined by a change in a signal indicating a horizontal blank period and a signal indicating a vertical blank period, and counting the pixel clock.

First and second image memories 102 and 103
Outputs pixel information of an image having the same size as the screen of the display device. In this circuit example, the pixels of the image are the three primary colors of light, red (Red), green (Green), and blue (Blue).
The intensity of each component (hereinafter referred to as RGB) is represented by 24-bit digital information represented by an 8-bit unsigned binary integer. First and second image memories 102, 1
In the case where the pixel output from No. 03 is not blended by the pixel blending device 104, either one is selected and displayed, and the other is not displayed. In this case, the pixel information may be a dummy appropriate value. For example, in the second image memory 103, when a video signal captured by a video camera is digitized and captured and output, due to the resolution of the video signal and the display size, it is smaller than 1152 pixels horizontally by 900 pixels vertically. It is conceivable that it is taken into size.
In that case, the second image memory 103 may output dummy data when outputting pixels in an area other than the area allocated to the captured video camera image.

The pixel blending device 104 comprises a first and a second
The two systems of RGB pixel data synchronously transferred from the image memories 102 and 103 are blended in accordance with the blend ratio input in synchronization with these, and pixels as a blending result are output. The blend ratio is a 5-bit fixed-point binary number in this circuit example. The most significant bit is the one's place. However, such a 5-bit fixed-point binary number can take a value greater than 1, but a value exceeding 1 is strange as a blend ratio. Therefore, when the fixed-point binary number is 1 or more, the blend ratio is set to 1. It shall be. The value of the given blend ratio is α, the value of an arbitrary color component among the RGB of the output of the first image memory 2 is A, and the value of the same color component of the output of the second image memory 3 is B. Then, the pixel blending device 104 calculates α × A + (1−α) × B (1). However, since each component of the output value is also 8 bits, the value after the decimal point in Expression (1) is truncated and output.

In the pixel blending device 104, FIG.
As shown in (1), the first load averaging circuit 111 is for the red component, the second weight averaging circuit 112 is for the green component, and the third weight averaging circuit 113 is for the blue component. ) Is calculated. The time required for the calculation of equation (1) varies depending on the value of the blend ratio.
Is once received by the D flip-flop 114,
Output is performed so that the timing is constant regardless of the value of the blend ratio.

Each of the load averaging circuits 111 to 113
Calculates the expression (1) with the configuration as shown in FIG. The details will be described later, and will be briefly described below. When the value of the blend ratio α is between 1 and 0, the calculation of the above equation (1) is performed by the addition circuit 201 and the input selectors 202 to 206. The addition result is output from the addition circuit 201.

As described above, the pixel blending device 104
As a result, a composite image of the image output from the first image memory 102 and the image output from the second image memory 103 is generated. Each pixel of the composite image is stored in the first image memory 1
02, a pixel output from the second image memory 103, or a pixel obtained by translucently combining the two.

The blend ratio given to the pixel blending device 104 is generated by a counter 105, a blend ratio buffer 106, a data selector 107, and an attribute buffer 108.

The counter 105 stores the value of the blend ratio to be written by the central processing unit 109, and constantly sends the stored value to the data selector 107. Central processing unit 1
From 09, an initial value, an end value, and a speed are designated, and upon receiving an instruction, for example, a signal indicating a vertical blank period is counted and automatically changed. If no instruction is received, a constant value is held as a register.

The blend ratio buffer 106 stores a blend ratio value corresponding to each pixel on the screen of the display device. That is, 1152 × 900 blend ratios are stored. This makes it possible to realize an arbitrary distribution of the blend ratio on the screen. According to the pixel position information including the pixel clock, the blend ratio data in the blend ratio buffer 106 is sequentially read and sent to the data selector 107.

The data selector 107 selects either the value output from the counter 105 or the value output from the blend ratio buffer 106 for each pixel and outputs the selected value to the pixel blending device 104 according to the control signal sent from the attribute buffer 108. .

The attribute buffer 108 has, for each pixel, a value of a control signal to be supplied to the data selector 107, that is, 1 bit 2 indicating whether to use the output of the counter 105 or the output of the blend ratio buffer 106 as the blend ratio. This 1-bit binary control signal is sequentially output to the data selector 107 in accordance with pixel position information including a pixel clock.

The central processing unit 109 updates the contents of the blend ratio buffer 106 and the attribute buffer 108 according to the window operation by the operator.

Next, the operation when a window is displayed on the screen will be described.

The coordinates on the display screen are
The position shifted x pixels to the right and y pixels down as (0,0)
(x, y). As an example for explanation, FIG. 5 shows the position and size of the window to be set. In the figure, 125 to 127 are first to third areas, and 130 is a display screen. First to third regions 125-1
27 are display screens 30 each having vertical and horizontal sides.
Is a rectangular area parallel to. The first area 125 has a size 480 with the upper left end set to (50,50) and the lower right end set to (529,349).
× 300 area. The second area 126 is located at the upper left corner.
(450,400), size 640x with lower right corner at (1089,879)
480 area. The third area 127 has the upper left corner at (3
00,200), size 640 × 4 with the lower right corner at (939,679)
80 area.

In FIG. 6, a fourth area 128 is an area where the first area 125 and the third area 127 overlap, and has a size 230 whose upper left end is (300,200) and whose lower right end is (529,349). × 150 area. Fifth area 129
Is an area where the second area 126 and the third area 127 overlap, and the upper left end is (450,400) and the lower right end is (939,679)
490 × 280.

Here, the first and second image memories 10
Reference numerals 2 and 103 store an image corresponding to the display screen and output the pixels. Now, a document 131 is displayed in the first area 125 as shown in FIG.
It is assumed that a pattern 132 is displayed in an area 126 of the document 131, and an image composed of the document 131 and the pattern 132 is stored and output in the first image memory 102 as shown in FIG. The content of the blend ratio buffer 106 is a blend ratio 1 for all the pixels on the display screen 130 (when this blend ratio is simply arranged on the display screen 130 in two-digit hexadecimal (original 5 bits), As shown in FIG. 8, the contents of the attribute buffer 108 are stored in the blend ratio buffer 1 for all the pixels on the display screen 130.
06 is a value 0 indicating an output selection. As a result, the data selector 107 sets the blend ratio buffer 10
6, the pixel blending device 104 selects the output of the first image memory 102 for all pixels and sends it to the display device. In this case, the value of the blend ratio stored in the counter 105 is not referred to.

Next, when the window displaying the design 132 is moved to the third area 127, the document 131 and the design 1 are moved.
Since 32 overlaps occur in the fourth area 128,
As shown in FIG. 9, a document 131 and a symbol 132 are stored in an area 128.
Are synthesized translucently. The operation of this translucent composition will be described. The portion of the symbol 132 that has moved onto the fourth area 128 does not overwrite the part of the document 131 on the area 128 as shown in FIG. Is transferred to a portion of the second image memory 103 corresponding to the area 128. Thus, the area 128 of the image stored in the first image memory 102 includes a part of the document 131, and the area 128 of the image stored in the second image memory 103.
8 has a part of the symbol 132, so that when the pixels of the respective areas 128 of the first and second image memories 102 and 103 are simultaneously output, the blend ratio is set to a value between 0 and 1, As shown in FIG. 9, a document 131 and a symbol 132 are stored in an area 128.
Is synthesized translucently.

At this time, there are two methods for setting the blend ratio in the fourth area 128 to a value between 0 and 1. One is a method of changing the contents of the area 28 of the blend ratio buffer 106 without changing the contents of the attribute buffer 108, and 230 × 150 × 5 = 172,50.
Requires writing of 0-bit data. Second, without changing the contents of the blend ratio buffer 106,
A value between 0 and 1 is set in the counter 105, and the contents of the area 128 of the attribute buffer 108 are stored in the counter 10
This is a method of changing the output of No. 5 to a value to be selected.
Since it is necessary to write data of 150 × 1 = 34,500 bits, only one-fifth of the method of changing the content of the blend ratio buffer 106 is required.

Therefore, in this circuit example, as shown in FIG. 10, the content of the blend ratio buffer 106 is a blend ratio of 1 for pixels other than the area 128 on the display screen 130 (the blend ratio shown in FIG. 10). Is a simple two-digit hexadecimal notation similar to the blend ratio in Fig. 8. Since the pixels in the area 128 are not referred to, any value may be used as shown by hatching in Fig. 8). As shown in FIG. 10, the value of the blend ratio stored in 105 is 08 in the same simple two-digit hexadecimal notation as described above. The contents of the attribute buffer 108 are stored in the area 12 on the display screen 130 as shown in FIG.
The value 0 instructs selection of the output of the blend ratio buffer 106 for pixels other than 8, and the value 1 instructs selection of the output of the counter 105 in the area 128. As a result, the data selector 107 selects the output of the blend ratio buffer 106 for an area other than the area 128 on the display screen 130 as shown in FIG.
At 28, the output of the counter 105 is selected. as a result,
The pixel blending device 104 stores the first image memory 10 in the pixels other than the area 128 on the display screen 130.
2 is selected, the output of the first image memory 102 and the output of the second image memory 103 are translucently synthesized at the pixels in the area 128 and sent to the display device.

As shown in FIG. 9, out of 1152 × 900 = 1,036,800 pixels on the display screen 130, the area 128
When the blending is performed at a blending ratio of a value between 0 and 1 only at 230 × 150 = 34,500 pixels, the load averaging circuit 111 provided inside the pixel blending device 104
To 113, the addition circuit 201 inside the region 128
It operates only during the output of the pixel. Assuming that there is no power consumption when not operating, the power consumption is 34,500 / 1,036,800 × 100 = 3.3% when operating for all pixels.

Further, by activating the counting operation of the counter 105, the blend ratio in the case of performing the translucent composition can be gradually changed even if the central processing unit 109 does not individually write. Thus, a smooth change in the blend ratio can be realized without burdening the central processing unit 109. When a moving image such as a video signal is displayed, switching between scenes and channels can be performed by a change that gives a soft image. Even when the windows of the still images overlap as shown in FIG. 9, if the blend ratio is changed smoothly at an appropriate speed and the information of the overlapping portion is alternately displayed, the display is always performed at a constant blend ratio. The display contents are easy to read, and the eyes do not need to be tired as compared with the case where the display is switched instantaneously and alternately displayed.

(Second Circuit Example of Image Blending Circuit) A second circuit example of the image blending circuit of the present invention will be described with reference to the drawings.

FIG. 11 shows a second embodiment of the image blending circuit of the present invention.
3 is a configuration diagram of a circuit example of FIG. In the figure, reference numeral 133 denotes a 2-bit selection input data selector, and 134 denotes a 2-bit output attribute buffer. The same components as those in FIG. 1 are denoted by the same reference numerals. FIG. 12 shows a function table of the data selector 133.

In this circuit example, the data selector 107 in the first circuit example is selected and output from the output of the counter 105, the output of the blend ratio buffer 106, and the other two fixed blend ratios. 1
33, and the control signal of the data selector 133 is 2
Attribute buffer 108,
This is replaced with an attribute buffer 134 that stores a 2-bit control signal for one pixel. FIG.
As can be seen from FIG. 2, the values of the two fixed blend ratios are 0
And 1. Therefore, a blend ratio is selected from four values obtained by adding two constant values to the output of the counter 105 and the output of the blend ratio buffer 106, for each pixel, controlled by the value of the attribute buffer 134. Other operations are the same as those of the first example of the image blending circuit.

In the image blending circuit of the first circuit example, the pixel blending device 104 operates in the first image memory 1 when the display state is not translucent as shown in FIG.
02 to select the output of blend ratio buffer 1
06 stores the value 1 for all pixels. Therefore, before turning on the power of the information processing apparatus including the image blending circuit and shifting to the display state as shown in FIG.
It is necessary to write the values of all the pixels in the blend ratio buffer 106 once. This is 1152 × 900 × 5
= Write data of 5,184,000 bits.

On the other hand, in the image blending circuit of the present circuit example, as shown in FIG.
3 can select the value 1 of the blend ratio as a constant. In order to give the value 1 of the blend ratio to all the displayed pixels, the value corresponding to all the pixels in the attribute buffer 134 is represented by a binary number. 11, it is unnecessary to rewrite the blend ratio for the blend ratio buffer 106 as shown in FIG. Therefore, 1
Writing of 152.times.900.times.2 = 2,037,600 bits of data results in 2/5 data writing.

When two pieces of information are overlapped only in a part of the area 128 on the display screen 130 as shown in FIG. 9, the area excluding the area 128 of the display screen 130 as shown in FIG. , The value of the attribute buffer 134 is set to the binary number 11, the data selector 133 selects the value 1 of the blending ratio, the pixel blending device 104 selects the output of the first image memory 102, and the display display screen 130 In the area 128, the value of the attribute buffer 134 is set to the binary number 01, the data selector 133 selects the value of the blend ratio 08 of the counter 105, and the pixel blending device 104 outputs the output of the first image memory 102 and the second image. Memory 103
And the output of the above are synthesized at the blend ratio 08.

As described above, according to the second circuit example,
The 1-bit selection input data selector 107 of the first circuit example is replaced with a 2-bit selection input data selector 133, and the attribute buffer 108 is replaced with a 2-bit output attribute buffer 134, corresponding to the window. When setting the blend ratio, the amount of data to be written can be smaller.

(Third Circuit Example of Image Blending Circuit) Hereinafter, a third circuit example of the image blending circuit of the present invention will be described with reference to the drawings.

FIG. 15 is a configuration diagram of a third circuit example of the present invention. In FIG. 15, 135 is a window information storage device, and 136 is a control signal determination device. The same components as those in FIG. 11 are denoted by the same reference numerals.

In this circuit example, the attribute buffer 134 in the second circuit example is replaced with a window information storage device 135 and a control signal determination device 136.

The window information storage device 135 stores the coordinates of each window to be displayed, the priority (overlap information), and the selection of the blend ratio. For example, the information stored in the window information storage device 135 in the states of FIGS. 7 and 9 is as shown in the tables of FIGS. 16 and 17, respectively. However, the information in the remarks column of FIGS. 16 and 17 does not need to be stored in the window information storage device 135. The information stored in the window information storage device 135 is always referred to by the control signal determination device 136.

The control signal determination device 136 receives the pixel clock, the signal indicating the horizontal blank period and the signal indicating the vertical blank period from the pixel position information supply device 101, and counts the signal indicating the horizontal blank period and the pixel clock. Then, the coordinates of the transferred pixel are calculated. By comparing these coordinates with the coordinates of each window stored in the window information storage device 135, it is determined which window contains the transferred pixel. If it is included in two or more windows, it is assumed that the window with the highest priority is included. The control signal determination device 136 determines and outputs the control signal of the data selector 133 by selecting the blend ratio of the window thus determined. The contents of this output are displayed on the display screen shown in FIG.
Both the case where the information overlaps and the case where the information does not overlap in FIG. 9 are the same as those in FIGS. 13 and 14.

The information stored in the window information storage device 135 must include only one window determined to include the coordinates for all coordinates on the screen. In other words, if two or more windows are included in the coordinate calculation, the window with the highest priority must be unique. The central processing unit 109 must obey this restriction when setting the window and updating the storage contents of the window information storage device 135.

Each window (corresponding to one row of data in the tables of FIGS. 16 and 17) stored in the window information storage device 135 does not always coincide with a window as a unit operated by the operator. For example, in the display state of FIG. 9, two windows as units operated by the operator are a document 131 displayed in the first area 125 and a symbol 132 displayed in the third area 127. However, in addition to the above, the window information storage device 135 needs a root window representing the entire screen and data of a window corresponding to the overlapping portion corresponding to the fourth area 128, and stores the information of FIG. In FIG. 17, for example, at the display position in the fourth area 128, three registered windows other than the root window match in the coordinate calculation. However, considering the priority, the document 131 and the pattern 132 of priority 2 are considered. Only the window corresponding to the overlap with is selected and satisfies the above constraint.

The method of determining the blend ratio of each pixel is as described above, and the other operation of this circuit example is the same as that of the second circuit example.

In the image blending circuit of the second circuit example, the pixel blending device 104 is operated by the pixel blending device 104 between the time the power is turned on and the transition to the display state in which translucent composition is not performed as shown in FIG. The binary number 11 is written to all the pixels in the attribute buffer 134 so as to select one output of the image memory 102. Accordingly, data of 1152 × 900 × 2 = 2,037,600 bits is written.

On the other hand, in the present circuit example, in order to shift to the display state of FIG. 7, instead of writing the data in the attribute buffer 134, the information of the table of FIG. Just write it. The number of bits of this data is 11 bits in the horizontal direction and 10 bits in the vertical direction. The maximum priority depends on the number of windows that can be registered. Assuming that the selection of the blend ratio is 2 bits using the control signal as it is, 32 bits are required for one window. In FIG. 16, since there are three pieces of window information, 96 bits may be used.

Further, even when the window of the symbol 32 is moved from FIG. 7 to the state of FIG. 9, the area 128 of the attribute buffer 18 or 134 is changed like the image blending circuit of the first and second circuit examples. Counter 1
230 × 15 to change the output of 05
Instead of changing the information of 0 = 34,500 pixels, the information corresponding to the window of the symbol 132 in the window information storage device 135 may be updated, and the information of the window corresponding to the overlapping portion corresponding to the area 128 may be added. 64-bit data writing may be used.

In the third circuit example, when the number of windows and the number of overlapping portions are increased, the information that must be stored in the window information storage device 135 increases, and the amount of information that must be updated by operating the window also increases. Therefore, the limit of the number of windows and the settable overlapping portion is limited by the storage capacity of the window information storage device 135. Even if this is taken into consideration, the necessary data write amount can be reduced when the area (number of pixels) of the display state is large due to the operation of the window.

As described above, according to the third circuit example, the attribute buffer 134 in the second circuit example is used.
Is replaced by the window information storage device 135 and the control signal determination device 136, so that the amount of data to be written becomes larger when the blend ratio is set corresponding to the window or when the display state is updated in response to the window operation. Less is needed.

It should be noted that the attribute buffer 108 in the first circuit example may be replaced with a window information storage device and a control signal determination device similar to those in the present circuit example.

In all of the above circuit examples, only one counter 105 serving as a register is provided, but two or more counters may be provided. In particular, in the second and third circuit examples, instead of the fixed values 0 and 1 selected by the data selector 133, the output may be selected by increasing the number of registers or counters. In this case, the number of regions in which the blend ratio can be individually rewritten at high speed can be increased by the number of registers. However, when the number of registers is increased, the number of options to be selected by the data selector 107 or 133 is increased, the number of bits of the control signal is increased, the capacity of the attribute buffer 108 or 134 or the window information storage device 135 is increased, and the speed is increased. It is important to note that the effect of this is reduced. If a low speed is acceptable, it is necessary to consider that the blend ratio buffer 106 can realize an arbitrary blend ratio distribution.

[0071] (load first example of proposed averaging circuit) will be described with reference to FIG. 4 for a first example of proposed weighted average circuit of the present invention.

FIG. 4 is a configuration diagram of a first proposed example of the present invention. In the figure, 201 is the addition circuits, 202-206
It is a selector. FIG. 18 shows a logic circuit diagram of each of the selectors 202 to 206. In the figure, 207 is an inverter, 20
8 to 215 are two-input AND circuits, and 216 to 231 are two-input OR circuits.

The adding circuit 201 is configured by continuously connecting the partial adding circuit 232 shown in FIG. 19 and the partial adding circuit 257 shown in FIG. The output # 1 of the partial addition circuit 232 in FIG. 19 is connected to the input A of the partial addition circuit 257 in FIG. 20, and the output # 2 of the partial addition circuit 232 is connected to the input B of the addition circuit 257. 19 and 20, 233 to 256
And 258 to 265 are 1-bit full adders. FIG.
1 shows a truth table of the operation of the logic circuit.

The adder 201 inputs and adds 8-bit binary numbers weighted to 1/2, 1/4, 1/8, 1/16, and 1/16 by shifting the digits, and adds the total. Output. The sum of the respective weights is 1, and 1/2, 1/4, 1/8, 1 /
16 is a geometric progression having a common ratio of 1/2. The weight of the output is the sum of the weights, that is, 1 and the output is 12 bits because it is shifted by 4 digits from the minimum weight 1/16.
The selectors 202 to 206 are configured to select which of the input signals A and B is to be applied to the input of each weight.
Let the selection control signals of the respective selectors be S2 to S6.

Next, the specific configuration and operation of the load averaging circuit will be described. The selection control signal input S of the selector is 0 or 1, and when S = 1, the output is Y = A, and when S = 0, the output is Y = B.
Can be represented as Y = [S2xA + (1-S2) xB]. Since the outputs of the selectors are weighted and summed in this way, the output value of the adder circuit 201 can be expressed by A, B, S2 to S6 as the following equation (2). (3)
Which is further transformed to the following equation (4).

[S1xA + (1-S2) xB] / 2 + [S3xA + (1-S3) xB] / 4 + [S4xA + (1-S4) xB] / 8 + [S5xA + (1 -S5) xB] / 16 + [S6xA + (1-S6) xB] / 16… (2) [S2 / 2 + S3 / 4 + S4 / 8 + S5 / 16 + S6 / 16] x A + [ (1-S2) / 2 + (1-S3) / 4 + (1-S4) / 8 + (1-S5) / 16 + (1-S6) / 16] xB… (3) [S2 / 2 + S3 / 4 + S4 / 8 + S5 / 16 + S6 / 16] x A + (1- [S2 / 2 + S3 / 4 + S4 / 8 + S5 / 16 + S6 / 16]) xB… (4) , Blend ratio α = S2 / 2 + S3 / 4 + S4 / 8 + S5 / 16
Assuming + S6 / 16, the output is αx A + (1-α) xB. α = S2 / 2 + S3 / 4 + S4 / 8 + S5 / 16 + S6 / 16, the first to fourth terms indicate that the selection control signal (S2, S3, S4, S5) Indicates that it represents a base number. Therefore, according to the first to fourth terms, 0.
It is possible to represent 16 values in increments of 0625. When the selection control signal S6 = 0, the fifth term becomes 0, so the blend ratio α has the value shown above, and the selection control signal S6
In the case of = 1, the value of the fifth term is 0.0625, so that the blending ratio α takes 16 values in the range of 0.0625 to 1 in increments of 0.0625. Therefore, the selection control signal S6 =
The number of possible cases of the blend ratio α between 0 and S6 = 1 overlaps in 15 ways. After all, the selection control signal (S2,
S3, S4, S5, S6) in the range of 0 to 1 in increments of 0.0625
The value of the blend ratio α can be specified.

As described above, the weighted average circuit of the proposed example calculates the value of αx A + (1-α) xB accurately and calculates the value of the blend ratio α in the case of 17 values in the range of 0 to 1. It was shown that it could be done.

Here, an example of an operation in which a specific numerical value is input will be described. The values of input signals A and B are decimal numbers 217 and 38, respectively.
Then, if expressed in binary, each is 11011001,00
100110. Here, the selection control signals (S2, S3, S4,
S5, S6) = (1,0,1,1,0), the following equation (5)
Becomes

Α = 1/2 + 1/8 + 1/16 = 11/16 = 0.6875 (5) By these inputs, the selectors 202, 204, 205
Selects the value of the input signal A, and the selectors 203 and 206 select the value of the input signal B. Therefore, the following calculation is performed in the addition circuit 201.

[0080] When the output 12-bit binary number 1010000001.0001 is converted to a decimal number, it is 161.0625, and the calculation is 217 × 0.687.
You can see that 5 + 38 x 0.3125 is done correctly.

Another example will be described. Assuming that the values of the input signals A and B are each 25,131 in decimal, they are 00011001, 10000011 in binary. When the selection control signal (S2, S3, S4, S5, S6) = (1,1,0,1,0), the following equation (6) is obtained.

Α = 1/2 + 1/4 + 1/16 = 13/16 = 0.8125 (6) By these inputs, selectors 202, 203, 205
Selects the value of the input signal A, and the selectors 204 and 206 select the value of the input signal B. Therefore, the following calculation is performed in the addition circuit 201.

[0083] The output 12-bit binary 00101100.1110 is 44.875 when converted to decimal, which is calculated as 25 x 0.8125 +
It turns out that 131 x 0.1875 is done correctly.

Next, the weighted average circuit of the proposed example and the multiplier will be compared.

The weighted average circuit of the proposed example is configured by connecting five inputs of 8-bit selectors 202 to 206 to each input of an adder circuit 201 having five 8-bit inputs. The 8-bit selector is a 2, 2-input AN as shown in FIG.
It is composed of eight D-OR circuits and one inverter. Therefore, the weighted average circuit of the proposed example has 40 AND-OR circuits. A multiplier that multiplies an 8-bit value by a 5-bit value includes a set of each bit of a multiplier and each bit of a multiplicand (8 × 8 bits) in five 8-bit inputs, that is, a 40-bit input divided into several weights. (5 = 40 patterns) AND is configured by connecting 40 2-input AND gates. Thus, the scale of the adder circuit is exactly the same in the weighted average circuit of the proposed example and the 8-bit × 5-bit multiplier. The circuit in the preceding stage is slightly larger in the proposed example by the difference between the 40 AND gates and the 40 AND-OR circuits, but has a negligible scale in view of the scale of the adder circuit. It can be said that the calculation time and the circuit scale are almost the same.

As described above, in the proposed example , the multi-input addition circuit is configured so that the sum of the weights is 1, which is twice the maximum value of the weight １ ／, and the digital input signals A, B
Has a selector that selects a signal to be input to the addition circuit from each of the weights for each weight, thereby having a circuit scale and an operation speed as small as the number of gates of a single multiplier, having a small number of gates, a high calculation speed, and accurately αx A weighted average circuit for calculating A + (1-α) xB can be provided.

In the proposed example , four input signals expressed in binary numbers are input to the adder 201.
It is not limited to the base number representation, but may be any i-base number representation. This is the same in the following description. (Load second example of proposed averaging circuit) Hereinafter, with reference to the drawings second example of proposed weighted average circuit of the present invention will be described.

[0088] Figure 32 is a second Hisage the weighted average circuit of the present invention
It is a block diagram of a Anrei. In the figure, reference numeral 266 denotes a circuit for performing zero rounding. The same components as those in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted.

FIG. 33 is a logic circuit diagram of the circuit 266 for performing zero rounding. In the figure, 267 to 274 are two-input exclusive OR circuits, and 275 to 281 are two-input AND circuits.

The circuit 266 for performing zero rounding discards the lower 3 bits from the input of 12 bits, ignores the 9th bit from the upper bit if it is 0, outputs the upper 8 bits as it is, and outputs the upper 8 bits as it is. If the 9th bit is 1, 8
The calculation is performed by incrementing the bit and adding 1 to output the upper 8 bits.

In this example , A ≦ 11111111
(Binary), B ≦ 11111111 (binary), 0 ≦ α
Since ≤1, the value input to the circuit 266 for performing the zero rounding, that is, the output of the adding circuit 201 is αx A + (1-α) x
B ≦ 111111111.000 (binary number). Therefore, in the circuit 266 for performing the zero rounding, the carry of the carry does not cause an overflow, so that the output of the AND circuit 281 and the input signal IN [11] are logically ANDed to the upper bit. There is no need to raise it.

The specific configuration and operation of the weighted average circuit of the present proposal will be described. Until the output of the adder 201, the first
Since this is the same as the proposal example , the description is omitted. Adder circuit 20
Although the output of 1 is 12 bits, it is rounded to 8 bits by a zero rounding circuit 266 and rounded down to 8 bits by a zero rounding circuit 266 and output.

An example of the operation when a specific numerical value is input will be described. The value of the example numerical value is set to the value shown in the first proposal example for simplicity. First, the values of the input signals A and B are 217 and 38 in decimal, respectively, and (S2, S3, S4, S5, S6) = (1, 0, 1, 1).
1,0), that is, α = 0.6875, as shown in the first proposal example , the output of the adder 201 is 10100001.0001 in a 12-bit binary number, which is 161.0625 when converted to a decimal number. Circuit 2 for this value to be rounded to zero
When the value is input to 66, the first decimal place of the ninth bit from the high order is 0, so the fractional part is discarded. Therefore, the output of the circuit 266 performing the zero rounding is 8 bits 2
It is 10100001 in decimal number, which is 161 when converted to decimal number.
It is. In this case, the error is -0.625.

Another example will be described. The values of the input signals A and B are each 25,131 in decimal, and the selection control signals (S2, S3, S4,
S5, S6) = (1,1,0,1,0), that is, α = 0.8125, the output of the adder 201 is a 12-bit binary number 00101100.1110 as shown in the first proposal example . In decimal notation, it is 44.875. When this value is input to the circuit 266 that performs the zero rounding, the first decimal place of the ninth bit from the high order is 1, and the decimal part is rounded up. Therefore, a circuit 266 for performing zero rounding is provided.
Output is 00101101 as an 8-bit binary number, and
In decimal notation, it is 45. In this case, the error is 0.125.

The error is compared with the case of the first proposed example . The position of the decimal point is between the 8th and 9th bits. In other words, the eighth bit is the one's place. First offer
When the output of the example is rounded down to 8 bits by truncating the 9th and lower bits, the error ε is −0.9375 ≦ ε ≦ 0, and the average assuming a uniform distribution is −0.46875. In the case of the proposed example , the error ε is −0.4375 ≦ ε ≦ 0.5, and the average assuming a uniform distribution is 0.03125.

As described above, the weighted average circuit of the present proposal example
By providing a circuit for performing the zero rounding, the average value of the errors can be reduced.

The partial addition circuit 257 of the addition circuit 201
May be changed to include a circuit 266 for performing zero rounding. In this case, the number of circuit stages can be reduced, and the circuit amount and the calculation time can be reduced.

[0098] (Third example of proposed weighted mean circuit) Hereinafter, with reference to the drawings third example of proposed weighted average circuit of the present invention will be described.

[0099] A third Hisage load averaging circuit 24 according to the present invention
It is a block diagram of a Anrei. In the figure, reference numeral 282 denotes a decoder as control means for outputting a selection control signal for controlling each of the selectors 202 to 206. The same components as those in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted.

The circuit of the decoder 282 is shown in FIG. In the figure, 283 to 286 are two-input OR circuits.

As shown in the first proposal example , the adder circuit 201 performs １ ／, ４ ，, 1
An 8-bit binary number weighted to / 8, 1/16, 1/16 is input and added, and the sum is output.

The specific configuration and operation of the weighted average circuit of the proposed example will be described. The input r is converted by the decoder 282 into selection control signals S2 to S6 of the selector and output. The operations of the selectors 202 to 206 and the addition circuit 201 are the same as those of the first embodiment.
This is as shown in the proposal example . As shown therein, the weights corresponding to the selectors 202 to 205 are 1/2, 1/4, 1
/ 8, 1/16 and a common ratio of 1/2, so when the selection control signal S6 = 0, (S2, S3, S4, S5) is converted to a 4-digit binary number after the decimal point. Blend ratio α = S2 / 2
Works with + S3 / 4 + S4 / 8 + S5 / 16. The input r is a 5-bit fixed-point binary number, the most significant bit of which is one's.
It represents the range of 0.0000 to 1.1111. Therefore, when the most significant bit is 0, the decoder 282 outputs the lower 4 bits of the input r as the selection control signal (S2, S3, S4, S5) as it is,
The selection control signal S6 is set to 0. The most significant bit of input r is 1
In the case of, the value is 1 or more, but for a value exceeding 1, the operation is performed with the blend ratio α = 1. That is, it is interpreted that the blend ratio is saturated at 1. Therefore, if the most significant bit of the input r is 1, S2 =
S3 = S4 = S5 = S6 = 1.

More specifically, the selection control signals S2 to S6 of the selector for some values of the input r will be described.
For example, if the input r = 11.0110, the most significant bit is 1
Therefore, (S2, S3, S4, S5, S6) = (1, 1, 1, 1,
1). If r = 0.001, the most significant bit is 0
Therefore, (S2, S3, S4, S5, S6) = (1,0,0,1,1)
0).

As described above, in the proposed example , the input weights of the adder circuit are 1/2, 1/4, 1/8, 1/16, 1/1.
6, a geometric progression having a common ratio of 1/2 is formed except for the last 1/16, the last weight is equal to the immediately preceding weight, and 1/16
Thus, a fixed-point number r representing a blend ratio in a certain range can be used as it is as a selection control signal of the selector, and a decoder for converting the input r into a selection control signal of the selector and outputting the same is added. Thus, even in a range where the fixed-point number r cannot be used as it is for the selection control signal of the selector, the selector can be controlled so as to operate correctly with respect to the value of the input r. Therefore, the proposed example operates correctly for all cases of the fixed-point number r representing the blend ratio.

[0105] (Fourth example of proposed weighted mean circuit) Hereinafter, with reference to the drawings, a fourth example of proposed weighted average circuit of the present invention will be described.

[0106] A fourth Hisage load averaging circuit 26 present invention
It is a block diagram of a Anrei. In the figure, 287-29
1 a first selector, 292 is a second selector, 601 is a de <br/> code Da. Note that the same components as those in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted. FIG. 27 shows a logic circuit diagram of the first selector, FIG. 28 shows a logic circuit diagram of the second selector, and FIG. 29 shows a circuit diagram of the decoder 601.

In FIG. 27, 293 to 318 are two-input AND circuits, 319 to 326 are three-input OR circuits,
7, 328 are inverters. In FIG.
354 is a two-input AND circuit, 355 to 362 are three-input OR circuits, and 363 and 364 are inverters.

The weighting of the adding circuit 201 is based on the first proposal.
Same as the example . Its output is a 12-bit, the Hisage
In the example , 8 bits are required as an output, and the lower 4 bits are truncated and input to the selector 292. Selector 28
7 to 291 receive the corresponding constant values C2 to C6 and the input signals A and B, and input the weights of the adder circuit 201 to the input signals A and B and the constant values. It operates to select and give one. Selector 292
Selects one of three values of the output (upper 8 bits) of the adder circuit 201 and the input signals A and B, and outputs the selected value.

In the decoder 601 shown in FIG.
602 is a 4-input OR circuit, and 603 is a 2-input OR circuit.

Next, the specific configuration and operation of the present load averaging circuit will be described.

When the selection control signal SC = 0, the selector 287
291 select one of the input signals A and B according to the respective selection control signals S2 to S6, and the selector 292 selects the addition circuit 2
Select output 01. Therefore, at this time, the operation of this circuit is the same as that of the conventional example, and the blend ratio α = S2 / 2 + S3 / 4 +
Calculation of synthesis by S4 / 8 + S5 / 16 + S6 / 16 αx A + (1-
α) Perform xB and output.

On the other hand, when the selection control signal SC = 1, the selectors 287 to 291 input the constant values C2 to C6 respectively input to the addition circuit 201. At this time, the selector 292 selects one of the input signals A and B according to the selection control signal SAB and outputs it. When SAB = 1, the input signal A
When = 0, B is output.

Next, the power consumption of the weighted average circuit of the present proposed example and the power consumption of the weighted average circuit of the first proposed example will be compared. As an assumption for calculating the power, both circuits use elements with very low DC power consumption, such as CMOS, for example, and the DC power consumption can be neglected. It is assumed that the value is consumed when the value is inverted at the output terminal (including). However, there is no transient inversion, and it is assumed that any output terminal is inverted at most once between the time when the input changes and the time when the next input changes, to obtain a correct value. The value of the power consumption is
Ignore the part that depends on the output load capacity for simplicity,
All terminals consume 25 (μW) per 1 (MHz).

The operating frequency is set to 20 (MHz), the blending ratio α is set to 1 in both weighted averaging circuits, and the control to output the input signal A is fixed. , 0,0,0,0,0,0,0) and (1,1,1,1,1,1,1,1) alternately.

In the weighted average circuit of the proposed example , when the blend ratio α = 1, the selection control signal SC is set to 1, and the output terminals of the logic gates inside the selectors 287 to 291 and the addition circuit 201 are all fixed. , And their power consumption becomes zero. Since only the outputs of the eight AND circuits and eight OR circuits corresponding to the path of the input signal A in the selector 292 are inverted for each pixel, the power consumption is 25 (μ).
W / MHz) x 20 (MHz) x 16 (pieces) = 8000 (μW) = 8
(mW).

In the load averaging circuit of the first proposed example , when the blend ratio α = 1, the values of the selection control signals S2 to S6 are all set to 1, and the selectors 355 to 359 all pass the input signal A. . Therefore, one selector selects the selector 29 described above.
Since the operation is the same as that of 2, the selector 3 consumes 8 (mW).
In the case of 55 to 359, a total of 40 (mW) is consumed. Further, inside the adder circuit 201, the outputs of all the full adders are inverted for each pixel except for the 4 bits of Σ [3: 0]. Full adder 28
There are a total of 32 output terminals 1 to 304 and 306 to 313, and there are 64 output terminals and 60 output terminals. Therefore, the power consumption is 25 (μW / MHz) × 20 (MHz) × 60. (
) = 30000 (μW) = 30 (mW). Therefore, the power consumption of the weighted average circuit of the first proposed example is 70 (mW) in total.

When the blend ratio α is a value between 0 and 1, the addition circuit 201 also operates in the weighted average circuit of the present proposal . Accordingly, in this case, the power consumption of the selector 292 (8 (mW)) is larger in the weighted average circuit of the proposed example than in the conventional example. When the input signal A is given under the above conditions and the input signal B is given so that B = A, the operation of the adding circuit 201 is such that the blend ratio α = 1
Therefore, the power consumption of the weighted average circuit of the proposed example is 70 + 8 = 78 (mW).

As described above, the weighted average circuit of the proposed example is
Similarly, when the blend ratio α = 1 and α = 0, the power consumption is extremely low as compared with the first proposed example . The control state of the blend ratio α = 1 is 1
If only pixels are maintained and switching is performed immediately, there is no effect of power consumption reduction, but such a use situation is rare, and even if the state of the blend ratio α = 1 is semi-fixed or switched, several hundreds are obtained. Since it is considered that the usage situation is normal for each pixel, the effect of reducing power consumption appears.

As described above, according to the proposed example ,
Instead of the selector of the weighted average circuit of the first proposed example , first selectors 287 to 291 which can be selected and input from the input signals A and B and a constant value are employed, and an addition circuit 201 is provided. Is provided and a second selector 292 for selecting and outputting one of the digital input signals A and B from the digital input signals A and B is provided. Without operating the circuit 201,
A load averaging circuit that reduces power consumption can be provided.

[0120] (Fifth example of proposed weighted mean circuit) Hereinafter, with reference to the drawings, a fifth example of proposed weighted average circuit of the present invention will be described.

[0121] Figure 30 is the fifth weighted average circuit of the present invention Hisage
It is a block diagram of a Anrei. In the figure, 232 is the first
Is a second partial addition circuit.
Note that the same components as those in FIG. 26 are denoted by the same reference numerals, and description thereof will be omitted. Also, the first partial addition circuit 2
FIG. 19 shows the internal configuration of the 32.

FIG. 31 is a block diagram of the second partial addition circuit 365. In the figure, 367 is the second of 4 bits.
368 is a first carry propagation adder that adds a 4-bit value and a 7-bit value, and 366 is 4
The third carry-propagating adder of bits, 369 is the sixth select
It is a vessel .

FIG. 32 is a circuit diagram of the second and third carry propagation adders 366 and 367. In the figure, reference numerals 370 to 373 denote 1-bit full adders.

FIG. 33 shows the first carry propagation adder 36.
8 shows a circuit configuration diagram of FIG. In the figure, 374 to 377
Is a 1-bit full adder.

The first carry propagation adder 368 performs addition on inputs and outputs from the least significant bit to a certain intermediate bit, and outputs a carry generated from the intermediate bit. The second carry-propagating adder 367 outputs a higher-order bit than an intermediate bit of the second partial adder circuit 232 when the carry of the first carry-propagating adder 368 is assumed to be 0. Addition is performed for input and output. Also, the third
The carry propagation adder 366 of the second case, when assuming that the carry of the first carry propagation adder 368 is 1,
The addition is performed for the input / output of the bits higher than the intermediate bit of the partial addition circuit 232 of FIG. Sixth selection means 369
Selects the output of the second carry propagation adder 367 if the carry value of the first carry propagation adder 368 is 0,
If the value of the carry is 1, the output of the third carry propagation adder 366 is selected and output.

The sixth selector 369 selects two systems of 5-bit binary numbers, and has a configuration obtained by removing the 3-bit circuit from the selector shown in FIG. . For example, from the circuit of FIG.
The third selector 369 can be configured by a circuit from which the two-input OR circuits 213 to 215 are removed.

Next, the specific configuration and operation of the weighted average circuit of the present proposal will be described.

This proposed example is based on the addition circuit 2 of the fourth proposed example.
The partial adder circuit 257 of 01 is replaced with a partial adder circuit 365, because it is exactly the same for the calculation function of the adder circuit, as in the fourth proposed example, the selection control signal
When SC = 0, the calculation αx A + (1-α) xB is performed. When the selection control signal SC = 1, one of the input signals A and B is selected and output by the selection control signal SAB, and SAB is output. = 1
, And B is output when SAB = 0.

[0129] Next, compare the weighted average circuit of the proposed example, the weighted average circuit of the first proposed embodiment.

Regarding the power consumption, the load averaging circuit of the present proposed example has the first and second parts when the blend ratio α = 1 and α = 0 as in the first proposed example. Since both inputs of the adders 232 and 365 are fixed, the power consumed by the selector 292 can be as small as 8 (mW).

On the other hand, when the blend calculation is performed with the blend ratio α between 0 and 1, both the first and second partial adders 232 and 365 consume power.
In this proposed example , the power consumption is slightly increased as the circuit amount is slightly increased compared to the first proposed example . Weighted average circuit of the proposed example, and four full adders than the first proposed embodiment, a single inverter, and 10 logical product circuits, the OR circuit 5 pieces of large, these output terminals Assuming that all the signals are inverted at 20 (MHz), there are 24 output terminals, so 25 (μW / MH
z) × 20 (MHz) × 24 (pieces) = 12000 (μW) = 12
(mW), and the power consumption of the entire weighted average circuit of the proposed example becomes 90 (mW).

Subsequently, the respective operation speeds are compared.

In the fourth proposed example , the addition circuit 20
The longest path inside 1 is, for example, from the input of the full adder 240 to each full adder 248, 256, 265, 264, 263,
262, 261, 260, 259, the full adder 2
In contrast, in the present example , the first partial adder 232 and the second partial adder 365 have the longest path, for example, the full adder From the input of 240, each full adder 248, 256, 37
7, 376, 375, 374, the sixth selector 3
Since the signal passes through one inverter, one AND circuit, and one OR circuit inside 29, the longest path in the weighted average circuit of the proposed example is 7 full adders, 1 inverter, and a logic circuit. One integrated circuit,
It consists of one OR circuit.

Since the propagation delay of the full adder is about 3 (ns) and the propagation delay of each of the other logic circuits is about 1 (ns), the output of each adder circuit is determined in the first proposed example. It takes about 33 (ns), but in the proposed example, it is about 24 (ns), and the calculation time can be reduced by about 9 (ns).

In the first proposed example , the maximum delay from the input signals A and B to the output is about 33 (ns) of the adder circuit 201 when performing the calculation of the synthesis through the adder circuit in the entire load averaging circuit. Approximately 37 (ns) by adding the delay time of the selector before and after
In the proposed example , the value is about 28 (ns).

[0136] Thus, towards the weighted average circuit of the proposed example, it is found that can operate up to a higher frequency than the first proposal example.

In the present proposal , the addition circuit 2 of the first proposal is used.
Since the second partial adder circuit 365 shown in FIG. 31 is used in place of the partial adder circuit 257 shown in FIG. 20 in FIG. 01, the calculation time of the adder circuit is reduced, and the high operating speed required for processing the video signal is reduced. Can be provided.

[0138] (Sixth example of proposed load averaging circuit) Hereinafter, with reference to the drawings sixth proposed embodiment of the weighted average circuit of the present invention will be described.

[0139] The sixth Hisage the load averaging circuit 34 according to the present invention
It is a block diagram of a Anrei. In the figure, 378 is the seventh
The selector 380 is selector of the eighth, 379 select the ninth
It is a vessel . The same components as those in FIGS. 30 and 31 are denoted by the same reference numerals, and description thereof will be omitted.

The internal structure of the first carry propagation adder 368 is as shown in FIG.

Second and third carry propagation adders 367 and 367
The internal configuration of 66 is as shown in FIG.

The internal structure of the seventh selector 378 is shown in FIG.
8 is the same as the logic circuit diagram of the selector shown in FIG.

The eighth selector 380 is connected to the seventh selector 37
Since the selection function is the same as 8 and the number of bits is reduced from 8 to 3, the internal configuration is such that five bits are deleted from the logic circuit of the selector shown in FIG.
For example, in FIG. 18, the AND circuits 222 to 231 and the OR circuits 211 to 215 are removed.

The ninth selector 379 is the first selector 28
7 to 291 with the same selection function and 8 to 5 bits
27, the internal configuration is such that three bits are deleted from the logic circuit of the selector shown in FIG. For example, in FIG.
01, with the OR circuits 319 to 321 removed.

Next, the specific configuration and operation of the weighted average circuit of the proposed example will be described.

When the selection control signal SC = 0, the selector 287
291 select one of the input signals A and B according to the respective selection control signals S2 to S6, the selector 380 selects the output of the carry propagation adder 368, and the selector 379 selects the output of the carry propagation adder 368. Carry carry adder 3
The output of either 67 or carry propagation adder 366 is selected.

Therefore, the carry propagation adders 366 to 368
And the selectors 379 and 380 combine to operate as a carry select adder, and the carry select adder sums and outputs the two outputs of the first partial adder circuit 232. Therefore, at this time, the operation of this load averaging circuit is the same as that of the conventional example, and the blend ratio α = S2 / 2 + S3 / 4 + S4 / 8 + S5 / 1
6 + S6 / 16 The calculation αx A + (1-α) xB is performed and output.

On the other hand, when the selection control signal SC = 1,
The selectors 287 to 291 are the constant values C2 to C6 respectively inputted.
Is input to the first partial addition circuit 232. The first partial adder 232 outputs a certain constant value irrespective of the input signals A and B, so that the carry propagation adders 366-3
68 also takes constant values for the input and output values.
The selector 380 selects and outputs the lower 3 bits of the selector 378, and the selector 379 selects and outputs the upper 5 bits of the selector 378. The selector 378 selects one of the input signals A and B according to the selection control signal SAB and outputs it, regardless of the selection control signal SC.

Therefore, when selection control signal SC = 1,
As an output of the weighted average circuit of the proposed example , an input signal A is output if SAB = 1, and an input signal B is output if SAB = 0.

As described above, the functions of the weighted averaging circuit of this proposed example are exactly the same as those of the fourth and fifth proposed examples .

Subsequently, the weighted average circuit of the proposed example and the fifth
The operation speed with the weighted average circuit of the proposed example will be compared.

In the weighted averaging circuit of the fifth proposed example , the longest path of the combined portion of the adder circuit 232 and the adder circuit 365 is, for example, from the input of the full adder 240 to the respective full adders 248, 256, 377, 376. , 375, and 374, and within the third selector 369, one inverter, one AND circuit, and one OR circuit. Therefore, seven full adders and one inverter , One AND circuit, one OR circuit
Individual.

Therefore, the longest path of the whole weighted average circuit of the fifth proposed example is composed of seven full adders, one inverter, and a logical unit including the adder 232 and the selectors before and after the adder 365. The signal passes through three product circuits and three OR circuits, and the delay time is about 28 (ns).

On the other hand, the weighted average circuit of the proposed example is
Two selectors 369, 2 of the weighted average circuit of the fifth proposed example
92 is removed and selectors 378 to 380 are added. In the longest path, a portion passing through the two selectors 369 and 292 is replaced with a portion passing through the selector 328. Accordingly, the longest path is shorter by one stage of the selector, and passes through seven full adders, one inverter, two AND circuits, and two OR circuits.

Therefore, the delay time in the proposed example is about 2 (n
s) is reduced to 26 (ns).

As described above, the weighted average circuit of the present proposed example can operate in a shorter time than the weighted average circuit of the fifth proposed example , and provides a weighted average circuit with a reduced calculation time. be able to.

[0157] (real施例load averaging circuit) Hereinafter, with reference to the drawings weighted average circuit of the actual施例of the present invention will be described.

[0158] Figure 35 is a block diagram of a weighted average circuit of the actual施例of the present invention. In the figure, 381 is a first adder (first adder), 382 to 385 are first selectors ( first selector), and 386 is a second adder (second adder).
Adders), 387 and 388 are second selectors ( second selectors), 389 to 393 are third selectors ( third selectors), and 394 are decoders (controllers). However, the fifth selectors 389 to 393 are divided into two types,
Selectors 389-392 are of the first type, the remaining selectors 393
Is a second type.

FIG. 36 shows an internal block diagram of the first adder circuit, and FIG. 37 shows an internal block diagram of the second adder circuit.
36 and 37, 396 to 402 denote carry save adders, and 195 denotes a carry propagation adder.

Here, signals having bit widths are connected in order from the one having the larger number of subscripts. For example, in FIG.
02 output OA [8: 1] is the input I1 of the carry save adder 401
A [7: 0], generally connected to OA [8]-I1A [7], OA
[7]-Connected as I1A [6], ....., OA [1]-I1A [0]. Of course, the bit width of the signals must be equal.

FIG. 38 shows the internal structure of the carry save adder.
FIG. 39 shows the internal configuration of the carry propagation adder.

In FIGS. 38 and 39, 403 to 409
And 412 to 418 are 1-bit full adders, 410 and 4
19 is a two-input AND circuit, and 411 and 420 are two-input exclusive OR circuits. FIG. 21 shows a truth table of the operation of the logic circuit of the 1-bit full adder.

FIG. 40 shows a logic circuit diagram of the first selector. The figure also shows the first type of logic circuit diagram of the third selector at the same time. In FIG. 40, 421 to 43
Reference numeral 6 denotes a two-input OR circuit, and reference numerals 437 to 444 denote two-input OR circuits.

FIG. 41 shows a logic circuit diagram of the second selector. In the figure, reference numerals 445 to 468 denote 2-input AND circuits, and 469 to 476 denote 3-input OR circuits.

FIG. 42 shows a second type logic circuit diagram of the third selector. In the figure, reference numerals 477 to 484 denote 2-input AND circuits.

FIG. 43 shows a logic circuit diagram of the decoder. In the figure, reference numerals 485 to 489 denote two-input OR circuits;
0 is a 3-input OR circuit, 491-500 are inverters, 50
1 to 513 are two-input AND circuits.

Next, the specific configuration and operation of the load averaging circuit will be described.

The carry-save adder of FIG. 38 inputs three 8-bit binary numbers, performs weighted addition of 2: 1: 1, and outputs the addition result in two bits of 8 bits and 9 bits. 2
Output in hexadecimal.

The carry propagation adder of FIG. 39 receives two 8-bit binary numbers, adds them with equal weights, and outputs the addition result as one 9-bit binary number.

The first adder circuit 381 is composed of one carry save adder and one carry propagation adder connected in cascade, so that 1/2, 1/4, 1
Six 8-bit binary numbers weighted to / 8, 1/16, 1/32, and 1/32 are input, added, and the sum is output. The sum of the weights is 1, and each weight 1/2, 1/4, 1/8, 1/16,
1/32 and 1/32 are a geometric progression having a common ratio of 1/2.

The weight of the output is the sum of the weights, that is, 1 and since it has a relationship shifted by 5 digits from the minimum weight of 1/32, the output has 13 bits.

The second adder circuit 386 cascade-connects three carry-save adders 400 to 402 to generate 5
Two binary numbers are input, weighted and added, and the sum is output as two binary numbers of 8 bits and 11 bits. Assuming that the output weight is 1/32, the input weight is 1/32, 1/64, 1/128, 1/256, 1/2, respectively.
56. 1/32, 1/64, 1/128, 1/2
Reference numeral 56 denotes a geometric progression having a common ratio of 1/2.

The first selector shown in FIG. 40 can select from three values of input signals A and B and a constant value 0. When the selection control signal SA = 1 and SB = 0, the output Y is Y =
A, the output Y when the selection control signals SA = 0 and SB = 1
Becomes Y = B, and when SA = SB = 0, the output becomes Y = 0.

The second selector shown in FIG. 41 can select one of the three values of the input signals A, B, and C (a constant value of 0 can also be selected, but is not used in this embodiment). ). Output Y when selection control signal SA = 1, SB = SC = 0
Becomes Y = A, and when the selection control signal SB = 1 and SA = SC = 0, the output Y becomes Y = B, and the selection control signal SC = 1 and SA = SB
When = 0, the output Y becomes Y = C.

In the selectors shown in FIGS. 40 and 41, the input patterns of the selection control signals SA, SB and SC are not given except for the above.

The selector shown in FIG. 40 may be used as the selector 393. However, since Y = A is not selected for the output Y, the circuit is simplified and the selector shown in FIG. 42 is used. Good. The selector shown in FIG.
When 1, the output Y becomes Y = B, and when the selection control signal SB = 0, the output Y becomes Y = 0.

As described above, not all selectors need a function of switching and selecting all input digital input signals. Like the conventional weighted average circuit, the blend ratio α realized by the combination of the selection control of the selectors
May be duplicated, and the selection function corresponding to the redundant portion (unused combination) may be removed, or the number of cases where the blend ratio α can be selected to reduce the amount of circuits, etc., may be reduced. In some cases, some selectors can reduce the number of selectable digital input signals to simplify the circuit.

The decoder 394 includes a code R and a signal AC.
C is input. The code R is a code for designating the blend ratio α. In this embodiment, a 9-bit binary fixed-point number (8 digits after the decimal point) is used. The signal ACC is a 1-bit signal that specifies the accuracy of the blend ratio.

The operation state of the weighted averaging circuit of this embodiment is classified according to the input to the decoder 394 when any of the following equations (7), (8) and (9) is satisfied.

R [8] = 1 (7) R [8] = 0 and {ACC = 0 or R [2] = R [1] = R [0] = 0} (8) R [8] = 0 and ACC = 1 and {R [2] = 1 or R [1] = 1 or R [0] = 1} (9) The operation in each case will be described below.

In the case of the equation (7), the outputs of the decoder 394 are SA2, SA3, SA4, SA5, SA7, SA8 = 1, and SB2, SB3, SB
4, SB5, SB7, SB8, SC7, SC8, SA9, SB9, SA10, SB10, SA11, SB11,
Since SA12, SB12 and SB13 = 0, the selectors 382 to 38
5, 387 and 388 select the input signal A, and the other selectors 389 to 393 select the constant value 0. Accordingly, the input signal A is guided to all inputs of the adder 381, and the calculation in the adder 381 is performed by A / 2 + A / 4 + A / 8 + A / 16 + A.
/ 32 + A / 32 = A, and the output is equal to the input signal A.
In this case, since the constant value 0 is given to all inputs of the second addition circuit 386, the operation of the second addition circuit 386 stops.

In the case of the above equation (7), the fixed-point number of R [8: 0] is 1 or more. However, if α> 1, no blend is defined. = 1
That is, if R [8] = 1, α = α regardless of the value of R [7: 0]
Calculate as 1.

In the case of equation (8), the output of the decoder 394 is SA2 =! , SB2 = R [7], SA3 =! , SB3 = R [6]
, SA4 =! , SB4 = R [5], SA5 =! , SB5 = R [4]
, SA7 =! , SB7 = R [3], SB8 = 1, SC7, SA
8, SC8, SA9, SB9, SA10, SB10, SA11, SB11, SA12, SB12, SB13 =
0 (however, “!” Indicates a unary operator instructing the inversion of the logic). In this case, for example, the selector 382 selects R
[7] controls to select either input signal A or B. When R [7] = 1, the output Y becomes Y = A, and R [7]
When = 0, the output Y becomes Y = B. Therefore, Y = [R
[7] xA + (1-R [7]) xB]. Similarly, selectors 383, 384, 385, 387 are controlled to select either input signal A, B by R [6], R [5], R [4], R [3], respectively. , Selector 3
88 selects the input signal B, and the selectors 389 to 393 select the constant value 0. Therefore, the selectors 382 to 385, 3
A value obtained by weighting and adding the outputs of 87 and 388 by the first adding circuit 381 is represented by the following equation (10). [R [7] xA + (1-R [7]) xB] / 2 + [R [6] xA + (1-R [6]) xB] / 4 + [R [5] xA + (1-R [5]) xB] / 8 + [R [4] xA + (1-R [4]) xB] / 16 + [R [3] xA + (1-R [3]) xB] / 32 + B / 32 (10) The above equation can be further transformed into the following two equations (11) and (12). [R [7] / 2 + R [6] / 4 + R [5] / 8 + R [4] / 16 + R [3] / 32] x A + [(1-R [7]) / 2 + (1-R [6]) / 4 + (1-R [5]) / 8 + (1-R [4]) / 16 + (1-R [3]) / 32 + 1/32] x B… (11) [R [7] / 2 + R [6] / 4 + R [5] / 8 + R [4] / 16 + R [3] / 32] x A + [1- (R [ 7] / 2 + R [6] / 4 + R [5] / 8 + R [4] / 16 + R [3] / 32)] xB (12) Therefore, the blend ratio α = R [7] / 2 + R [6] / 4 + R [5] /
Assuming 8 + R [4] / 16 + R [3] / 32, the output is αx A + (1-
α) × B.

Therefore, in the case of the above formula (8), R [7:
3], 32 kinds of blend ratios can be specified in the range of 0 / 0.96875 in 1/32 = 0.3125 steps. In other words, in the case of Equation (8), the blend ratio is a fixed-point binary number, where the integer part is 0 and the decimal part is 5
Matches if it can be expressed in digits or less. R [2: 0] is ignored (it may be considered truncated). At this time, the second
The constant value 0 is given to all inputs of the adder circuit 386, so that the operation of the second adder circuit 386 is stopped.

In the case of equation (9), the output of the decoder 394 is SA2 =! , SB2 = R [7], SA3 =! , SB3 = R [6]
, SA4 =! , SB4 = R [5], SA5 =! , SB5 = R [4]
, SA7 = SB7 = SA8 = SB8 = 0, SC7 = SC8 = 1, SA9
=! , SB9 = R [3], SA10 =! , SB10 = R [2], SA11
=! , SB11 = R [1], SA12 =! , SB12 = R [0], SB13 =
It becomes 1. Therefore, the selectors 382 to 385 are controlled to select either the input signal A or B by R [7: 4],
The selectors 387 and 388 select C (the output of the second adder circuit 386), and the selectors 389 to 392 are controlled to select one of the input signals A and B by R [3: 0]. 393 selects the input signal B. Second adder circuit 386
Are input to the first adder circuit 381 via the selectors 387 and 388, so that these four components can be regarded as one adder circuit, and 1 /
2, 1/4, 1/8, 1/16, 1/32, 1/64,
It can be regarded as an adder circuit that inputs and adds nine 8-bit binary numbers weighted to 1/128, 1/256, and 1/256 and outputs the sum (strictly speaking, the output 16-bit data). The lower 3 bits are truncated to 13 bits. If output without truncation, the function is completely equivalent.) Selectors 382 to 385, selector 389
Since the outputs of で 393 are summed by the above weighting,
The output of the first adder circuit 381 is as shown in the following equation (13). [R [7] xA + (1-R [7]) xB] / 2 + [R [6] xA + (1-R [6]) xB] / 4 + [R [5] xA + (1-R [5]) xB] / 8 + [R [4] xA + (1-R [4]) xB] / 16 + [R [3] xA + (1-R [3]) xB] / 32 + [R [2] xA + (1-R [2]) xB] / 64 + [R [1] xA + (1-R [1]) xB] / 128 + [R [0] xA + (1-R [0]) xB] / 256 + B / 256 (13) This equation can be further transformed into the following equations (14) and (15). [R [7] / 2 + R [6] / 4 + R [5] / 8 + R [4] / 16 + R [3] / 32 + R [2] / 64 + R [1] / 128 + R [0] / 256] xA + [(1-R [7]) / 2+ (1-R [6]) / 4+ (1-R [5]) / 8+ (1-R [4] ) / 16 + (1-R [3]) / 32+ (1-R [2]) / 64+ (1-R [1]) / 128+ (1-R [0]) / 256 + 1 / 256] x B ... (14) [R [7] / 2 + R [6] / 4 + R [5] / 8 + R [4] / 16 + R [3] / 32 + R [2] / 64 + R [1] / 128 + R [0] / 256] xA + [1- (R [7] / 2 + R [6] / 4 + R [5] / 8 + R [4] / 16 + R [3] / 32 + R [2] / 64 + R [1] / 128 + R [0] / 256)] xB (15) Therefore, the blend ratio α = R [7] / 2 + R [6] / 4 + R [5] /
8 + R [4] / 16 + R [3] / 32 + R [2] / 64 + R [1] / 128 + R
[0] / 256, the output is αx A + (1-α) × B.

Therefore, in the case of the above formula (9), R [7:
0], the blend ratio α is 0.00390625
You can specify 1/256 = 0.00390625 as the minimum step size in the range of ~ 0.99609375. Although there are always 255 cases when the interval is always assumed to be 1/256, there are 224 cases since the case of the equation (8) is excluded. In other words, the expression
In the case of (9), the blending ratio is equal to the case where the integer part can be represented by a fixed-point binary number of 0 and the decimal part can be represented by 6 digits or more and 8 digits or less. At this time, the second adder circuit 386 also operates, contributing to the realization of a blend ratio with a fine precision.

Next, the load averaging circuit of this embodiment and the first
We compare the power consumption of the proposed example with the accuracy of the blend ratio with the weighted average circuit expanded.

The load averaging circuit of the first proposed example sets the minimum step size of the blend ratio α to 1/256 =
It must be extended to 0.00390625. FIG. 44 shows a block diagram of the expanded weighted average circuit of the first proposed example . In FIG.
15 to 523 are selectors. The selector is similar to that shown in FIG.

The internal block diagram of the adder circuit 514 is shown in FIG.
Shown in In the figure, 523 to 531 are carry save adders, and 524 is a carry propagation adder.

In the load averaging circuit of FIG. 44, the value of the blend ratio α is 1/256 in the range of 0 to 1 as in the present embodiment.
= 0.00390625 You can specify 257 patterns in increments.

As a presumption for calculating the power consumption, it is assumed that both the load averaging circuits use very low DC power consumption elements such as CMOS, for example, and that the DC power consumption can be ignored. (Including full adders) when the value is inverted at the output terminal.
However, there is no transient inversion, and it is assumed that any output terminal is inverted at most once between the time when the input changes and the time when the next input changes, to obtain a correct value. The value of the power consumption is 25 (μ) per 1 (MHz) at any terminal, ignoring the part that depends on the output load capacity for simplicity.
W).

The operating frequency is set to 20 (MHz), and the signals (S1 to S9, R, ACC) are fixed so that both weighted average circuits have the blend ratio α = 1 and output the value of the input signal A as it is. And

The input signal A is a pattern that consumes the maximum power under the above assumption (0,0,0,0,0,0,
It is assumed that (0,0) and (1,1,1,1,1,1,1,1) are input alternately for each pixel.

In the load averaging circuit of the present embodiment, the blend ratio α = 1 is realized in the case of the above equation (7). At this time, the selectors 382 to 385, 387, and 388 select the input signal A, and the selectors 389 to 393 select the constant value 0. Therefore, the selectors 382 to 385, 387, 38
The output of 8 and the upper 8 bits of the output of the first adder 381 are inverted for each pixel, and the outputs of the selectors 389 to 393 and the output of the second adder 386 remain constant at 0.

In each of the selectors 382 to 385, 387, and 388, the outputs of eight AND circuits and eight OR circuits that correspond to the path of the input signal A are inverted for each pixel.

The inside of the first adder 381 is composed of four carry save adders and one carry propagation adder, and each block is a 1-bit full adder 7.
, One AND circuit, and one exclusive OR circuit. In the above-mentioned operation state, all outputs other than the exclusive OR circuit are inverted for each pixel.
Five outputs are inverted.

Therefore, the number of outputs to be inverted is 16
(Per selector) x 6 + 15 (per adder block)
× 5 = 171, and the power consumption is 25 (μW / MHz) × 2
0 (MHz) × 171 (pieces) = 85500 (μW) = 85.5
(mW).

On the other hand, in the extended weighted average circuit of the first proposed example , the blend ratio α = 1 is realized by:
(S1, S2, S3, S4, S5, S6, S7, S8, S9) = (1,1,1,1,1,1,1,1,1)
In this case, the outputs of the selectors 515 to 523 are inverted for each pixel.

The inside of the adder circuit 514 is composed of a block of seven carry save adders and one carry propagation adder.

Since the number of inverting outputs in the selector and the adder block is the same as that of the proposed example , the number of inverting outputs is 16 (per selector) × 9 + 15 (per adder block). × 8 = 264, and the power consumption is 2
5 (μW / MHz) × 20 (MHz) × 264 (pieces) = 13200
0 (μW) = 132 (mW).

Thus, when the blend ratio α = 1,
The maximum power consumption is 132 for the weighted average circuit of the first proposed example.
(mW), whereas the weighted average circuit of this embodiment is 85.
5 (mW) and 46.5 (mW) less.

Next, consider the power consumption when the blend ratio α is not 1. In this case, the one giving the maximum power consumption as an input is a signal equal to the input signals A and B,
This is the case where (0,0,0,0,0,0,0,0) and (1,1,1,1,1,1,1,1) are alternately input for each pixel.

In the extended weighted average circuit of the first proposed example , the above blend ratio α =
As in the case of 1, power consumption of 132 (mW) is consumed. This is because the number of outputs to be inverted is the same, only the signal path in the selector is different.

In the load averaging circuit of this embodiment, a difference occurs between the case of the equation (8) and the case of the equation (9).

In the former case, the selectors 382 to 385, 38
7, 388 select the input signal A or B,
To 393 select the constant value 0, and the second adder circuit 386
Is stopped, so that 85.5 (mW) of power is consumed as in the case where the blending ratio α = 1.

On the other hand, in the latter case, selectors 389-39
Since the third and second adder circuits 386 also operate, their power consumption must be added.

The number of inverted outputs of these added parts is 16 (per selector) × 4 (selectors 9 to 12)
+8 (selector 13) +15 (per adder block) x 3
= 117, and the increasing power consumption is 25 (μW / MHz) ×
20 (MHz) × 117 (pieces) = 58500 (μW) = 58.
Since this is 5 (mW), the power consumption of the weighted average circuit of this embodiment in this case is 85.5 + 58.5 = 144 (mW).

When the maximum power consumption is repeated, it is 132 (mW) regardless of the blend ratio α in the extended circuit of the first proposed example. In the weighted average circuit of this embodiment, the selectors 389 to 393 are used. Equations (7) and (8) for selecting a constant value (that is, the second adder circuit 386 does not operate) are 85.5 (mW), and the selectors 389 to 393 select the input signal. (The second addition circuit 386 operates)
In the case of (9), it is 144 (mW).

As described above, the load averaging circuit of this embodiment is
When the blend ratio can be expressed by a fixed-point binary number and up to five digits after the decimal point, about 2/3 of the power consumption (compared to the extended weighted average circuit of the first proposed example ) Maximum value). If the number of digits after the decimal point is 6 digits or more and it is necessary to add a fine weight, the power consumption (maximum value) is increased by less than 10% compared with the conventional circuit. Therefore, it is desirable to set the blend ratio to five decimal places.

Also, when the operation / pause state of the second addition circuit 386 is switched for each pixel or at a speed close to that, power is consumed by the switching operation of the circuit at the time of switching.
The effect of low power consumption in the idle state is lost and should be avoided.

When used for translucent synthesis of an image, switching of the blend ratio is often performed every several hundred pixels even at the maximum speed. In this case, the effect of reducing power consumption is not lost as described above.

Since it is difficult to accurately perceive and recognize the value of the blend ratio to a fine precision by human vision, there is no problem in using a value that can be expressed with up to five decimal places when the blend ratio is fixed.

Since human vision is sensitive to a change in the blend ratio (and, consequently, a change in the image), if the width of the step of setting the blend ratio is not narrow, it is difficult to change the value of the blend ratio. The screen flickers.

For example, when the blend ratio is changed by expressing it to five digits after the decimal point, the minimum step size is 1/32. However, when the contrast of the images of the input signals A and B is clear, for example, When the blend ratio changes, the screen flickers and the stage of the change is perceived. If the blending ratio is expressed using up to eight decimal places and changed with the minimum step size, the blending rate changes by 1/256, and the screen changes smoothly and the screen flicker is not perceived.

Therefore, the second addition circuit 386 operates only in a transitional state when the blend ratio is changed, and if the blend ratio with a fine precision is realized, the change of the screen due to the change of the blend ratio is possible. Can be perceived smoothly. If the operation of the above equation (9) is performed only in such a case, the second adder circuit 3
The effect of low power consumption can be exhibited by reducing the appearance frequency of the state in which the 86 operates and increasing the time ratio of the state with low power consumption.

In this embodiment, the input signal ACC is supplied to the decoder 394, and the stop of the second adder circuit 386 is instructed by this signal ACC. However, R [2] = R [1] = R
[0] = 0, control can be performed. Therefore, when control by the input signal ACC is not performed, ACC = 1
As a result, a redundant circuit (that is, the logical product circuit 313) can be removed.

In this embodiment, the first adder 381
And the second adder circuit 386 are divided into two.
Needless to say, it may be divided into the above plurality.

As described above, according to the present embodiment,
When a plurality of small bit addition circuits are provided and the blend ratio can be realized by a sum of relatively large weights, for example, the value of the blend ratio can be expressed by a fixed-point binary number up to 5 digits after the decimal point. Since only a part of the adder circuits is used, and the remaining adder circuits can stop the operation and perform the blend calculation, the power consumption can be reduced.

In the above description, the decoder is used as the control means for inputting the blend ratio and generating the selection control signal for each selector. However, the present invention is not limited to this. For example, it may be constituted by a ROM.
In this case, there is little variation in the delay time from when the blend ratio is input to when the selection control signal is output, and this is advantageous in that the maximum value of the delay time can be limited to a small value. Further, the control means may be constituted by a CPU and its software. In this case, if the CPU has sufficient processing capability, the amount of hardware can be reduced.

[0220]

As described above , claims 1 and 2 have been described.
2, according to the weighted average circuit of the invention of claim 3 and claim 4, wherein, by providing a plurality of adder circuits of small bits, if it can be realized by the sum of the blending ratios by a relatively large weight, the plurality of summing Since only a part of the circuits is used and the remaining adder circuit can stop the operation and perform the blend calculation, the power consumption can be reduced .

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image blending circuit in which window management is performed.

FIG. 2 is a diagram showing a function table of a data selector in FIG. 1;

FIG. 3 is a block diagram showing an internal configuration of the pixel blending device in FIG.

FIG. 4 is a circuit diagram showing an internal configuration of one load averaging circuit in FIG. 1;

FIG. 5 is a diagram showing an example of arrangement of first to third windows on a display screen of an information processing apparatus using the image blending circuit of FIG. 1;

FIG. 6 is a diagram showing a position of a window overlapping portion in FIG. 5;

FIG. 7 is a diagram showing an example in which a document is displayed in a first window and a symbol is displayed in a second window in FIG. 5;

8 is a diagram showing the storage contents of each means in the case of FIG. 7 where two pieces of information do not overlap on the display screen.

FIG. 9 is a diagram showing an example in which a document is displayed in a first window and a symbol is displayed in a third window in FIG. 5;

10 is a diagram showing the storage contents of each means in the case of FIG. 9 where two pieces of information partially overlap on the display screen.

FIG. 11 is a block diagram illustrating a configuration of another image blending circuit that performs window management.

FIG. 12 is a diagram showing a function table of a data selector in FIG. 11;

FIG. 13 is a diagram showing the storage contents of each means in the case of FIG. 7 where two pieces of information do not overlap on the display screen.

14 is a diagram showing the storage contents of each means in the case of FIG. 9 where two pieces of information partially overlap on the display screen.

FIG. 15 is a block diagram showing a configuration of still another window-managed image blending circuit.

16 is a diagram showing a table representing an example of storage contents of the window information storage device in FIG. 15 when there is no overlapping of windows.

FIG. 17 is a diagram showing a table representing an example of storage contents of the window information storage device in FIG. 15 when windows overlap;

FIG. 18 is a logic circuit diagram of a selector provided in the weighted average circuit in the first proposed example .

FIG. 19 is an internal block diagram of a first partial addition circuit provided in the weighted average circuit.

FIG. 20 is an internal block diagram of a second partial addition circuit provided in the weighted average circuit.

FIG. 21 is a diagram showing a truth table of the operation of the 1-bit full adder.

FIG. 22 is a block diagram of a weighted average circuit in the second proposed example of the present invention.

FIG. 23 is a logic circuit diagram of a circuit for performing zero rounding.

FIG. 24 is a block diagram of a weighted average circuit in a third proposed example of the present invention.

FIG. 25 is a logic circuit diagram of a decoder provided in the weighted average circuit.

FIG. 26 is a block diagram of a weighted average circuit in a fourth proposed example of the present invention.

FIG. 27 is a logic circuit diagram of a first selector provided in the load averaging circuit.

FIG. 28 is a logic circuit diagram of a second selector provided in the load averaging circuit.

FIG. 29 is a logic circuit diagram of a decoder provided in the weighted average circuit in the second proposed example .

FIG. 30 is a block diagram of a weighted average circuit according to a fifth proposed example of the present invention.

FIG. 31 is a block diagram of a second partial addition circuit provided in the load averaging circuit.

FIG. 32 is a block diagram of a 4-bit carry propagation adder provided in the weighted average circuit.

FIG. 33 is a block diagram of a carry propagation adder that adds values of 4 bits and 7 bits included in the weighted average circuit.

FIG. 34 is a block diagram of a weighted average circuit in a sixth proposed example of the present invention.

FIG. 35 is a block diagram of a weighted average circuit in the real施例of the present invention.

FIG. 36 is a block diagram of a first addition circuit provided in the weighted average circuit.

FIG. 37 is a block diagram of a second addition circuit provided in the weighted average circuit.

FIG. 38 is an internal configuration diagram of a carry save adder provided in the load averaging circuit.

FIG. 39 is an internal configuration diagram of a carry propagation adder provided in the load averaging circuit.

FIG. 40 is a logic circuit diagram of a first selector provided in the load averaging circuit.

FIG. 41 is a logic circuit diagram of a second selector provided in the load averaging circuit.

FIG. 42 is a logic circuit diagram of a third selector provided in the load averaging circuit.

FIG. 43 is a logic circuit diagram of a decoder provided in the weighted average circuit.

FIG. 44 shows a load obtained by expanding the load averaging circuit of the first proposed example.
It is a block diagram of an averaging circuit .

Figure 45 is an internal configuration diagram of a first adder circuit provided in the weighted average circuit.

FIG. 46 is a block diagram showing a first example of a conventional load averaging circuit.

FIG. 47 is a block diagram showing a second example of the conventional load averaging circuit.

FIG. 48 is a block diagram showing a third example of the conventional load averaging circuit.

[Explanation of symbols]

101 pixel position information supplying apparatus 10,103 image memory 104 pixel blending unit 105 counter 106 blending ratio buffers 107,133 data selector 108,134 attribute buffer 109 central processing unit 111 to 113 weighted average circuit 394 decoder (control hand stage) 381 first adder circuit (second first addition means) 382 to 385 first selector (first selecting means) 386 second adding circuit (second adding means) 387,388 second selector (second selecting means) 389 to 393 second 3 selector (third selecting hand stage)

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI G06T 11/00 100 G06T 11/00 100Z G09G 5/14 G09G 5/14 C (32) Priority date January 31, 1994 (Jan. 31, 1994) (33) Priority country Japan (JP) (56) References JP-A-3-163595 (JP, A) JP-A-3 JP-A-1444693 (JP, A) JP-A-1-136233 (JP, A) JP-A-3-75925 (JP, A) JP-A-63-145527 (JP, A) JP-A-1-205327 (JP, A) JP-A-5-100653 (JP, A) JP-A-4-220693 (JP, A) JP-A-4-256999 (JP, A) JP-B-3-74543 (JP, B2) JP-B-4-4 21891 (JP, B2) Interface, 16 [12] (December 1, 1990), CQ Publishing, P . 218-221 (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F ⁷ /38-7/54 G06F 17/10 G06F 3/14-3/153 G06G 5/14 G06T 3/00 G06T 11 / 00

Claims (4)

(57) [Claims] (1) i, j, m, n are integers of 2 or more;
Where j is a natural number, and a first set of signals composed of k signals expressed in i-ary and a second set of signals composed of jk (j> k) signals expressed in i-ary. , The j signals are multiplied by weights corresponding to the respective j inputs, the respective multiplication results are added, and the addition result is output as a signal expressed in i-ary. A first adding means for converting the digital input signal from the m digital input signals represented by the i-ary number to 1
And k first selecting means for selecting one of the signals, wherein the k signals selected by the k first selecting means are each used as the first set of signals in the first adding means. Is input, and n signals expressed in i-ary are input, the n signals are multiplied by weights corresponding to the respective n inputs, and the respective multiplication results are added. A second addition means for outputting the addition result as j-k signals expressed in i-ary, and j-k pieces corresponding to the second addition means, the corresponding second addition means being provided. A second selection means for selecting one of the output signal and the m digital input signals; j selected by the jk second selection means.
-K signals are input to the first adding means as the second set of signals, and n signals for selecting one from the m digital input signals and the constant value signal expressed in i-ary number third selecting means comprises a, each selected n signal is input to the second addition means by said n third selection means, given blend ratio, m-number of digital inputs A weight averaging circuit , comprising: control means for controlling said j selection means so as to mix signals at said given blend ratio . 2. A number of signals belonging to a second set (j-k) is weighted average circuit according to claim 1, characterized in that the 2. 3. The integer i is i = 2, and each weight of the first addition means is a first sequence in which the respective weights are arranged in descending order, except for the last term of the first sequence. , Form a geometric progression with a common ratio of 1/2, the value of the first term of the first sequence is 1/2, and the value of the last term of the first sequence is the value immediately before the last term. The weights of the last two terms of the first sequence are each multiplied by each of the two signals of the second set, and each weight of the second adding means increases its weight by The second numerical sequence arranged in order forms a geometric progression of a common ratio of 1/2 except for the last term of the second numerical sequence, and the value of the first term of the second numerical sequence is the first numerical value. 3. The weighted averaging circuit according to claim 2, wherein the value of the last term of the second sequence is equal to the value of the last term of the second series. 4. The integers j, m and n are respectively j = 6 and m =
4. The weighted average circuit according to claim 3 , wherein 2, n = 5 .