JP3211061B2 - Digital protection relay - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital protection relay, and more particularly to a digital protection relay suitable for converting an analog signal of a power system into a digital signal and performing a relay operation according to the digital signal.

[0002]

2. Description of the Related Art As an example of a conventional power system control / protection device, a digital relay device described in Hitachi Review Vol. 61, No. 11 is known. According to this,
As shown in FIG. 17, the input signal processing unit A includes an auxiliary transformer A
1, A2, analog filters A3, A4, sample hold circuits A5, A6, a multiplexer A7, and an analog-to-digital converter A8. The data processing unit D controls and controls the internal system. Central processing unit (CPU) for executing various operations on input data
D1, a RAM D2 serving as a work area and a data storage area of the CPU D1, and a ROM D storing a control program and an operation program of the CPU D1.
2, an input interface D4 for receiving input signals from the input section A and the setting panel B, and an output interface D for outputting a control signal obtained as a result of the operation to an output section.
5 is provided.

[0003] This digital relay device transmits current from a current transformer CT, a transformer PT, and the like disposed on the transmission line L.
A voltage signal is obtained, the signal is calculated according to a predetermined algorithm, and the presence or absence of an accident is monitored. And
For example, when an accident such as a ground fault occurs in the power transmission line L, the current and voltage signals that fluctuate due to the accident are received, and an operation is performed based on these signals to obtain an accident point. A signal that supports tripping is output.

[0004] As a power system control device to which this type of device is applied, a 946, 1987 IEEJ National Convention.
A voltage / reactive power control device as shown in P1200 to P1201 is known.

[0005]

In the above-mentioned prior art, the gain characteristic of the input filter for removing harmonics is not constant with respect to the frequency. There has been a problem that the detection accuracy of a physical quantity such as an effective value to be obtained is reduced.
In digital processing, the input signal from the power system was sampled at 620 Hz or 720 Hz (electrical angle of the fundamental wave 30 °), and the sampling cycle was relatively coarse. Therefore, it is necessary to perform processing such as interpolation calculation of a complicated algorithm to detect the effective value and the like of the AC signal, which increases the number of calculation units, increases the number of calculation units, increases the size of the device and reduces consumption. There has been a problem that an increase in electric power and an increase in cost are caused.

An object of the present invention is to provide a digital protection relay capable of processing a signal from a power system with high accuracy.

[0007]

In order to achieve the above object, the present invention provides a method for inputting a plurality of AC signals from a power system in a time-division manner.
Analog-to-digital conversion means for converting a signal obtained by sampling with force to a digital signal;
And a digital filter for performing filtering processing for each sampling period to the digital signal converted by the analog-to-digital conversion means, the difference in the analog-digital converting means
The sampling period is set to one of one cycle of the fundamental wave of the AC signal.
/ 24 or less, and set in the digital filter
The heart frequency corresponds to the system frequency and the center frequency
With the wave number as the center, the frequency before and after the center frequency
The frequency higher than the attenuation of the frequency lower than the center frequency
The attenuation of the wave number is large, and is twice as large as the center frequency.
The double and quintuple frequencies are set to zero and the digital
The filter coefficient of the total filter is
The digital protection relay device is set in accordance with the data coefficient .

According to the above means, to set the zero point frequency of the digital filter 2 times the system frequency, 3 times, 5 times
And the center characteristic as the attenuation characteristic of the digital filter.
Attenuation at higher frequencies than at lower frequencies
To increase the attenuation characteristics of the entire digital filter.
Since the attenuation on the side of
Even if the primary frequency fluctuates , low-order harmonics can be removed, which can contribute to higher accuracy of the protection arithmetic processing.
Furthermore, time-division processing of multiple AC signals
And filter each digital signal.
Therefore, it is possible to cope with an increase or decrease in the number of input points.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on embodiments.

(First Embodiment) FIG. 1 shows an overall configuration diagram of an analog input unit to which a digital signal processing device of the present invention is applied. The analog input unit takes in input signals such as voltage and current of a power system, performs predetermined input processing on the input signals, obtains desired physical quantities, and outputs the physical quantities to other control units and protection relay units. .

As shown in FIG. 1, an analog input unit according to the present embodiment includes a filter 101 for preventing aliasing errors of a plurality of channels, a sample-and-hold circuit (S / H) 102 of a plurality of channels of an all-channel simultaneous sampling method, Multiplexer (MPX) 103, analog / digital conversion (A / D) circuit 104, dual-port buffer memory 105 using dual-port random access memory (hereinafter abbreviated as DPRAM), timing generation circuit 106, unit It comprises an interface circuit 107 for synchronizing the analog unit with other units or other systems (such as input signals).

Further, a digital signal processor (hereinafter abbreviated as DSP) 100, the DSP 100
Program memory 108, dual-port data memory 109 using DPRAM, system bus interface
It comprises a face circuit 110, an interrupt generation circuit 111, and an abnormality detection circuit 112.

A signal line d is an interrupt generation signal for taking in data, and a signal line e is an abnormality notification and recognition signal (S
YS FAIL) to the system bus B1.

The buffer memory 105 and the DSP 10
0, the program memory 108, the dual-port data memory 109, the interrupt generation circuit 111 and the abnormality detection circuit 112 are connected to the local bus LB. Also,
The interrupt generation circuit 111 and the abnormality detection circuit 112
Are also connected to the system bus B1. Further, the dual port data memory 109 has a system bus interface.
It is connected to the system bus B1 via the face circuit 110.

Next, in the configuration of the present embodiment, the key
Component, DS that performs digital signal processing
The P (digital signal processor) will be described.

FIG. 2 shows a detailed diagram of the configuration of an embodiment of the DSP.

The DSP according to the present embodiment, as shown in the figure,
Address register 2 for addressing external memory
00, a data register 201 used as a parallel port, a data RAM 202, an m-bit × m-bit high-speed parallel multiplier 203, and an instruction ROM 20
4. ALU (Arithmetic Logic Unit) that performs addition and subtraction
205, a register 206 such as an accumulator, a control circuit 207 for controlling interruption of control signals (a, b, c, etc.) with the outside, and an internal bus 208 in the DSP.

The multiplier 203 multiplies the contents of the input signals A and B during one instruction cycle, and outputs the result C to the internal bus 208. The ALU 205 adds and subtracts the data from the internal bus 208 and the data in the register 206, and stores the result in the register 2
Write to 06. As is well known, the DSP is capable of performing a product-sum operation during one instruction cycle and being capable of performing pipeline processing.
It is characterized in that high-speed numerical operation of fixed and floating point data can be realized. As a result, input data relating to a large number of input points can be filtered in real time. In this regard, the processing speed is faster than that of a general-purpose microprocessor, which is preferable.

Here, FIG. 3 shows a detailed block configuration of a digital signal processing device which is a main part of the present embodiment. The processing in each block shown is realized by the above-described DSP 100, and in the present embodiment, processing for detecting a voltage effective value of a power system based on an input voltage signal is shown.

First, an outline of the processing of each unit will be described.
The digital filter 300 sequentially takes in the voltage signal Vi of the power system sampled and converted in a fixed cycle from the buffer memory 105, and removes a high frequency component and an offset component superimposed on the input signal Vi by filtering. It is supposed to.

In this embodiment, in order to increase the detection accuracy, the sampling period T of the input signal is set to a period equal to or smaller than 1/24 (electrical angle 15 °) of one cycle of the fundamental wave of the AC signal. .

Further, the filter characteristics are set so that a low-order harmonic of n times (n is an integer) of the fundamental wave becomes the zero-point frequency of the digital filter 300, whereby a large attenuation is provided for the low-order harmonic. Make sure you get the amount.

The next frequency detecting means 301 obtains the frequency of the filtered input voltage signal Vi by calculation. The gain correction means 302 in the next stage has gain correction data set based on the frequency / gain characteristics of the digital filter 300, and outputs a voltage filtered by a correction coefficient corresponding to the obtained frequency. The gain of the signal Vi is corrected.
The next peak value detecting means 303 detects the peak value of the gain-corrected voltage signal Vi, for example, every half cycle. The effective value calculating means 304 calculates an effective value from the detected peak value by calculation. The averaging processing means 305 at the next stage averages the effective values obtained every half cycle, for example, to further improve the detection accuracy. The effective value of the voltage signal Vi obtained in this manner is stored in the data memory 1.
09, etc. to control the power system and the data of the protection relay.
Used as a

Next, the processing contents of each block shown in FIG. 3 will be described in more detail.

First, the digital filter 300 will be described.

FIG. 4 shows a conceptual block diagram of a typical digital filter. FIG. 4A shows an IIR type (Infi
nite-extent Impulse Response) filter, (b) is F
This is an IR (Finite-extent Impulse Response) filter. In the reference numerals assigned to the respective parts in FIG. 3A, Xn is an input signal, 400 is a coefficient block, K is a gain coefficient, and A1, A2, B1, and B2 are filter coefficients. Reference numeral 401 denotes a delay block, which includes a block (Wn-1) that delays the signal Wn by one time of the cycle T and a block (Wn-2) that similarly delays the signal Wn by two times. 402 is an addition block, and Yn is filter output data.

As can be seen from the figure, in the structure of the figure, by appropriately setting the filter coefficients, the following equations (1), (2),
Various filters shown in (3), (4) and (5) can be realized.

(Low-pass filter)

[0029]

(Equation 1)

(Band pass filter)

[0031]

(Equation 2)

(High-pass filter)

[0033]

(Equation 3)

(Notch filter)

[0035]

(Equation 4)

(All-pass filter)

[0037]

(Equation 5)

On the other hand, among the reference numerals assigned to the respective parts in FIG. 4B, X'n indicates input data and Y'n indicates output data. 403 is a delay block, X'n-1 is a block delayed by one time, and X'n-2 is a block delayed by two times, as described above. Reference numeral 404 denotes a filter coefficient block in which filter coefficients A'0, A'1, and A'2 are set. 405 is an addition block. When this figure is represented by an arithmetic expression, it can be expressed by the following expression (6).

[0039]

(Equation 6)

As described above, in the present embodiment, DS
The input signal is filtered by a digital filter using P, and the filtering is repeatedly performed for each sampling period T based on a preset filter coefficient. Therefore, filter processing can be performed by software in a time-division manner according to the number of input points, and it is possible to cope with increase / decrease of the number of input points, change of characteristics, and standardization of a printed circuit board.

Further, since filtering can be performed without using an analog filter, factors such as the initial value deviation of elements such as resistors and capacitors, fluctuations in element values due to ambient temperature, and deterioration of elements due to aging, like analog filters, can be obtained. , And high precision and no adjustment can be achieved.

Also, since an external inspection circuit is unnecessary and can be handled by internal software, the manufacturing process can be greatly reduced, maintenance is not required, and the accuracy and cost of the protective relay device are reduced. The merits such as are very large.

Here, the frequency of the digital filter 300
FIG. 5 shows an example of gain characteristics. The grid frequency of the power grid
Filter center frequency f₀And the gain at that time is g₀
And In addition, a frequency that is n times (n is an integer) the system frequency
Is set to the zero point frequency of the digital filter. this
Can greatly attenuate low-order harmonics,
Characteristics with harmonics can be greatly improved compared to conventional products.
You. Note that the center frequency f ₀In the vicinity, the gain characteristic increases
It has a convex curve.
The voltage signal level of the filter output will fluctuate. this
The fluctuation is detected by the next frequency detecting means 301 and the gain correcting means 30.
It is corrected by 2.

The processing function and operation of the frequency detecting means 301 will be described with reference to FIGS. First, the voltage signal V
Is performed according to the procedure shown in FIG.

It is determined whether or not the change in the filter output signal (V) has undergone zero crossing (change from negative to positive) (step 600).

If there is no zero cross, the count is incremented (step 601).

This counter indicates the number of samplings in one cycle of the input signal.

After the zero crossing, it is determined whether or not it is the second time. That is, zero crosses for one cycle are detected (step 602).

If it is not the second time (if it is the first time), the data υ (t−1) one time before is set to V1 and the current data υ (t) is set to V2 (step 603). ).

Then, the counter is cleared (step 604). That is, as shown in FIG. 6 (c), the counter that has counted up for each sampling is set to 0, and the counter is counted up again from the time of zero crossing.

If the zero crossing is the second time, the data υ (k + t−1) one time earlier is set to V3, and the current data υ (k + t) is set to V4 (step 605). Then, the counter is cleared (step 604).

Using the positive and negative voltages V1, V2, V3, and V4 at the time of zero crossing, the number of samplings k within one cycle of the input signal, and the sampling cycle T, the frequency f is calculated by the following equation. Ask (Step 60
6).

[0053]

(Equation 7)

Where:

[0055]

(Equation 8)

[0056]

(Equation 9)

In order to determine the frequency of the input voltage signal Va with high accuracy, it is desirable that the sampling period T be as fine as possible, for example, a frequency that is at least 24 times the fundamental wave.
In this case, the processing of FIG. 3 including the digital filter processing is desirably realized by a DSP that enables high-speed processing.

Although the frequency detection method described with reference to FIG. 6 has been described with respect to a method in which a negative to positive zero cross is detected, the present invention is not limited to this, and a positive to negative zero cross or a method in which both are combined can be realized. it is obvious.

Here, the gain correction means 302 of FIG. 3 will be described with reference to FIG. FIG. 7 shows the system frequency on the horizontal axis and the gain on the vertical axis. A curve 700 indicated by a dotted line in the figure is a center frequency f of the digital filter 300.
_{This is} a frequency / gain characteristic near _zero . The gain of the center frequency f ₀ is g ₀ , the gain of the frequency (f ₀ −f ′) is g ₁ , (f ₀
+ F ') is g ₂ and the gain of (f ₀ + 2f') is g
₃ , the gain of (f ₀ + 3f ′) is g ₄ .

A broken line 701 in the figure is an approximate line for correcting gain characteristics. That is, by correcting the gain of the detected frequency to the center frequency f gain g ₀ o'clock _0, a correction function y for adjusting a constant gain, the formula shown below.

[0061]

(Equation 10)

As described above, the characteristics of the digital filter 300 are examined in advance to set a correction coefficient. Although the example shown in FIG. 7 is an example in which the frequency near the center frequency is divided into four equal parts, it is needless to say that it can be realized even if the frequency is unevenly divided into many sections. Furthermore, it can be realized not only by linear approximation but also by curve approximation.

By the above-described gain correction of the frequency characteristic, the input signal is corrected by the following equation.

[0064]

[Equation 11]

The calculation cycle of the frequency correction calculation is the same as or longer than the calculation cycle of the peak value detection calculation described later.

Next, the operation of the peak value detecting means 303 of FIG. 3 will be described with reference to FIG. FIG. 8A shows an input signal of the peak detection means 303, that is, an input signal V after gain correction. First, as shown in FIG. 8B, the peak values (Vm1 to Vm1) of the absolute values are detected from the data corresponding to the half cycle of the input signal V taken in. By the way, peak detection can be easily obtained only by comparing the level of an input signal. However, an error occurs because the peak is not an actual peak depending on the sampling phase, so the peak values are averaged.
Here, another embodiment of the peak value detecting method will be described with reference to FIG. Now, input signals that are input with the sampling period Δt interposed therebetween are respectively {a, υ
b, the input signals υa, υb and the peak value V
The relationship with p is represented by the following equation. Here, ω is the angular frequency of the input signal.

[0067]

(Equation 12)

[0068]

(Equation 13)

From the above equations (12) and (13)

[0070]

[Equation 14]

[0071]

(Equation 15)

Is obtained. Next, the equations (12) and (15) are respectively
To get the sum of them,

[0073]

(Equation 16)

Is obtained. Therefore, the peak value Vp can be calculated by the following equation.

[0075]

[Equation 17]

Note that the calculation cycle of the peak value Vp may be the same as the sampling cycle T of the input signal, but may be calculated with a longer cycle, that is, by thinning out the data.

Next, the processing and operation of the effective value calculating means 304 in FIG. 3 will be described. Peak value Vp obtained above
And the effective value Vrms have the following relationship, and the effective value Vrms is calculated based on this relationship.

[0078]

(Equation 18)

Then, the averaging means 305 in FIG.
An average value of the effective value Vrms obtained by the effective value calculating means 304 for a certain period is calculated and an average effective value is output.

As described above, according to the embodiment shown in FIGS. 1 and 3, the frequency of the filtered voltage signal is detected based on the frequency / gain characteristics of the digital filter, Is corrected, the peak value or the effective value can be detected from the voltage signal with high accuracy even when the system frequency fluctuates.

Further, by performing the processing by the DSP, the sampling period T of the input signal Va is set to 600 Hz (or 7 Hz).
20 Hz) or twice or more than 20 Hz), and the detection accuracy of the peak value or the effective value can be further increased.

Further, as described above, since the correction according to the frequency and gain characteristics of the filter is performed and the sampling period is shortened by using the digital signal processor, the interpolation operation of the complicated algorithm is not performed. Also, the effective value of the system voltage can be detected with high accuracy. As a result, a highly accurate input signal processing device can be realized without increasing the size. The detection accuracy is, for example,
５5% (12 samplings / 1 cycle) can be increased to 0.1% (60 samplings / 1 cycle).

Further, since the digital filter is applied, problems associated with the analog filter of the RC active filter composed of a resistor and a capacitor, such as variations in elements, temperature characteristics, deterioration of characteristics due to aging, and a large number of input channels The problem that characteristic variations occur between the two can be solved. As a result, the accuracy of the input filter can be improved, and the quantization error can be significantly reduced.

However, since the present invention does not essentially include a digital filter, the effect of the present invention by gain correction can be obtained even if the digital filter 300 in FIG. 3 is replaced with an analog filter.

The gain correction means 3 of the embodiment shown in FIG.
The correction of the gain corresponding to 02 may be incorporated anywhere as long as it is after the frequency detecting means 301 in the embodiment of FIG. For example, it may be inserted on the output side of the peak value detecting means 303 or the effective value calculating means 304.

Also, the DSP of FIG.
Although the description has been made on the assumption that 100 is used, it is apparent that the present invention can be realized by a general-purpose processor or a combination of a general-purpose processor and a coprocessor (floating point arithmetic processor). Moreover, the digital filter 300
Considering that filtering is performed with a short sampling period, a high-speed DSP is desirable. Therefore, the digital filter 300 and the frequency detecting means 301 can be realized by the DSP 100 in FIG. 1, and the processing after the gain correcting means 302 can be performed by a general-purpose processor in another unit.

(Second Embodiment) FIG. 9 shows a second embodiment of the present invention.
1 shows a block diagram of an embodiment. FIG. 9 shows only a portion corresponding to FIG. 3, and is a unit realized by the DSP 100 of FIG. The present embodiment differs from FIG. 3 in that the effective value is directly detected without detecting the peak value, and blocks having the same functions and configurations as those in FIG. Is omitted. 9 calculates the effective value Vrms according to the following equation (19). In the equation, VAaβ is shown in FIG.
(A) is an output voltage signal of the digital filter 300, where n indicates the number of times of sampling, and N indicates the number of sampling data used for calculation.

[0088]

[Equation 19]

FIG. 10B shows the change in the effective value Vrms obtained as described above. Further, the gain of the obtained effective value Vrms changes in accordance with the change of the system frequency, as shown by a line 1100 in FIG. The change in gain due to this frequency is corrected by the next gain correction unit 901 using the correction function indicated by the line 1101 in FIG. The correction process here is performed in the same procedure as in the embodiment of FIG. 3, but differs in that the present embodiment corrects the effective value Vrms. Considering that the gain correction is also originally required in the effective value calculation processing of FIG. 3, in the present embodiment, the gain correction is performed in accordance with the frequency gain correction of the digital filter after the effective value calculation. Possible, and the accuracy is improved. Further, since the effective value is directly obtained without detecting the peak value, there is an effect that the detection accuracy is high.

(Third Embodiment) FIG. 12 shows a third embodiment of the present invention.
13 shows a block configuration of another embodiment. This figure corresponds to FIG.
Only corresponding parts are shown, and the DSP 100 of FIG.
It is a means that is realized. In FIG.
Output means 303 to averaging means 305 are the same as those in FIG.
Therefore, the description is omitted. Difference between this embodiment and FIG.
Indicates that the frequency gain characteristics of the digital filter 1200 are different.
It is in the point. That is, the digital filter of the present embodiment is
The filter 1200 has a frequency gain characteristic diagram shown in FIG.
Adjust the filter calculation program and filter coefficients as
And the power system frequency fluctuation range (f ₀± Δf) gay
G₀Is adjusted to a fixed value.

Therefore, according to the present embodiment, FIG.
The frequency detecting means 301 and the gain correcting means 304 and 901 as in the embodiment shown in FIG. The characteristics shown in FIG. 13 are obtained by improving the characteristics of the digital filter described with reference to FIG. 4, and the filter processing operation becomes more complicated than that in FIG. And higher accuracy can be realized.

(Fourth Embodiment) FIG. 14 shows a configuration diagram of still another embodiment of the present invention. This embodiment is different from the embodiment shown in FIG. 9 in that the digital filter 1 shown in FIG.
200, and the same high accuracy as in the embodiment of FIG. 12 can be obtained.

The above-mentioned FIGS. 3, 9, 12, and 1
In each of the fourth embodiments, an example in which the digital filter 300 or 1200 is applied as an input filter has been described. However, as described above, an analog filter may be applied in the present invention. In this case, the output of the analog filter is sampled at high speed (for example, 24 times /
1 cycle), and after converting to a digital signal, performing the processing of each of the above embodiments to obtain the effective value of the voltage from the voltage signal, thereby compensating for the frequency and gain characteristics of the filter, and achieving a highly accurate voltage effective value. Can be detected.

(Fifth Embodiment) FIG. 15 is a block diagram showing an embodiment in which a signal processing device is applied to a voltage reactive power control device (VQ control device) according to the present invention. As shown in the drawing, the present embodiment device includes a Q detection block 1500 for detecting reactive power (Q), a setting block 1502 for setting an integration relay 1501 and a target value (Q ₀ , V ₀ ),
Voltage (V) detection block 1503, integration / instantaneous relay 1504, logic decision block 1505, on-load voltage regulation transformer (LR) control block 1506, power capacitor (SC) and shunt reactor (ShR) control block 1507.

In such VQ control, it is necessary to detect the voltage with high accuracy because the accuracy of voltage detection affects the control accuracy. Therefore, a voltage effective value detection device to which the signal processing device of each embodiment described above is applied is incorporated in the V detection block 1503 of this embodiment.

The operation of the embodiment configured as described above will be described with reference to FIG.

FIG. 16 shows an example of control characteristics of the VQ control device. In the control, first, a target voltage and a reactive power value are set, and the reactive power control device and the LR tap are controlled so as to conform to the target voltage and the reactive power value. . Generally, priority is given to maintaining the target voltage, and at the same time, power transmission loss is reduced. The operating principle is to follow a voltage and a reactive power flow pattern determined based on a certain prediction, and to perform a deviation from the actual one by adjusting and controlling a transformer tap, a power capacitor, and a shunt reactor.

For example, in FIG. 16, if the voltage / reactive power is in the region (A) (V → high, Q → many), the operation of lowering the LR voltage is performed. In the area (B) (V → high, Q →
If so, the SC is released and the ShR is input.
In the region (C) (V → low, Q → small), the operation of increasing the LR voltage is performed. In the area of (D) (V → low, Q → many), the SC is inserted and the ShR is opened. By such an operation, the voltage and the reactive power are maintained at the target values.

According to the present embodiment, since the effective voltage value can be detected with high accuracy, highly accurate voltage / reactive power control can be performed.

[0101] As described above, according to the present invention, twice the system frequency of the zero point frequency of the digital filter, 3
, 5 times and digital filter attenuation
Higher than the attenuation at frequencies below the center frequency
Increase the amount of attenuation of the
As the attenuation characteristic, the characteristic that the amount of attenuation on the high frequency side gradually increases and
Therefore, even if the system frequency fluctuates , low-order harmonics can be removed, and it is possible to contribute to higher accuracy of the protection arithmetic processing. In addition, time-sharing multiple AC signals
Process and convert to digital signals, and for each digital signal
Filter processing, so that the
I can respond.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of an analog input unit that is a signal processing device according to an embodiment of the present invention.

FIG. 2 is a detailed configuration diagram of the digital signal processor of the embodiment shown in FIG.

FIG. 3 is a block diagram of a voltage effective value detection according to a feature of the embodiment shown in FIG. 1;

FIGS. 4A and 4B are processing block diagrams of a digital filter, respectively.

FIG. 5 is a characteristic diagram illustrating an example of a frequency gain characteristic of a digital filter.

6A is a flowchart illustrating a frequency detection procedure, and FIG. 6B is a time chart illustrating a filter output and an operation of a counter.

FIG. 7 is a diagram illustrating an example of a gain correction function applied to a digital filter.

FIG. 8 is an operation waveform diagram of peak value detection.

FIG. 9 is a block diagram of a voltage effective value detection according to a characteristic part of another embodiment of the present invention.

FIG. 10 is a time chart for explaining the operation of the embodiment shown in FIG. 9;

11 is a diagram illustrating an example of a gain correction function according to the embodiment shown in FIG. 9;

FIG. 12 is a block diagram of a voltage effective value detection according to a feature of another embodiment of the present invention.

13 is a characteristic diagram showing an example of a frequency gain characteristic of the digital filter according to the embodiment shown in FIG.

FIG. 14 is a block diagram of a voltage effective value detection according to a feature of another embodiment of the present invention.

FIG. 15 is an overall configuration diagram of a voltage reactive power control device according to an embodiment to which the signal processing device of the present invention is applied.

16 is a diagram for explaining the operation of the embodiment shown in FIG.

FIG. 17 is an overall configuration diagram of a conventional digital relay device.

[Explanation of symbols]

 Reference Signs List 100: digital signal processor, 300: digital filter, 301: frequency detection means, 302: gain correction means, 303: peak value detection means, 304, 900: effective value calculation means, 305: averaging processing means, 901: gain effective Value correction means, 1200: Digital filter.

──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Junzo Kawakami 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Within Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Tadao Kawai 1-1-1, Kokubuncho, Hitachi City, Ibaraki Prefecture No. 1 In the Kokubu Plant of Hitachi, Ltd. (56) References JP-A-3-239113 (JP, A) JP-A-62-293923 (JP, A) (58) Fields investigated (Int. Cl. ⁷⁾ , DB name) H02H 3/02

Claims (1)

(57) [Claims] 1. A plurality of AC signals from a power system are time-divided.
Input, sample, and sampled signal
The provided analog-digital converting means for converting the digital signal, and a digital filter for performing filtering processing for each sampling period to the digital signal converted by the analog-to-digital conversion means, the analog-to-digital converting means
Sampling cycle of one cycle of the fundamental wave of the AC signal
Set to a period of 1/24 or less of the digital filter
And the center frequency of the
With the heart frequency as the center, frequencies before and after the center frequency
Higher than the attenuation of frequencies lower than the center frequency
High frequency attenuation and the center frequency 2
Double, 3x and 5x frequencies are set to zero and
The filter coefficient of the digital filter is
Digital protection relay set according to the filter coefficient .