JP3211234B2 - Information processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor based on VLSI technology, and more particularly to a microprocessor having a plurality of independent processing circuits inside to realize an improvement in execution performance by parallel processing. The present invention relates to a suitable information processing device. [Prior Art] Conventionally, the internal structure of a microprocessor has been discussed, for example, in "68000 Microcomputer (Maruzen, Microcomputer Series 14, 1983)", pp. 7-9. The internal structure of this microprocessor is roughly divided into an execution unit and an instruction control unit. Furthermore, the execution unit is composed of three units consisting of a register and an arithmetic circuit, each of which has two addresses and data.
They are connected by a 16-bit global bus. These two global buses are allocated for address and data, enabling parallel data transfer for each bus, and aiming to improve the efficiency of data transfer between arithmetic circuits and arithmetic. In addition, two switches are provided on each bus so that the buses can be separated, and by controlling these switches, data transfer between three units or
Data transfer is performed between a register and an arithmetic operation unit in each unit. The three units that make up the execution unit described above process the lower 16 bits of the address and the lower
Allocated to 16-bit processing, upper 16-bit processing of address and data. Therefore, these three processes can be performed in parallel. [Problems to be Solved by the Invention] The above-mentioned prior art divides data of 32 bits into the above 16 bits and lower 16 bits, and within the execution unit, a 16 bit width comprising a register and an arithmetic operation unit. The processing is performed using a plurality of units for processing the data, and the processing is performed in parallel with each other, thereby speeding up the processing of the 32-bit data. However, in recent years, with the progress of VLSI realization technology, it has become possible to realize a larger-scale and higher-speed circuit on one chip. As a result, there is no method of decomposing and processing data having a width of 32 bits or more, and a circuit for processing data having a single meaning on its own is provided on a single chip. It is possible to achieve processing efficiency higher than technology. Further, by providing a plurality of circuits that independently process data having one meaning and operating these circuits at the same time, it has become possible to achieve an improvement in processing efficiency by parallel processing. Considering such a situation, in the above conventional technology,
While having a plurality of circuits operating at the same time inside the microprocessor, at one time, they only realize processing of one piece of data having one meaning as described above. Also, since data transfer between each circuit is realized using a global bus,
There is a problem that it is difficult to simultaneously realize data transfer for supplying data necessary for each circuit to operate. The present invention has been made in view of the above circumstances, and an object of the present invention is to solve the above-described problems in a conventional information processing apparatus and to provide a single-chip microprocessor having a single meaning of data. An object of the present invention is to provide an information processing apparatus capable of efficiently realizing parallel processing by performing a plurality of processes simultaneously and data transfer for supplying data necessary for each process. [Means for Solving the Problems] An object of the present invention is to connect each circuit by a plurality of global buses for performing data transfer in an information processing device such as a microprocessor having a plurality of circuits. In addition, a local bus dedicated to the circuits is provided in a part between the circuits, and the operation of each of the plurality of circuits and the data transfer at the register transfer level in the plurality of buses including the local bus are related. This is achieved by performing processing using instructions consisting of fields that independently specify individual operations. [Operation] In the present invention, a plurality of circuits provided inside the microprocessor operate in parallel so as to realize processing of data having a single meaning. Here, the operations of the individual circuits described above are independently controlled, and the processing is scheduled and instructed by hardware, software, or firmware.
There is no malfunction. The local bus is used for data transfer between specific circuits, which occurs more frequently than other circuits. On the other hand, the global bus is connected to a plurality of circuits provided inside the microprocessor, and realizes data transfer between circuits having no local bus. There are a plurality of these buses, and data transfer between circuits realized by each is controlled independently by hardware, software, or firmware. As a result, a plurality of data transfers are realized at the same time, and data necessary for processing is simultaneously supplied to each circuit, so that no malfunction occurs. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows an embodiment of the present invention. FIG. 2 is a configuration diagram of a microprocessor having therein a circuit that performs processing on data having one meaning alone. In the figure,
1 denotes an execution control unit, 2 denotes an execution unit, and the execution unit 2
Is composed of a plurality of circuits 31 to 35 that perform processing on data having one meaning by itself. The operations of these circuits 31 to 35 are independently designated by the execution control unit 1 and the processing can proceed in parallel. The circuits 31 to 35 are connected by a plurality of global buses 10 to 12, and data can be transferred between various circuits via the global buses 10 to 12. On the other hand, in the processing of the entire execution unit 2, particularly between the circuit 32 and the circuit 34 where data transfer frequently occurs, and between the circuit 32 and the circuit 35.
Between local bus 21 and local bus 2
Two are provided. This makes it possible to perform data transfer using the local buses 21 to 22 in parallel with data transfer using the global buses 10 to 12. As a method of implementing execution control 1 for independently controlling the operations of the plurality of global buses 10 to 12 and the plurality of local buses 21 to 22 in the execution unit 2 described above, a microinstruction of a microprogram operates in each circuit. Can be specified independently, a method specified by a machine language instruction in software, or a method specified by hardware. According to the above embodiment, when the circuit groups 31 to 35 that perform processing on data having one meaning alone in the microprocessor perform parallel processing, supply of data necessary for the operation of each circuit 31 to 35 Is realized by efficient data transfer. FIG. 2 shows a register file 38, a pointer register group 36, and a dedicated adder in an internal structure of a microprocessor according to another embodiment of the present invention, which has a plurality of circuits whose operations are independently controlled. It is an explanatory view showing a part consisting of 37. In the figure, 13 to 15 indicate global buses, 23 to 25 indicate local buses described later, and 39 indicates a register file select. In the present embodiment, the register involved in the access is specified by storing the number assigned to the register in the register file 38 in the register file select 39. The pointer register group 36 holds a pointer that manages the flow of data in and out of the stack and queue on the register file 38 when the stack and queue are realized. Adder 37
Performs operations for updating the value of the pointer register group 36 and realizing various access methods of the register file 38 using the pointer register group 36 and the like. These circuits are connected to circuits (not shown) via global buses 13 to 15. By the way, the register file 38, shown in FIG.
Data transfer between the register file selct 39, the adder 37, and the pointer register group 36 is performed by these circuits,
The frequency of data transfer between these circuits and a circuit (not shown) connected via global buses 13 to 15 is higher. Therefore, the local bus 23 connects between the input of the adder 37 and the pointer register group 36, and the output of the adder 37 and the pointer register group 36, the register file 3
8 is connected by a local bus 24, and the output of the adder 37 and the inputs of the pointer register group 36, the register file 38, and the register file select 39 are connected by the local bus 25. According to the present embodiment, the adder 37, the pointer register group 36,
Frequent data transfer between the register files 38 can be realized by using the local buses 23 to 25. Therefore, between the circuits (not shown) via the global buses 13 to 15 or between those circuits and the adder described above. 37, the data transfer between the pointer register group 36 and the register file 38 can be executed in parallel, whereby the circuit groups 31 to 35 that perform processing on data having one meaning alone in the microprocessor are provided. Thus, there is an effect that the supply of data necessary for performing the processing is efficiently performed. Further, in the case where a large-capacity register file is provided in the microprocessor as in the present embodiment to improve the performance by reducing the frequency of accessing the external bus, the amount of internal data transfer becomes large as compared with others. Therefore, efficient data transfer inside the microprocessor is effective in improving performance. FIG. 3 shows another embodiment of the present invention, which is a data input register for controlling external bus access control in the internal configuration of a microprocessor having a plurality of circuits for processing data having one meaning alone. (DIR) 4
3, Data output register (DOR) 44, Address output register (AOR) 45, and ALU (Arithmetic Lo)
FIG. 4 is an explanatory diagram of a part including a gic unit 41 and a barrel shifter 43. In the figure, 16 to 18 indicate global buses, and 51 to 55 indicate local buses described later. In the external bus access, the writing process is realized by writing data in the data output register 44 and writing an address in the address output register 45, respectively, and designating a WRITE process. On the other hand, in the external bus access, in the read processing, the address is written in the address output register 45, the READ processing is designated, and when the bus cycle is completed, the data input register 43 is read.
This is realized by storing the data at the address specified in. The barrel shifter 42 performs a shift process on the input data with a designated arbitrary bit width. The ALU 41 performs arithmetic and logical operations on two input data. The above-described circuits are all connected to each other via global buses 16 to 17, and are also connected to a circuit (not shown), thereby realizing data transfer.
Furthermore, dedicated data local buses 51 to 54 are provided for data transfer between specific circuits related to processing frequently appearing in the execution of software, and thereby, between the other circuits via the global bus 16 to 17. Can be realized in parallel. Further, by providing the local bus 55 between the output and the input of the ALU 41, data transfer of intermediate results in continuous arithmetic and logical operations can be realized without passing through the global buses 16 to 18. By providing the local bus 51 from the output of the barrel shifter 42 to the input of the ALU 41, transfer of shifted data in arithmetic and logical operations using shifted data can be realized without passing through the global buses 16 to 18. Further, the barrel shifter 42 and the ALU4
By providing the local bus 52 for one input, in an arithmetic / logic operation using data obtained by an external bus cycle, transfer of the data can be realized without passing through the global buses 16 to 18. Similarly, by providing local buses 53 to 54 from the outputs of the ALU 41 and the barrel shifter 42 to the address output register 45 and the data output register 44, data transfer regarding a bus cycle for writing the operation result to the outside can be performed on the global bus.
It can be realized without going through 16-18. According to the present embodiment, data transfer between specific circuits related to processing that frequently appears in software execution is
By realizing using the dedicated local buses 51 to 54, data transfer between other circuits via the global buses 16 to 17 can be realized in parallel with it.
Data transfer for efficient parallel operation of a group of circuits within the microprocessor that performs processing on data having one meaning alone can be realized, and as a result, performance can be improved. Each of the above embodiments is merely an example of the present invention, and it goes without saying that the present invention should not be limited to these. [Effects of the Invention] As described above, according to the present invention, for example, in a single-chip microprocessor, parallel processing by simultaneously performing a plurality of processes on data having one meaning independently, The present invention has a remarkable effect that an information processing apparatus capable of efficiently realizing data transfer for supplying necessary data can be realized.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 to FIG. 3 are diagrams showing the internal configuration of a microprocessor according to an embodiment of the present invention. FIG. Diagram of a microprocessor having a plurality of circuits for performing
FIG. 3 is an explanatory diagram of a portion related to a register file unit in an internal structure of a microprocessor having a plurality of circuits whose operations are independently controlled, and FIG. 3 independently performs processing on data having one meaning. Of the internal configuration of a microprocessor with multiple circuits inside,
FIG. 3 is an explanatory diagram of a portion related to external bus access control. 1: Execution control unit, 2: Execution unit, 10 to 18: Global bus, 21
~ 25,51 ~ 55: Local bus, 31-35: Processing circuit, 36: Pointer register group, 37: Adder, 38: Register file, 4
1: ALU, 42: barrel shifter, 43: DIR, 44: DOR, 45: AOR.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-60-204036 (JP, A) JP-A-59-177655 (JP, A) JP-A-62-93734 (JP, A) JP-A-51- 40728 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 9/22 330 G06F 9/30

Claims (1)

(57) [Claims] An information processing system having a plurality of circuits, wherein the circuits are connected by a plurality of global buses for performing data transfer, and a local bus dedicated to the circuits is provided in a part between the circuits; In the apparatus, processing is performed using an instruction including a field that independently specifies individual operations of the plurality of circuits and individual operations related to data transfer at a register transfer level in the plurality of buses including the local bus. An information processing apparatus characterized by the above-mentioned. 2. The plurality of circuits include at least a register file unit, a pointer register group for managing selection of a register to be accessed in the register file unit, and an adder.
2. The information processing apparatus according to claim 1, wherein the information processing apparatus is provided between the register file and the pointer register group, and between the pointer register group and an input of the adder. 3. The plurality of circuits have at least an external access control unit, a barrel shifter, and an ALU, and the local bus is provided between the input and output of the external bus access control unit, the barrel shifter, and the ALU, and between the input and output of the ALU. The information processing apparatus according to claim 1, wherein the information processing apparatus is provided.