JP3213461B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming an alignment mark directly corresponding to an ion implantation step.

[0002]

2. Description of the Related Art A method of manufacturing a conventional semiconductor device will be described below with reference to the drawings. In order to manufacture a MOS transistor, a gate electrode (3) made of polysilicon is formed on a semiconductor substrate (1) made of p-type silicon or the like via a gate insulating film (2) as shown in FIG. Then, using the gate electrode (3) as a mask, an n-type impurity such as, for example, phosphorus ion (P +) is ion-implanted to form a source / drain region layer (4, 4) as shown in FIG.
5).

[0003]

By the way, in order to manufacture a medium-breakdown-voltage transistor having a breakdown voltage of about 12 V, which has been miniaturized to about a submicron, a high temperature of about 1000 ° C. after ion implantation is required in order to increase the withstand voltage of the drain. Requires an annealing step. However, according to the above-described conventional method for manufacturing a semiconductor device, since ion implantation is performed after the gate electrode (3) is formed, the profile of the impurity in the channel region in the depth direction is widened at the time of the annealing step, so that the transistor is not used. Since the problem that the punch-through characteristic is deteriorated occurs, it is not possible to manufacture a medium-breakdown-voltage transistor having a withstand voltage of about 12 V which is miniaturized to about a submicron.

To solve this problem, ion implantation may be performed before forming the gate electrode. However, in the ion implantation process, the resist film serving as a mark when the resist film is patterned and then removed is also removed. Therefore, it is not possible to form an alignment mark directly corresponding to the ion implantation process. For this reason, if the source / drain and the gate electrode are not self-aligned, it is necessary to achieve alignment accuracy between the source / drain and the gate electrode in the exposure step. Therefore, there has been a problem that it is difficult to achieve good accuracy.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional disadvantages. As shown in FIG. 1, a selective oxide film (12) is formed on a semiconductor substrate (11) to form a first oxide film. Forming first and second openings (14A, 14B) in the first resist film (13) after the formation of the resist film (13), and through the first opening (14A). A step of implanting ions into the semiconductor substrate (11) to form an ion-implanted region layer (15); and irradiating far ultraviolet rays as shown in FIG. 2 to cure the first resist film (13). Step and the second resist film (16) as shown in FIG.
After the formation, is selectively exposed and developed to remain on the ion-implanted region layer (15), and as shown in FIG. 5, the selective oxidation is performed using the first resist film (13) as a mask. The film (12) is etched and removed, and the second
In the region of the opening (14B) of the ion implantation region layer (1)
5) forming a positioning mark (17) corresponding to (5), thereby forming a positioning mark for ion implantation and performing accurate positioning in a subsequent step, and consequently, It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of manufacturing a transistor having a medium withstand voltage which is miniaturized to about a sub-micron, in which a gate electrode needs to be formed after forming an implantation region layer.

[0006]

According to the method of manufacturing a semiconductor device of the present invention, the first resist film (13) is cured by irradiating far ultraviolet rays as shown in FIG. 2 is selectively formed on the ion-implanted region layer (15), and as shown in FIGS. 5 and 6, the selective oxidation film (12) is formed using the first resist film (13) as a mask. ) Is etched and removed to form a positioning mark (17).

For this reason, it is possible to form the alignment mark (17) directly corresponding to the ion implantation step, and in the subsequent manufacturing process, the alignment may be performed based on the alignment mark (17). In addition, it is possible to perform the alignment directly corresponding to the ion implantation region layers (15, 18). This makes it possible to improve the accuracy of alignment between the ion-implanted region layer (15) and an ion-implanted region. For example, a gate electrode is formed between ion-implanted regions to form a MOS transistor. It is possible to form a gate electrode with high positioning accuracy even if there is a process of forming a gate electrode.

Therefore, it is possible to manufacture a medium-breakdown-voltage transistor having a breakdown voltage of about 12 V, which has been miniaturized to a submicron level, which cannot be conventionally performed because the gate electrode must be formed after the ion implantation step.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. (1) First Embodiment A method for manufacturing a semiconductor device according to a first embodiment of the present invention will be described below. The method for manufacturing a semiconductor device according to the present embodiment is a method for forming a positioning mark in an ion implantation step, which is a target for positioning in a subsequent forming step.

First, as shown in FIG. 1, a selective oxide film (12) is formed in a scribe region on a semiconductor substrate (11) made of p-type silicon, and a photoresist of about 1 μm is applied to form a first oxide film. The first and second resist films (13) are formed on the first resist film (13) by photolithography in a region into which ions are to be implanted later and a region for forming an alignment mark therefor. Opening (14A,
15A) is formed, and phosphorus ions are implanted into the surface of the semiconductor substrate (11) from the first opening (14A) under the conditions of a dose of 5.times.10@15 cm @ -2 and an acceleration voltage of 50 keV to form an ion-implanted region layer (15). Form.

Then, as shown in FIG. 2, the entire surface is irradiated with far ultraviolet rays having a wavelength of 250 nm and 750 mW / cm 2 for 60 seconds by increasing the temperature to cure the first resist film (13). Next, as shown in FIG. 3, a photoresist of about 1 μm is applied on the entire surface to form a second resist film (16). Next, as shown in FIG. 4, the second resist film (1
6) is exposed and developed to selectively remain in the ion implantation region layer (15). At this time, the first resist film (12)
Is hardened, so that it is not removed even when exposed to a developing solution, and maintains the original pattern.

Next, as shown in FIG. 5, using the cured first resist film (12) as a mask, the selective oxide film (12) is wet-etched with a mixed solution of hydrofluoric acid and fluorinated ammoacetic acid for about 120 seconds. A positioning mark (17) for ion implantation is formed on the selective oxide film (12). Next, as shown in FIG. 6, after performing plasma ashing, the first resist film (12) and the second resist film (16) are removed using sulfuric acid.

As described above, according to the method of manufacturing a semiconductor device according to the present embodiment, the first resist film (13) is cured by irradiating far ultraviolet rays as shown in FIG. As shown in FIG. 5, a second resist film (16) is selectively formed on the ion implantation region layer (15), and the first resist film (13) is used as a mask as shown in FIGS. The selective oxidation film (12) is etched and removed to form a positioning mark (17).

As a result, a positioning mark (17) directly corresponding to the ion implantation step can be formed, and in a subsequent manufacturing step, an exposure step or the like is performed based on the positioning mark (17). It is sufficient to perform the alignment, and the alignment can be performed directly corresponding to the ion implantation region. This makes it possible to improve the accuracy of the alignment between the ion-implanted region layer (15) and the one to be formed later.

In this embodiment, the alignment mark (17) is formed on the selective oxide film (12) formed in the scribe region. However, the present invention is not limited to this. The same effect can be obtained by forming an alignment mark (17) on the surface of the semiconductor substrate (11) in a region not directly affecting the device. (2) Second Embodiment A method for manufacturing a semiconductor device according to a second embodiment of the present invention will be described below. The method of manufacturing a semiconductor device according to the present embodiment is a method of forming a medium-breakdown-voltage transistor that is miniaturized to about a submicron using the alignment mark in the ion implantation step formed in the first embodiment. It is. The description of the same items as in the first embodiment will be omitted to avoid complication.

After forming the ion implantation region layers (15, 18) and the alignment marks (17) as shown in FIG. 6 by the same method as in the first embodiment, the ion implantation region layers (15, 18) are formed. ) So as to withstand a medium withstand voltage (12 to 15 V). The ion-implanted region layer (18) is composed of the ion-implanted region layer (15).
1 to 6 are formed at the same time when forming
Are not shown in FIG.

Next, as shown in FIG.
A), a polysilicon layer (20A) is sequentially formed, a resist film (not shown) is formed on the entire surface, and the alignment mark (1) is formed.
After exposing the resist film with a stepper or the like to develop 7), a resist pattern (not shown) is formed by development, and the polysilicon layer (20A) and the SiO2 film (19A) are etched and removed using the resist pattern as a mask. Then, as shown in FIG. 8, a gate insulating film (19) and a gate electrode (20) are formed between the impurity diffusion region layers (15, 18).

As described above, according to the method of manufacturing a semiconductor device according to the present embodiment, the alignment mark (17) directly corresponding to the ion implantation step can be formed. In the step of forming (20), alignment in an exposure step or the like may be performed based on the alignment mark (17), and alignment directly corresponding to the ion implantation region can be performed.

Therefore, the impurity diffusion region layers (15, 18)
After the formation of the gate electrode, it is possible to form the gate electrode (20) between the impurity diffusion region layers (15, 18) with high positioning accuracy. This makes it impossible to manufacture a medium-breakdown-voltage transistor with a breakdown voltage of about 12 V that has been miniaturized to about a submicron.

[0020]

According to the method of manufacturing a semiconductor device of the present invention, after the first resist film (13) is cured by irradiating far ultraviolet rays, the second resist film (16) is ion-implanted. The alignment mark (17) is formed selectively on the region layer (15) and etching and removing the selective oxide film (12) using the first resist film (13) as a mask.

For this reason, a positioning mark (17) for ion implantation directly corresponding to the ion implantation step is formed, and in a later manufacturing process of the semiconductor device, the positioning mark (17) is formed based on the positioning mark (17). All you have to do is
It is possible to improve the accuracy of the alignment between the ion-implanted region layer (15) and the one to be formed later.

[Brief description of the drawings]

FIG. 1 is a first cross-sectional view illustrating a method for manufacturing a semiconductor device according to first and second embodiments of the present invention.

FIG. 2 is a second cross-sectional view illustrating a method for manufacturing a semiconductor device according to first and second embodiments of the present invention.

FIG. 3 is a third cross-sectional view illustrating a method for manufacturing a semiconductor device according to first and second embodiments of the present invention.

FIG. 4 is a fourth sectional view illustrating the method for manufacturing the semiconductor device according to the first and second embodiments of the present invention;

FIG. 5 is a fifth sectional view illustrating the method for manufacturing the semiconductor device according to the first and second embodiments of the present invention;

FIG. 6 is a sixth sectional view illustrating the method for manufacturing the semiconductor device according to the first and second embodiments of the present invention;

FIG. 7 is a seventh sectional view illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 8 is an eighth sectional view illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention;

FIG. 9 is a first cross-sectional view illustrating a method for manufacturing a semiconductor device according to a conventional example.

FIG. 10 is a second cross-sectional view illustrating a method for manufacturing a semiconductor device according to a conventional example.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/027 G03F 9/00 H01L 21/266

Claims (3)

(57) [Claims] 1. A selective oxide film (1) on a semiconductor substrate (11).
2) forming a first resist film (13), and then forming first and second openings (14A, 14B) in the first resist film (13); Through the opening (14A) of the semiconductor substrate (1).
1) implanting ions into an ion-implanted region layer (15), irradiating far ultraviolet rays to cure the first resist film (13), and forming a second resist film (16). ), After exposing and developing to selectively remain on the ion-implanted region layer (15), and using the first resist film (13) as a mask to remove the selective oxide film (12). By etching and removing, in the region of the second opening (14B), the ion implantation region layer (15)
Forming a positioning mark (17) corresponding to the method (1). 2. After forming a first resist film (13) on a semiconductor substrate (11), the first resist film (1) is formed.
3) forming first and second openings (14A, 14B) in the semiconductor substrate (1) through the first openings (14A);
1) implanting ions into an ion-implanted region layer (15), irradiating far ultraviolet rays to cure the first resist film (13), and forming a second resist film (16). ), After exposing and developing to selectively leave on the ion-implanted region layer (15), and etching the semiconductor substrate (11) using the first resist film (13) as a mask. Removing the ion-implanted region layer (15) in the region of the second opening (14B);
Forming a positioning mark (17) corresponding to the method (1). 3. A selective oxide film (1) on a semiconductor substrate (11).
2) forming a first resist film (13), and then forming first and second openings (14A, 14B) in the first resist film (13); Through the opening (14A) of the semiconductor substrate (1).
1) implanting ions into an ion-implanted region layer (15), irradiating far ultraviolet rays to cure the first resist film (13), and forming a second resist film (16). ), After exposing and developing to selectively remain on the ion-implanted region layer (15), and using the first resist film (13) as a mask to remove the selective oxide film (12). By etching and removing, in the region of the second opening (14B), the ion implantation region layer (15)
Forming a positioning mark (17) corresponding to the following; and a gate insulating film (19) between the impurity diffusion region layers (15, 18) based on the positioning mark (17).
Forming a gate electrode (20) through the semiconductor device.