JP3214103B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device having a redundant fuse.

[0002]

2. Description of the Related Art Conventionally, an overcoat film formed on a semiconductor device has been formed by one or more whole-surface CVD films. However, as devices have been miniaturized, the space for upper-layer wiring, for example, Al wiring has become smaller, which has caused a problem that the coverage of the overcoat formed by the entire CVD film deteriorates.

[0003] SOG with good coatability as overcoat
However, in this case, as shown in FIG. 7, a shear stress is applied to the SOG film 3 as shown by an arrow A in FIG. 7, and the SOG film 3 is peeled off by this stress. There was a problem.

On the other hand, in a semiconductor device having a structure requiring a redundant fuse, typically a memory device, an opening is provided in the fuse to prevent heat storage when the fuse is cut, generally laser heat storage.

Therefore, a semiconductor device having a structure having a redundant fuse is required to have a structure capable of improving the above-mentioned problem of coverage of the overcoat and at the same time, preventing the heat storage when the fuse is cut. Is done.

[0006]

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems of the prior art, has good overcoat coverage, is resistant to overcoat film peeling due to stress, and has good flatness. An object of the present invention is to provide a method for manufacturing a semiconductor device having an overcoat excellent in moisture resistance and having a structure suitable for a structure requiring fuse cutting.

[0007]

SUMMARY OF THE INVENTION A semiconductor device according to the present invention is manufactured.
The fabrication method has the following configuration.

[0008] The method of manufacturing a semiconductor device of the present invention, a redundant
A method of manufacturing a semiconductor device having a configuration including a fuse.
To form an SOG on the wiring structure and etch the SOG
The SOG top and below the upper surface of the wiring structure and click, O
Form a bar coat layer and form an opening for wiring connection
And the opening on the fuse for redundancy is lower than that of SOG.
Is formed in a structure that comes down, an insulating film is formed and the entire surface is etched.
Back to open at least the redundant fuse.
Characterized by forming an insulating sidewall on the side wall at the mouth
A method for manufacturing a semiconductor device,
The purpose is achieved.

According to the present invention, the uppermost wiring (for example, Al wiring)
Using SOG smoothing, the formed SOG is entirely etched back to remove SOG on the wiring, and then an overcoat film is formed. After the wiring pad is opened in the overcoat film, P- The present invention can be implemented in a mode in which a sidewall is formed by SiN or the like.

[0010]

According to the present invention, since SOG is used, coverage can be improved. In addition, since the SOG has a separated structure, stress resistance is improved, and film peeling can be prevented.
This is because the stress is divided. The characteristics as flattening can also be fully exhibited. In addition, etch-off at the opening,
Alternatively, since SOG exposure is prevented by the sidewall, the moisture resistance is improved.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. Note that, needless to say, the present invention is not limited to the embodiments described below.

Embodiment 1 In this embodiment, the present invention is applied to an SRAM semiconductor device.

As shown in FIG. 1, the semiconductor device of this embodiment is a semiconductor device having a configuration in which a redundant fuse 1 is provided, and SOGs 3a to 3d are formed between wiring structures 2a and 2b. Reference numeral 3d denotes an isolated structure separated by the wirings 2a and 2b, an opening 4 is formed in the SOG at a corresponding position on the redundant fuse 1, and an insulating sidewall 5 is provided on a side wall of the opening 4. Are formed.

The semiconductor device of this embodiment is manufactured as follows. That is, the wirings 2a and 2b (see FIG. 2)
In between, an SOG coat 3 is formed (FIG. 3), and the SOG coat 3 is etched back so that the upper surfaces of the SOGs 3a ', 3c, 3d are lower than the upper surfaces of the wiring structures 2a, 2b (SiO 2 on the wirings).
_{When the} undercoat layer 20 such as ₂ or TEOS is present, the undercoat layer 20 (including the undercoat layer 20 and below) is formed (FIG. 4), the overcoat layer 6 is formed (FIG. 5), and wiring connection is established. And an opening 4 is formed on the redundant fuse by SOG.
3a to 3d are formed with a structure in which the bottom surface is below (FIG. 6)
An insulating film is formed and the entire surface is etched back to form an insulating sidewall 5 at least on the side wall of the opening on the redundant fuse, thereby obtaining the structure of FIG.

More specifically, in this embodiment, the following:
A semiconductor device was manufactured by the process.

A base interlayer film 10 is formed, and an Al wiring 2
a, 2b are formed by patterning into a fine structure having a submicron rule or less. Thus, the structure shown in FIG. 2 is obtained. In the prior art, the overcoat layer is
With the above connection, the coverage of the overcoat layer is deteriorated in the case of the fine rule of submicron or less.

P-SiO ₂ is formed by CVD at 100 to 4
The underlayer 20 is formed to a thickness of 00 nm. Further, SOG coating (400 to 600 nm thick on a flat wafer) is performed to form an SOG coating layer 3. That is, in order to improve the coverage of the overcoat layer, the smoothing of the underlying step by SOG is used. The underlayer 20
Because poor adhesion between the SOG and Al, before SOG coating is to that formed by the P-SiO ₂ for example TEOS-CVD or the like. SOG-Al
This is because the adhesion strength of OG-P-SiO ₂ and P-SiO ₂ -Al is higher. The resulting structure is shown in FIG.

The entire surface of the SOG coat 3 is etched back, and etching is performed until the SOG on the Al wirings 2a and 2b is removed. Next, P-SiO ₂ -CVD (100
nm) to form the adhesion layer 21. As a result, the structure shown in FIG. 4 is obtained.

The structure in which the SOG coat layer 3 is entirely etched back and separated between the wirings 2a and 2b (the separated 3
a ', 3c and 3d) for the following reasons. The adhesion strength of SOG-P-SiO ₂ is SO
It is higher than the adhesion strength of G-Al. However, even in the case of a large chip in which one side of the chip exceeds 15 mm, the stress due to the thermal stress applied to the semiconductor package is large, so that the film peels off at the SOG-P-SiO ₂ interface (the larger the chip size, the larger the chip size). , And the step stress increases toward the outer periphery of the chip (see FIG. 7). Accordingly Therefore, when using the SOG to the coverage improvement overcoat as in the present embodiment, the SOG and etching back the entire surface, by reducing the SOG-P-SiO ₂ contact area, the membrane is to prevent peeling .

P-SiN is formed by CVD.
A considerably thick overcoat layer 6 of about 0 nm to 1 μm
To form Thus, the structure shown in FIG. 5 is obtained.

The pad portion and the overcoat layer 6 in the fuse portion are removed by a resist patterning and etching technique. On the fuse portion, the SOG film 3a '
Also open. That is, after forming the overcoat layer 6, the bonding pad is opened to form the connection opening 40, and the fuse 1 is formed using the same resist pattern and mask pattern that can be opened during the etching step. Is also removed at the same time. When the fuse 1 is repaired with a laser, if the thickness of the coat layer on the fuse 1 is large, the amount of heat stored by the laser in that portion is large, and the film is cracked due to this, so that the film remains on the fuse 1. It is preferable to form the opening 4 by making the coat layer as thin as possible. Pad Al
Since the thickness of the coat layer (overcoat 6 and SOG 3b) on the fuse 1 is larger than the thickness of the coat layer on the (wiring 2b) (see FIGS. 5 and 6), the etching time is longer than that of the coat layer on the fuse 1. Set according to removal. Thus, the pad is overetched, but there is no problem since the pad Al has a selectivity of about 10 with respect to SiO ₂ etching. Even if the opening 4 on the fuse is over-etched as shown by the broken line in FIG.
Therefore, it can be set so that a sufficient opening 4 is formed.

Next, an insulating side wall 5 is formed. Here, the sidewalls 5 are formed by P-SiN (plasma silicon nitride).
Generally, in a semiconductor memory, the fuse 1 is formed using a first layer or a second layer poly-Si or the like. Therefore, the fuse 1 is in a lower layer than the Al wiring such as a pad in the vertical structure of the memory device. Since the fuse 1 is located below the pad Al, even if the SOG is etched back so that the SOG is not exposed on the side wall of the pad opening 40, the SOG may be exposed on the side wall of the fuse opening 4. When the SOG side wall is exposed, the SOG absorbs water through the exposed portion, and there is a concern that the SOG may swell and cause overcracks.

Therefore, in this embodiment, the P-SiN entire surface C
By performing VD (200 to 300 nm) and further performing overall etch back (equivalent to 250 to 350 nm),
This problem is solved by forming a P-SiN sidewall 5 and preventing the SOG sidewall from being exposed by the sidewall.

When the overcoat is smoothed by SOG, there is no effective means other than taking the configuration of the present invention to avoid the problem of SOG exposure.

That is, when the overcoat is smoothed by SOG, two places where the SOG is exposed at the opening are the pad opening 40 and the opening 4 of the fuse 1. However, the SOG is exposed at this part. The following means (1) to (4) are conceivable as the means for preventing. (1) a pad opening 4 0 protected by the sidewalls and protects the fuse on opening 4 at the side wall. (2) the pad openings 4 0 is removed by etching off the SOG, it is removed by etching off the SOG fuse on opening 4
You. (3) the pad opening 4 0 protected by the sidewalls are removed by etching off the SOG fuse on the opening 4. (4) a pad opening 4 0 is removed by etching off the SOG, to protect the fuse on opening 4 at the side wall.
(The present invention)

However, of the above means (1) to (4),
In (1), since the SOG cannot be formed into an isolated structure, the SOG is weak against stress and the SOG film is peeled off. In (2), flattening cannot be ensured. That is, using the means of (2), SOG
However, if the etch back is performed to the extent that it is not exposed in any of the openings 4 and 40, the etching must be performed to the extent that it is shallow and extremely small, and cannot serve as a flattening layer. In addition, (3) has a problem that it is weak against stress similarly to the above.

For this reason, desired effects and characteristics cannot be obtained except for the means of the present invention (4).

[0028]

According to the present invention, the effect of good coverage by SOG, the effect of improving stress resistance and preventing film peeling due to the SOG having an isolated structure, and the flatness are improved. Good effect and SO
Since the G exposure is prevented, the effect of improving the moisture resistance can be obtained.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a structure of a semiconductor device according to a first embodiment.

FIG. 2 is a diagram illustrating a manufacturing process of the semiconductor device according to the first embodiment (1).

FIG. 3 is a diagram illustrating a manufacturing process of the semiconductor device according to the first embodiment (2).

FIG. 4 is a diagram illustrating a manufacturing process of the semiconductor device of the first embodiment (3).

FIG. 5 is a diagram illustrating a manufacturing process of the semiconductor device of the first embodiment (4).

FIG. 6 is a diagram illustrating a manufacturing process of the semiconductor device of the first embodiment (5).

FIG. 7 is a diagram showing a problem.

[Description of Signs] 1 Fuse 2a, 2b wiring 3 SOG coat layer 3a to 3d Separated SOG 4 Opening on fuse 1 40 Connection opening on pad wiring 5 Insulating sidewalls 6a to 6d Overcoat layer

Claims (1)

(57) [Claims] 1. A method of manufacturing a semiconductor device having a redundant fuse, comprising: forming an SOG on a wiring structure; etching back the SOG so that the upper surface of the SOG is lower than the upper surface of the wiring structure; At least by forming a layer, forming an opening for making a wiring connection, and forming an opening on the redundant fuse with a structure in which the bottom surface is lower than SOG, forming an insulating film, and etching back the entire surface. A method of manufacturing a semiconductor device, comprising: forming an insulating sidewall on a side wall in an opening on a redundant fuse.