JP3215364B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a plurality of transistors including a power transistor, and more particularly to a measure for preventing deterioration of characteristics due to mutual interference between transistors.

[0002]

2. Description of the Related Art FIG. 8 is a circuit diagram showing an example of a speaker output circuit (hybrid integrated circuit) for a general audio device. As shown in the figure, the speaker output circuit includes a pair of complementary transistors connected in series to a pair of speakers. That is, the NPN transistor 3
2A and a circuit having a PNP transistor 33A are connected to the speaker 31A, and an NPN transistor 32B and a PN
A circuit having a P-transistor 33B is connected to the speaker 31B.

In such a speaker output circuit,
The output characteristics of the pair of speakers are required to be equivalent. Generally, when a power transistor is arranged in each of a plurality of circuits, a plurality of power transistors are individually connected and mounted on a substrate. This is because, when a plurality of power transistors are mounted on a common substrate, there is a possibility that thermal characteristics and breakdown voltage characteristics of each transistor constituting a circuit may be deteriorated due to current leakage and heat generation between the transistors. Therefore, when a plurality of circuits having the same output characteristics are required as in this example, transistors corresponding to the number of circuits required to have the same output characteristics are individually produced. NPN transistors whose characteristics are matched with each other are selected from among transistors.
By connecting an NP transistor in series, a plurality of circuits having the same characteristics as each other have been realized.

On the other hand, as disclosed in Japanese Patent Application Laid-Open No. 6-342876, a semiconductor device having a function of protecting an output transistor formed on a semiconductor substrate from thermal destruction is surrounded by output transistors. There has been proposed a semiconductor device in which a transistor for detecting the temperature of an output transistor is arranged in a region. In this semiconductor device, the output transistor and the temperature detection transistor through which a weak signal flows are electrically separated by a single impurity diffusion region (channel stopper) formed simultaneously with the emitter region of the transistor. ing.

[0005]

By the way, in recent years, high power and multi-channel audio output amplifiers have been demanded, and when the above-mentioned conventional speaker circuit is used, it is necessary to construct individual circuits. Therefore, in order to make the output characteristics of a plurality of circuits substantially equal, it is necessary to match the characteristics such as the electrical characteristics or the thermal characteristics of each of the transistors.

However, as in the above prior art,
It is not easy to match the characteristics of individually manufactured transistors according to the purpose, and it has been difficult to obtain a plurality of circuits whose manufacturing costs are increased and whose characteristics are sufficiently equalized.

Further, in a circuit used for audio speaker output, there is a problem that the size of the hybrid integrated circuit increases because transistors are individually connected.

On the other hand, in a semiconductor device having an output transistor having a thermal destruction prevention function disclosed in the above-mentioned conventional publication, an electrical isolation between the output transistor and the temperature detecting transistor separated by the channel stopper is provided. , There is a problem that the operation of one transistor is easily affected by the other transistor. In particular, in the operation of the temperature detection transistor,
There is also a problem that the output transistor and the semiconductor device are susceptible to external noise.

A first object of the present invention is to provide a semiconductor device which is individually controlled but has output characteristics substantially equal to each other by taking measures for ensuring electrical isolation between a semiconductor element and another region. A semiconductor device in which power semiconductor elements are provided on a common substrate, and a detection element and a signal control element that handle weak signals are provided on a common semiconductor substrate with those that handle large voltages and currents such as power semiconductor elements. An object of the present invention is to provide a semiconductor device.

[0010]

According to the present invention, there is provided a semiconductor device comprising:
A first conductive type substrate region, a separation band formed on the surface of the substrate region, and a second conductive region provided on the surface of the substrate region and sandwiching the separation band and spaced apart from each other; A first semiconductor region and a second semiconductor region of the first type, a third semiconductor region of the first conductivity type provided on the surface of the substrate region and surrounded by the first semiconductor region, and a third semiconductor region of the first conductivity type provided on the surface of the substrate region. And a fourth semiconductor region of a first conductivity type surrounded by the second semiconductor region, wherein the separation band is a second conductivity type of a second conductivity type extending rearward from a surface of the substrate region. 1 separation part, provided between the first semiconductor region and the first separation part, in contact with the first separation part, and separated from the first semiconductor region, from the surface of the substrate region to the back. A first second separation part of a first conductivity type extending to the second semiconductor; A first conductive type of first conductive type, which is provided between the first region and the first separation portion, is in contact with the first separation portion, is separated from the second semiconductor region, and extends rearward from the surface of the substrate region. 2 of the second separation unit
Thus, the first and second second separating sections are closer to each other than the first separating section.
It is formed shallow.

Thus, unlike the conventional structure having a single conductivity type separation structure, a so-called double conductivity type separation structure can be obtained, so that the semiconductor layers on both sides of the separation band are activated.
When a semiconductor element is formed as a region, the electrical isolation characteristics between the two semiconductor elements are improved, and element isolation can be performed such that each semiconductor element can operate independently.

[0012]

[0013] The first and second second separation portions of the separation zone are
By the both sides of the first separation portion sandwich the first separation unit, a double conductivity type structure is obtained at each part of the separation zone, the separation function increases. A semiconductor device characterized by the above-mentioned.

[0014] The substrate area includes two power vertical type
A collector region of the first and second transistors.
The second semiconductor region includes two power vertical bipolar transistors, respectively.
A base region of the third transistor and the fourth region.
The semiconductor area consists of two power vertical bipolar
An emitter region of a transistor, wherein
The isolation portion has a diffusion depth and an impurity concentration equal to or greater than each of the base regions, so that the isolation region can be formed by using an impurity introduction step when forming the base region of the power vertical bipolar transistor. Since the first semiconductor region can be formed, the manufacturing cost can be reduced.

The substrate area includes two power vertical type bipolars.
A collector region of the first and second transistors.
The second semiconductor region includes two power vertical bipolar transistors, respectively.
A base region of the third transistor and the fourth region.
The semiconductor area consists of two power vertical bipolar
An emitter region of a transistor, wherein
The second separation part and the second second separation part have substantially the same impurity concentration and diffusion depth as the above-mentioned respective emitter regions, so that the emitter region of the power vertical bipolar transistor is formed. Since the structure is such that the second semiconductor region of the separation band can be formed by utilizing the impurity introduction step, the manufacturing cost is reduced.

The substrate area includes two power vertical type
A collector region of the first and second transistors.
The second semiconductor region includes two power vertical bipolar transistors, respectively.
A base region of the third transistor and the fourth region.
The semiconductor area consists of two power vertical bipolar
An emitter region of the transistor, wherein the first and second
The lateral distance between the separation portion and the first semiconductor region is
Laterally between the second second isolation portion and the second semiconductor region;
By making the distances substantially equal to each other, the separation characteristics and the breakdown voltage characteristics of both power vertical bipolar transistors can be made substantially equal.

The substrate area includes two power vertical type
A collector region of the first and second transistors.
The second semiconductor region includes two power vertical bipolar transistors, respectively.
A base region of the third transistor and the fourth region.
The semiconductor area consists of two power vertical bipolar
An emitter region of the transistor, wherein the first and second
The separation part is the above two power vertical bipolar transistors
Of the power vertical bipolar transistor
Surrounding the box, the first and second separation sections and the one of the power
The lateral distance between the base region of the bipolar transistor and the power bipolar transistor
By being substantially constant over the entire circumference of the transistor, it becomes possible to make each power vertical bipolar transistor break down by the breakdown voltage value of each transistor itself, thereby improving the isolation and breakdown voltage characteristics of each semiconductor element. .

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a sectional view taken along line II-II shown in FIG. However, in FIG. 2, a plurality of electrodes and an insulating film above the semiconductor device shown in FIG. 1 are omitted.

In this embodiment, on a common semiconductor substrate,
A case where a pair of two vertical transistors having a common collector region is formed will be described.

As shown in FIG. 1, the semiconductor device has the following structure on a plane.

The semiconductor substrate 3 includes two NPN vertical bipolar transistors (first
A vertical bipolar transistor 1 and a second vertical bipolar transistor 2) are arranged. The semiconductor substrate 3 is, for example, doped with an N-type impurity (for example, boron) having a chip size of 3.3 mm × 3.3 mm, a thickness of 200 μm, and a concentration of about 5 × 10 ¹⁴ / mm ³ .

The first vertical bipolar transistor 1 has an N-type first emitter region 13, a P-type first base region 12 surrounding the first emitter region 13, and an N-type first base region 12 surrounding the first base region 12. And the first collector region 11 of the mold. Second vertical bipolar transistor 2
Similarly, the N-type second emitter region 23 and the second
A P-type second base region 22 surrounding the emitter region 23;
N-type second collector region 21 surrounding second base region 22
It is composed of The first and second emitter regions 13 and 23 of each of the vertical bipolar transistors 1 and 2
Have a portion close to the separation band 7 and a portion away from the separation band 7, and are arranged so that the portions close to each other as little as possible overlap each other. In other words, the two emitter regions 13 and 23 have a structure in which a part of a rectangle is missing in a plan view, and are arranged so as to be point-symmetric with respect to the center point of the semiconductor device.
On the other hand, the first and second base regions 12 and 22 of each of the vertical bipolar transistors 1 and 2 have a rectangular outer shape in plan view and outer peripheral portions thereof are line-symmetric with respect to the center line of the semiconductor device. Are arranged as follows. The dimensions of the first and second base regions 12 and 22 on a plane are, for example, about 3.1 mm in length and about 1.45 mm in width.

The separation zone 7 is formed between the base regions 12 and 2.
2 having a width of about 30 μm near the upper surface having substantially the same impurity concentration and diffusion depth as the same conductivity type as
And both emitter regions 1 formed on both sides of the first isolation portion 8.
3 and 23, the second isolation portion 9 having the same conductivity type and substantially the same impurity concentration and diffusion depth. The first separating portion 8 is formed on the upper surface of the semiconductor substrate 3 in a straight line from one side surface to the other side surface facing the semiconductor substrate 3 so as to cross the semiconductor substrate 3. In other words, the first separating section 8 is formed so as to divide the semiconductor substrate 3 into two in a plane. On the upper surface of the semiconductor substrate 3, each of the second separating portions 9 sandwiches the first separating portion 8 from both sides in the center of the semiconductor substrate 3, and surrounds the outer peripheral portions of the bipolar transistors 1 and 2, respectively. Is formed. In other words, each of the second separating units 9 includes the first and second
The collector regions 11 and 21 are formed so as to surround them, and the width of each portion is about 30 μm.

As shown in FIG. 2, the semiconductor device comprises:
A collector electrode 6 made of chromium, silver, or the like is formed on the lower surface of the semiconductor substrate 3 having the following structure in the cross section taken along the line II-II shown in FIG. The lowermost portion of the semiconductor substrate 3 close to 6 is an N + type common collector contact region 5. Also,
Above the common collector contact region 5, there is an N- type common collector region 4. Above the common collector region 4, a separator 7 and the first and second bipolar transistors 1, 2 Second base regions 12 and 22 and first and second emitter regions 13 and 23 are formed.
The common collector region 4 becomes the first collector region 11 near the first base region 12 and the second base region 22
Is the second collector region 21 in the vicinity of
There is no boundary between the first collector region 11 and the second collector region 21. The first and second base regions 12 and 22 are surrounded by first and second collector regions 11 and 21 in the substrate, and the first and second emitter regions 13 and 23 are formed by the first and second collector regions. It is surrounded by base regions 12 and 22. That is, each of the emitter regions 13 and 23
Is shallower than each of the base regions 12 and 22. The first and second base regions 12 and 22 have the same depth, and the first and second emitter regions 13 and 23 have the same depth.

On the other hand, on the upper surface of the semiconductor substrate 3,
First and second contacting second base regions 11 and 12
Base electrodes 14 and 24 and first and second emitter regions 1
First and second emitter electrodes 1 contacting 3, 23
5, 25 are formed. However, an insulating film is interposed between the substrate and each electrode except for a contact portion between each electrode and each region.

In the semiconductor substrate 3, the first separation portion 8 of the separation band 7 includes first and second base regions 12 and 2.
2 is formed to the same depth as the second, and the second separation portion 9
To the same depth as the emitter regions 13 and 23, that is, the first
The separation part 8 is formed deeper than each second separation part 9. Then, the first separation unit 8 at the back of the semiconductor substrate 3
Is about 60 μm (as described above, the width near the upper surface is 30 μm). In other words, only the first separation part 8 exists in the back part of the semiconductor substrate 3, but near the upper surface of the semiconductor substrate 3, the second separation part 9 is connected to the first separation part 8 and the first and second collector regions 11 and 21. Formed at the boundary with
The first separating unit 8 is sandwiched between the separating units 9.

Next, a method of manufacturing the semiconductor device according to the present embodiment will be described.

First, boron is selectively diffused simultaneously on a circular N-type silicon substrate 3 having a diameter of 10 cm (4 inches) to which phosphorus is added, so that the first base region 12 and the second base region 22 independent of each other are formed. And the first separation portion 8 are simultaneously formed at the same diffusion depth. Note that the common collector region 4 has the same impurity concentration as the N-type silicon substrate 3 to which phosphorus is added. Further, it is common that phosphorus in the common collector contact region 5 is diffused at a higher concentration than the common collect region 4 in a wafer state.

Next, phosphorus is introduced into a part of the first base region 12 and the second base region 22 formed in the previous step,
A first emitter region 13 and a second emitter region 23 are formed. At this time, the first base region 12 and the first
Phosphorus is introduced into a region straddling the separation unit 8 and a region straddling the second base region 22 and the first separation unit 8 to form the second separation unit 9. By this step, each base region 1
Each emitter region 13, 23 shallower than
The separation part 9 is formed.

After that, an insulating film is deposited on the substrate, a connection hole is formed in the insulating film, and a metal film such as an aluminum alloy film is further deposited on the substrate and then patterned.
First and second base electrodes 14 and 24 contacting the first and second base regions 12 and 22, respectively, and first and second base electrodes 14 and 24 contacting the first and second emitter regions 13 and 23, respectively.
The second emitter electrodes 15 and 25 are formed.

Finally, the circular silicon substrate 3 is
A pair of first vertical bipolar transistors 1;
An appropriate chip size is cut out for each semiconductor device including the vertical bipolar transistor 2 and a separation band 7 for electrically separating the transistors.

The semiconductor device according to the present embodiment has the following functions and effects due to the above structure.

First, two vertical bipolar transistors 1 and 2 required to have the same characteristics are simultaneously formed as a pair at close positions on a common semiconductor substrate by the same manufacturing process. As a result, the electrical characteristics or thermal characteristics of each of the vertical bipolar transistors 1 and 2 become very close to each other as compared with two vertically formed bipolar transistors of the related art. Therefore, the vertical bipolar transistors 1 and 2 are used as the NPN bipolar transistors 32A and 32B in the circuit shown in FIG. 8, and the PNP bipolar transistors 33A and 33B have a common semiconductor substrate having the same configuration as that of the present embodiment. A pair of two PNPs formed above
By using the vertical bipolar transistors, the characteristics of the speakers 31A and 31B can be made almost equal.

In particular, the separation zone 7 is made of two different conductive types.
By forming the layers into layers, that is, by adopting a double conductivity type structure, separation and breakdown voltage between the paired vertical transistors can be ensured.

Second, the first separation portion 8 of the separation band 7 has substantially the same depth, the same conductivity type and the same concentration of impurities as the base regions 12 and 22, and the second separation portion 9 includes the two emitter regions. 1
Since they have substantially the same depth, the same conductivity type and the same concentration of impurities as those of the bipolar transistors 3 and 23, the separation band 7 can be formed using the process for forming each of the vertical bipolar transistors 1 and 2. it can.

Third, because of the structure of the separation band 7, breakdown occurs at a voltage approximately equal to the withstand voltage value of each of the vertical bipolar transistors 1 and 2 itself. The separation withstand voltage can be kept as high as possible. That is, when a bias is applied between the emitter electrodes 15 and 25 of each of the vertical bipolar transistors 1 and 2, the same applies to the case where a reverse bias is applied between the base region and the collector region. The depletion layer spreads. At this time, by making the distance between the base region and the surrounding separation zone (including the second separation portion) substantially constant, the spread of the depletion layer can be made substantially constant around the base region. As a result, each of the vertical bipolar transistors 1 and 2 is
Breakdown occurs at the same voltage as the voltage that breaks down due to reverse bias between the collector regions. That is, the isolation withstand voltage between the vertical bipolar transistors 1 and 2 is secured to a level substantially equal to the withstand voltage of the transistor itself. For example, the distance from both ends of the separation zone 7 to the first base region 12 and the second base region 22 is 60 μm.
m, and the base depth (diffusion depth) and the emitter depth (diffusion depth) are 15 μm and 12 μm, respectively. When the specific resistance of the common collector region 4 which is an N-type silicon substrate is 10 ohms, the separation withstand voltage of each of the vertical bipolar transistors 1 and 2 is 100 volts.

Fourth, since the collector regions 11 and 21 of the vertical bipolar transistors 1 and 2 are connected to the common collector region 4 at the back of the substrate, in other words, since the collector regions of the transistors are shared, The heat generated in each of the vertical bipolar transistors 1 and 2 can be shared, and the thermal characteristics of each can be easily matched.

Fifth, in the separation zone 7, the first separation section 8
And the second separating portion 9 are superposed,
The width of the entire separation band 7 can be reduced. That is, since the chip size can be reduced as much as possible, an increase in cost of the semiconductor device can be prevented.

Sixth, as shown in FIG. 2, in the separation band 7, a first separation portion 8 having the same conductivity type and the same impurity concentration as the base regions 12 and 22 reaches the upper surface of the semiconductor substrate 3, and Since the first separating portion 8 is configured to protrude below (becomes deeper into the semiconductor substrate 3) than the second separating portion 9, as described above, the separation characteristics between the two transistors 1 and 2 are improved. Can be good.

Further, since the semiconductor device has the planar shape shown in FIG. 1, the following operation and effect can be obtained.

First, the substrate region in which the vertical bipolar transistors 1 and 2 are formed is divided into two mutually symmetrical regions by a separation band 7 formed in the center of the chip-shaped semiconductor substrate 3. First and second base regions 12, 22
Are made to be line-symmetrical with each other, the electrical characteristics or thermal characteristics of each vertical bipolar transistor can be made closer.

Second, the first emitter region 13 and the second emitter region 23, which are emitter regions involved in the main heat generating portion.
Since the emitter regions 13 and 23 are arranged symmetrically with respect to the point, the wide regions (main heating portions) of the emitter regions 13 and 23 are staggered from each other. The characteristics of the two vertical bipolar transistors 1 and 2 separated by the separation band 7 can be made equal to each other to further improve the heat resistance characteristic.

Third, since the outer shape of each of the emitter regions 13 and 23 is different from the outer shape of each of the base regions 12 and 22, the heat generated by the two vertical bipolar transistors 1 and 2 is reduced to the central portion of the semiconductor substrate 3. There is no danger of thermal characteristics being reduced. In particular, in the present embodiment, the emitter region 1
3 and 23, the width is widened at a pair of opposed diagonal portions of the semiconductor substrate 3, and the first in the separation band 7.
Since there is no place near both the emitter region 13 and the second emitter region 23, this effect can be remarkably exhibited. In fact, in the semiconductor device according to the present embodiment employing such a configuration, the heat withstand characteristic is improved by about 20% as compared with a semiconductor device having a conventional configuration in which a pair of vertical bipolar transistors is simply formed.

In this embodiment, each emitter region 1
3 and 23, the separation zone 7 is closer than the portion adjacent to the separation zone 7
Since there is a longer portion away from the emitter region, there is no portion near both the emitter regions 13 and 23 on both sides in the separation band 7. In other words, the emitter regions 13 and 23 have a planar shape such that they do not approach each other. However, the present invention is not limited to the planar shape of this embodiment, and a portion of each emitter region that is closer to the separation band may be longer than a portion that is farther from the separation band. Also in this case, it is only necessary that the separation band be formed so that the portions close to both the emitter regions on both sides are reduced.

Fourth, in the present embodiment, a large area of each of the emitter regions 13 and 23 can be used for wire bonding to each of the emitter electrodes 15 and 25, so that the pattern shape is Since the configuration is clear and the emitter electrodes 15 and 25 are separated from each other, the wire bonding connection is facilitated. In particular, in the present embodiment, a region in which the respective emitter regions 13 and 23 and the respective base regions 12 and 22 are connected by wire bonding can be provided on all sides of the semiconductor substrate 3, so that mounting is further facilitated.

However, in the case where the shape of the base region is different from that of the present embodiment, the pattern shape of the emitter region corresponds to the large heat-generating portion of the emitter region corresponding to the pattern shape of the base region. May be formed on one side of the base region, and a region for performing wire bond connection to the base region may be secured on the other side of the base region.

Fifth, since each of the emitter regions 13 and 23 is formed of a wide region and a narrow region extending near one end of each of the base regions 12 and 22,
The active area can be utilized.

Sixth, in the present embodiment, the size is set to the minimum necessary size in which the two vertical bipolar transistors 1 and 2 can be equally divided and arranged at the separation band 7, so that the semiconductor device The active region functioning as a vertical bipolar transistor can be secured as much as possible by reducing the chip size. However, the separation band 7 may be provided not only at the center of the semiconductor substrate 3 that divides the semiconductor substrate 3 into two parts and reaches from the one side to the other side, but also around the vertical bipolar transistors 1 and 2.

In this embodiment, the base regions 12 and 22 are preferably as wide as possible with respect to the semiconductor substrate 3 in order to widely utilize the active region. Accordingly, base regions 12 and 22 are arranged around collector regions 11 and 21 which are the same conductivity type regions as semiconductor substrate 3.

Further, according to the manufacturing method of the present embodiment, the first separating portion 8 and the second separating portion 9 of the separation band 7 are formed by introducing impurities into each of the base regions 12 and 22 and each of the emitter regions 13 and 23. Since they are formed at the same time, there is no need to add a step to the conventional process for manufacturing individual vertical bipolar transistors, and a pair of two vertical bipolar transistors 1 and 2 can be formed easily and at low cost. Can be.

Therefore, the size of the hybrid integrated circuit using the semiconductor device of the present embodiment can be reduced, and the number of assembling steps of the hybrid integrated circuit can be reduced.

Next, a modified example of the planar structure of the first separating section 8 and the second separating section 9 in the separation band 7 will be described. FIG.
(a)-(c) is a top view for explaining the modification of the arrangement relation of the 1st separation part 8 and the 2nd separation part 9 in the above-mentioned separation zone 7.

As the shape other than the shape of the separation band 7 in the present embodiment, the shapes shown in FIGS. Here, in order to improve the isolation characteristics between the respective vertical bipolar transistors 1 and 2, it is necessary to use FIGS. 3 (a) and 3 (b).
It is preferable that the first separating portion 8 of the semiconductor substrate 3 surrounds the second separating portion 9 as shown in FIG. On the other hand, as shown in FIG. 3C, if the first separating portion 8 is configured to be surrounded by the second separating portion 9, a leak may occur in the range A.

In this embodiment, a simple vertical bipolar transistor is used as the power transistor. However, even if a vertical MOS transistor or a Darlington connection power transistor described later is used, substantially the same effects as described above can be obtained. The effect is obtained.

Second Embodiment Next, a second embodiment relating to a semiconductor device provided with an output transistor for preventing thermal destruction and a temperature detecting transistor for detecting the temperature of the output transistor will be described. explain.

FIG. 4 is a plan view of a semiconductor device according to the second embodiment, and FIG. 5 is a cross-sectional view taken along line VV shown in FIG.

As shown in FIG. 4, the semiconductor device comprises a collector region 51 which is an N-type silicon substrate, a ring-shaped first base region 52 formed on the collector region 51,
A C-shaped first emitter region 53 formed on the first base region 52, a separation band 61 formed inside the first base region 52 and the first emitter region 53 on the collector region 51, It has a cubic second base region 62 formed inside the separation band 61, and a rectangular parallelepiped second emitter region 63 formed on the second base region 62. Further, the semiconductor device includes a collector electrode 54 provided on the lower surface of the collector region 51, a first base electrode 55 provided on the upper surface of the first base region 52, and a second electrode provided on the second base region 62. 2 base electrode 65 and first emitter electrode 5 provided on the upper surface of first emitter region 53
6 and a second emitter electrode 66 provided on the upper surface of the second emitter region 63. The output transistor 50 is constituted by the collector region 51, the first base region 52, and the first emitter region 53, and the collector region 5
The first, second base region 62 and second emitter region 63 form a temperature detecting transistor 60.

The separation zone 61 is formed between the two base regions 5.
The first isolation portion 58 is of the same conductivity type as that of the emitter regions 2 and 62 and is doped with substantially the same concentration of impurities to substantially the same depth. And the second separating portion 59 which has been doped to this extent. Then, only the first separation part 58 exists in the back part of the semiconductor substrate, but near the upper surface of the semiconductor substrate, the second separation part 59 is formed at the boundary between the first separation part 58 and the collector region 51, and The first separation part 58 is sandwiched between two second separation parts 59.

Next, a method of manufacturing the semiconductor device according to the present embodiment will be described.

First, boron is simultaneously diffused selectively on a circular N-type silicon substrate (collector region 51) to which phosphorus is added, so that the first base regions 5 independent of each other are formed.
2 and the second base region 62 and the first separation portion 58 are simultaneously formed with the same diffusion depth. Next, phosphorus is introduced into a part of the first base region 52 and the second base region 62 formed in the previous step to form the first emitter region 53 and the second emitter region 63. At the same time, phosphorus is introduced into the region extending over the first base region 52 and the first isolation portion 58 and the region extending over the second base region 62 and the first isolation portion 58 to form the second isolation portion 59. By this step, each of the emitter regions 53 and 63 and the second isolation portion 59 shallower than each of the base regions 52 and 62 are formed.

Then, after an insulating film is deposited on the substrate, a connection hole is formed in the insulating film, and a metal film such as an aluminum alloy film is deposited on the substrate, and then this is patterned.
First and second base electrodes 56 and 65 contacting the first and second base regions 52 and 62, respectively, and first and second base electrodes 56 and 65 contacting the first and second emitter regions 53 and 63, respectively.
The second emitter electrodes 56 and 66 are formed.

Finally, the circular silicon substrate is divided into an output transistor 50 and a temperature detection transistor 60.
And an appropriate chip size for each semiconductor device including a separation band 61 for electrically separating each transistor.

According to the semiconductor device of this embodiment, the following effects can be exhibited by having the above structure.

First, since the output transistor 50 and the temperature detection transistor 60 are separated by a separation band 62 composed of two layers of different conductivity types, the output transistor 50 and the temperature detection transistor 60 are not affected by noise signals (noise). Thus, when the temperature of the output transistor 50 is detected by the temperature detection transistor 60, more accurate temperature detection can be performed.

Second, the first isolation portion 58 of the isolation zone 61 has the same depth, the same conductivity type and the same concentration of impurities as the base regions 52 and 62, and the second isolation portion 59 has the same impurity concentration as the base regions 52 and 62.
Since it has the same depth, the same conductivity type, and the same concentration of impurities as those of the transistors 3 and 63, the separation band 61 can be formed by using the process for forming the transistors 50 and 60.

Third, as described in the first embodiment, the output transistor 50 and the temperature detection transistor 60 are applied with a reverse voltage substantially equal to the withstand voltage of the transistors 50 and 60 themselves. In this case, a breakdown occurs, so that the separation and breakdown voltage between the output transistor 50 and the temperature detection transistor 60 can be maintained as high as possible.

In particular, since the periphery of the temperature detecting transistor 60 is surrounded by the first emitter region 53 which is a portion of the output transistor 50 that generates heat, the temperature detected by the temperature detecting transistor 60 is lower than the temperature of the output transistor 50. Good agreement and improved temperature detection accuracy.

Next, data relating to the effect of the semiconductor device of this embodiment will be described. FIG. 6 shows a conventional semiconductor device having a channel stopper region of a single conductivity type surrounding the periphery of each transistor, and a present embodiment provided with a separation band composed of two layers of different conductivity types separating transistors. FIG. 7 is a diagram showing data of an experiment performed to compare variations in detected temperature among semiconductor devices. However, the conventional semiconductor device and the semiconductor device of the present embodiment are:
Both are provided in the audio device, and the temperature of the output transistor is set to 220 ° C.

In the figure, P indicates the distribution of the detected temperature of the semiconductor device according to the present embodiment, and Q indicates the distribution of the detected temperature of the conventional semiconductor device. As shown in the figure, the variation in the detected temperature of the semiconductor device according to the present embodiment is significantly smaller than the variation of the detected temperature of the conventional semiconductor device.

Therefore, by applying the semiconductor device according to the present embodiment to an audio device, the failure rate of the audio device can be greatly reduced.

In the present embodiment, a single transistor structure is used as the output transistor. However, even if a Darlington connection transistor structure is used instead of the single transistor, the same effects as described above can be obtained.

(Third Embodiment) Next, a third embodiment will be described.

FIG. 7 is a sectional view showing an example in which the present invention is applied to a power MOSFET. However, the illustration on the left side of the figure is omitted, and an arbitrary semiconductor element can be arranged in this portion. As shown in the figure, a power vertical MOSFET 1 separated from other regions by a separation band 87 is provided on a semiconductor substrate 83. This power vertical MOSFET 1 has two vertical MOSFs in this example.
ET, but generally, one power vertical MOS is formed by a number of vertical MOSFETs corresponding to the power.
An FET is configured. The semiconductor substrate 83 is doped with an N-type impurity (for example, boron).

Each MOSFET has two source regions 93 formed apart from each other and the two source regions 93 in the substrate.
It comprises a P-type well region 92 surrounding one source region 93 and an N-type substrate region 84 (including an impurity doped into the semiconductor substrate 83) surrounding the P-type well region 92 in the substrate. Further, below the N-type substrate region 84 is a drain contact region 85 containing a high concentration of N-type impurities, and a drain electrode 86 is provided on the drain contact region 85. On the other hand, on the upper surface of the semiconductor substrate 83, a source electrode 95 that contacts the P-type well region 92 and the two source regions 93 is formed. In addition, a polysilicon gate 96 that straddles the P well region 92 and one source region 93 of the two MOSFETs via an insulating film, and a gate electrode 97 that contacts the polysilicon gate 96 are provided.

The separation zone 87 is formed in the P-type well region 92.
A first isolation portion 88 near the upper surface doped with an impurity of substantially the same conductivity type and substantially the same concentration, and an impurity of the same conductivity type and substantially the same concentration as the source region 93 formed on both sides of the first isolation portion 88; And the second separation unit 89 into which the is introduced. Although not shown, the first separation unit 88
Extends from one side surface of the chip (for example, above the plane of FIG. 7) to the other side surface (for example, below the plane of FIG. 7), and the second separating unit 89 includes a power vertical MOSFET 81.
Surrounds the In addition, the first separation unit 88 and the second
The width dimension of the separating portion 89 may be substantially the same as that of the first embodiment.

Also in the present embodiment, a power vertical MOSFET having the same structure as the power vertical MOSFET 81 is arranged in the left region of FIG. 7, and a pair of power transistors having the same characteristics is required. Can be arranged. Further, a sensor element and a control element used for controlling the temperature of the power vertical MOSFET can be arranged in the left area of FIG. Further, as shown in FIG.
A power vertical MOSFET composed of an SFET may be provided.

Also in this embodiment, by providing the cross-sectional structure and the planar shape in the same manner as in the first or second embodiment, the same as in the first or second embodiment is provided. The effect of can be exhibited. Note that the heat generating portion of the power vertical MOSFET according to the present embodiment is the source region 93 where current is concentrated.

(Other Embodiments) Next, a planar structure in the case where the separation band structure according to the present invention is provided in a semiconductor device having three or more transistors will be described.

FIG. 9 shows an arrangement state of each region in a semiconductor device provided with four transistors 1A, 2A, 1B and 2B having basically the same structure as the vertical bipolar transistor according to the first embodiment. It is a top view. As shown in the figure, the first separation unit 8 of the separation band 7
The first separating unit 8 is formed in a cross shape so as to be divided.
Are provided on both sides. Each of the second separating units 9 includes a corresponding one of the transistors 1A, 2A, 1B, 2B.
Surrounds the Further, each transistor 1A,
Collector regions 11A, 21A, 11 of 2A, 1B, 2B
B, 21B, the base regions 12A, 22A, 12
B, 22B are formed, and each base region 12A, 2B is formed.
The outer peripheral portions of 2A, 12B and 22B are all formed in the same rectangular shape. And each base region 12
Emitter regions 13A, 23A, 13B and 23B are formed inside A, 22A, 12B and 22B, respectively. The heat generating portions of each of the emitter regions 13A, 23A, 13B, and 23B are arranged at four corners, so that heat concentration can be avoided.

FIG. 10 is a plan view showing an example of the structure of the first separation part 8 and the second separation part 9 of the separation band 7 when three power transistors, that is, first to third transistors are arranged. FIG. 11 is a plan view showing an example of the structure of the first separation part 8 and the second separation part 9 of the separation band 7 when six power transistors, that is, first to sixth transistors are arranged. In such a case, electrical isolation between the transistors can be ensured while providing three or six power transistors having the same electrical characteristics on a common semiconductor substrate.

[0082]

According to the semiconductor device of the present invention, each semiconductor element in a semiconductor device having two power transistors and two power transistors and two semiconductor elements such as a sensor element or a control element on a common semiconductor substrate. Has a double conductivity type structure including a first conductivity type first semiconductor region and a second conductivity type second semiconductor region adjacent to the first semiconductor region. Can operate independently without being interfered by each other's signals.

In particular, two power vertical bipolar transistors are provided, and the first semiconductor region of the separation band and the base region of the first conductivity type of the bipolar transistor have the same impurity concentration and diffusion depth. By making the second semiconductor region and the emitter region of the second conductivity type of the bipolar transistor have the same impurity concentration and diffusion depth, it is possible to provide a separation band having high separation characteristics without increasing the number of diffusion steps. it can.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor device provided with two vertical bipolar transistors according to a first embodiment.

FIG. 2 is a sectional view taken along line II-II shown in FIG.

FIG. 3 illustrates a first separation unit and a second separation unit in a separation band of a semiconductor device.
It is a top view for explaining the modification of the installation state with a separation part.

FIG. 4 is a plan view of a semiconductor device provided with an output transistor and a temperature detection transistor according to a second embodiment.

5 is a sectional view taken along line VV shown in FIG.

FIG. 6 is a view showing data of variation in detected temperature between the semiconductor device according to the second embodiment and a conventional semiconductor device.

FIG. 7 is a power vertical MOSFET according to a third embodiment.
FIG. 3 is a cross-sectional view showing the structure of FIG.

FIG. 8 is a circuit diagram showing an example of an audio speaker output circuit in which a conventional semiconductor element and the semiconductor element of the first embodiment are arranged.

FIG. 9 is a plan view showing an arrangement state of an emitter region of a semiconductor device provided with four power vertical bipolar transistors according to another embodiment.

FIG. 10 is a plan view showing a structure of a separation band for separating between three transistors according to another embodiment.

FIG. 11 is a plan view showing a structure of a separation band for separating between six transistors according to another embodiment.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 First vertical bipolar transistor 2 Second vertical bipolar transistor 3 Semiconductor substrate 4 Common collector region 5 Common collector contact region 6 Collector electrode 7 Separator band 8 First separator 9 Second separator 11 First collector region 21 Second Collector region 12 First base region 22 Second base region 13 First emitter region 23 Second emitter region 50 Output transistor 51 Collector region 52 First base region 53 First emitter region 54 Collector electrode 55 First base electrode 56 First Emitter electrode 58 First separating part 59 Second separating part 60 Temperature detecting transistor 61 Separation band 62 Second base region 63 Second emitter region 65 Second base electrode 66 Second emitter electrode 81 Power vertical MOSFET 83 Semiconductor substrate 84 Substrate Region 85 Drain capacitor Tact region 86 Drain electrode 87 Separator band 88 First separator 89 Second separator 92 P-type well region 93 Source region 95 Source electrode 96 Polysilicon gate 97 Gate electrode

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-47-27685 (JP, A) JP-A-54-88091 (JP, A) JP-A-6-342876 (JP, A) JP-A-63-1988 229758 (JP, A) JP-A-8-51222 (JP, A) JP-A-50-3270 (JP, A) JP-A-3-34360 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/761 H01L 27/082 H01L 29/73

Claims (6)

(57) [Claims] A first conductivity type substrate region; a separation band formed on a surface portion of the substrate region; and a separation band provided on a surface portion of the substrate region, sandwiching the separation band.
A first semiconductor region and a second semiconductor region of a second conductivity type, which are separated from each other; and a third semiconductor of a first conductivity type, provided on a surface portion of the substrate region and surrounded by the first semiconductor region. A semiconductor region comprising a first region and a fourth semiconductor region of a first conductivity type provided on a surface portion of the substrate region and surrounded by the second semiconductor region. A first of a second conductivity type extending rearward from the surface
An isolating portion, provided between the first semiconductor region and the first isolating portion, in contact with the first isolating portion and separated from the first semiconductor region so as to extend from the surface of the substrate region to the back. Extending first
A first second separating portion of a conductivity type, provided between the second semiconductor region and the first separating portion, in contact with the first separating portion, and separated from the second semiconductor region. , it is constituted by a second second separation unit from the surface of the first conductivity type extending deeper in the substrate region, the first, second separation portion of the second, rather than the first separation unit
A semiconductor device characterized by being formed shallowly . 2. The semiconductor device according to claim 1, wherein the first and second separation portions of the separation band sandwich the first separation portion from both sides of the first separation portion. A semiconductor device characterized by the above-mentioned. 3. The semiconductor device according to claim 1, wherein said substrate region is a collector region of two power vertical bipolar transistors, and said first and second semiconductor regions are each two power vertical bipolar transistors. The third and fourth semiconductor regions are emitter regions of two power vertical bipolar transistors, respectively, and the first isolation portion of the isolation band is equal to or greater than each of the base regions. A semiconductor device having a diffusion depth and an impurity concentration of 4. The semiconductor device according to claim 1, wherein said substrate region is a collector region of two power vertical bipolar transistors, and said first and second semiconductor regions are two power vertical bipolar transistors, respectively. The third and fourth semiconductor regions are emitter regions of two power vertical bipolar transistors, respectively, and the first and second separation portions and the second second separation portion of the separation band are provided. "A semiconductor device having substantially the same impurity concentration and diffusion depth as those of the emitter regions. 5. The semiconductor device according to claim 1, wherein said substrate region is a collector region of two power vertical bipolar transistors, and said first and second semiconductor regions are two power vertical bipolar transistors, respectively. Wherein the third and fourth semiconductor regions are emitter regions of two power vertical bipolar transistors, respectively, and a lateral region between the first second isolation portion and the first semiconductor region. A semiconductor device, wherein a distance in a direction is substantially equal to a lateral distance between the second second separating portion and the second semiconductor region. 6. The semiconductor device according to claim 1, wherein said substrate region is a collector region of two power vertical bipolar transistors, and said first and second semiconductor regions are two power vertical bipolar transistors, respectively. The third and fourth semiconductor regions are emitter regions of two power vertical bipolar transistors, respectively, and the first and second isolation portions are formed of two power vertical bipolar transistors. And surrounding a periphery of one of the power vertical bipolar transistors, a horizontal distance between the first second isolation portion and a base region of the one power vertical bipolar transistor is:
A semiconductor device characterized by being substantially constant over the entire periphery of the one power vertical bipolar transistor.