JP3215545B2 - Thin film multilayer wiring board and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film multilayer wiring board and a method for manufacturing the same.

[0002]

2. Description of the Related Art When realizing a large-scale and high-speed computer system, a small, high-speed, highly integrated I
It is important to use C chips and the like, and to mount them on a wiring board in a structure suitable for high-speed operation.

As one of the devices capable of realizing such a large scale and high speed, a device called a so-called multichip module (MCM) in which a plurality of IC chips are mounted on a ceramic wiring board has been conventionally used. Has been proposed.

In recent years, in particular, in recent years, multilayer ceramic wiring boards constituting the MCM, thinner conductive patterns,
There have been many attempts to fabricate MCMs that can be mounted at a higher density by reducing the thickness.

[0005] Here, the thin film multilayer wiring board suitable for increasing the density of the MCM refers to a wiring board manufactured by alternately laminating, for example, a resin insulating layer and a metal layer (conductor pattern or the like). Things.

Usually, as a method of forming a metal layer, either a dry process (sputtering, vacuum deposition, etc.) or a wet process (plating, etc.) is selected. In this type of thin-film multilayer wiring board, a metal layer is generally formed by a dry process having excellent pattern formation accuracy.

[0007]

In the dry process, the conductor pattern is formed by, for example, forming a hole for forming a via hole in an insulating layer, forming a metal thin film by sputtering or the like, etching in a resist arrangement state, or the like. It is made.

However, the formation of a metal thin film only by a dry process such as sputtering has a problem that it takes time and cost to form the film. In addition, when a desired conductive pattern is formed by etching a metal thin film, there is a problem that strict control of etching conditions must be performed in order to avoid problems such as etching residues and overetching.

Further, when sputtering is performed on a recessed portion such as a via hole, there is a disadvantage that it is difficult to secure a film thickness on a side wall portion of the via hole. Therefore, in order to avoid a decrease in the reliability of connection between metal layers, it is necessary to fill the via holes by electroless plating or the like, resulting in complicated processes and high costs. Moreover, even if the hole is filled by electroless plating or the like, if the diameter of the via hole is small, the hole is likely to be incomplete.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a thin-film multilayer wiring board capable of easily and inexpensively forming a fine conductor pattern excellent in accuracy and reliability. And a method for manufacturing the same.

[0011]

According to a first aspect of the present invention, an insulating layer made of a photosensitive resin and a conductive pattern made of a metal are alternately formed on a ceramic substrate. In a thin film multilayer wiring board formed by lamination,
A thin chromium layer formed on the insulating layer made of the photosensitive resin, a thin metal layer formed on the thin chromium layer, made of at least one metal selected from iron and nickel, and the metal A conductive pattern comprising an electrolytic copper plating layer formed on a thin layer and an electrolytic metal plating layer formed on the electrolytic copper plating layer and made of at least one metal selected from nickel, cobalt, chromium, and palladium. The gist of the present invention is a thin-film multilayer wiring board provided with the above.

Further, according to a second aspect of the present invention,
At least the following steps (a) to (f), that is, (a) a step of forming an insulating layer made of a photosensitive resin on a ceramic substrate having a conductor pattern, (b) chromium on the insulating layer by sputtering. Forming a thin layer, (c) forming a thin metal layer made of at least one metal selected from iron and nickel on the thin chromium layer by sputtering, and (d) forming a thin metal layer on the thin metal layer. After forming a plating resist on a predetermined portion of the step of forming an electrolytic copper plating layer on the thin metal layer using a copper sulfate electrolytic plating bath,
(E) nickel, cobalt, chromium, using a plating bath containing at least one metal selected from palladium,
Forming a metal plating layer on the electrolytic copper plating layer,
(f) removing the plating resist and removing the thin metal layer and the thin chromium layer exposed from the portions by etching to form a predetermined conductor pattern, thereby producing a thin-film multilayer wiring board. The method is the gist.

In the case where the thin metal layer is formed by sputtering of iron, at least one type of electrolytic plating bath selected from a copper pyrophosphate electrolytic plating bath or a copper cyanide electrolytic plating bath is provided as a pre-process before the electrolytic copper plating layer forming process. A step of forming an electrolytic copper plating thin layer on the metal thin layer using a plating bath may be provided. Further, a brightener may be added to the copper sulfate electrolytic plating bath for forming the electrolytic copper plating layer.

[0014]

The method for manufacturing a thin film multilayer wiring board according to the present invention will be described in detail in the order of steps. In the present invention, a ceramic sintered body substrate such as an aluminum nitride (AlN) substrate, an alumina (Al ₂ O ₃ ) substrate, a boron nitride (BN) substrate, a silicon nitride (Si ₃ N ₄ ) substrate, or the like is used. On the surface of such a substrate, a conductor pattern of a thin film made of a plurality of types of metals is formed by a conventionally known method, and an insulating layer made of a photosensitive resin is formed thereon. These become the first-layer conductor pattern and the insulating layer in the thin-film multilayer wiring board of the present invention.

The insulating layer is formed by applying a photosensitive resin and exposing and developing the same. At this time, as the photosensitive resin, for example, a photosensitive polyimide resin or divinylsiloxane bisbenzocyclobutene (BC
B) A resin or the like is used. The thickness of the insulating layer thus formed is preferably about 10 μm to 30 μm. It is preferable to keep the thickness within the above range in order to reduce the thickness of the entire wiring board while maintaining preferable electrical characteristics.

Then, holes for forming via holes for establishing electrical continuity between the respective layers are formed in the insulating layer by means such as a photolithography technique or an etching method.

Next, the procedure for forming the second and subsequent conductor patterns and insulating layers will be described. A thin chromium layer is formed on the first insulating layer by sputtering.

The reason why sputtering is used to form the chromium thin film is that according to the above method, a thin film having excellent adhesion and denseness can be relatively easily formed on the insulating layer. .

The reason for choosing chromium is that chromium has excellent adhesion to the underlying photosensitive resin layer and can be easily removed with a common etching solution. In the case of the present invention, the thin chromium layer serves to prevent the physical properties of the insulating layer from being impaired by the diffusion of copper that easily reacts with a photosensitive resin such as polyimide into the insulating layer.

The thickness of the thin chromium layer is 0.05 μm or more.
It is preferably 0.1 μm. This thickness is 0.05
If it is less than μm, the effect of preventing the diffusion of copper may not be sufficiently achieved. On the other hand, if the thickness exceeds 0.1 μm, it takes time and cost for sputtering, which is not preferable.

On the thin chromium layer, a thin metal layer made of at least one metal selected from iron and nickel is formed by sputtering. The reason why sputtering is employed for forming the metal thin film is that according to the above method, a thin film having excellent adhesion and denseness can be formed relatively easily on the chromium thin layer.

Each of the thin metal layers made of iron or nickel plays a role in improving the adhesion between the thin chromium layer and the electrolytic copper plating layer deposited on its surface. Preferably, the thickness of the thin metal layer is 0.05 μm to 0.2 μm. If the thickness is less than 0.05 μm, the adhesion of the electrolytic copper plating layer may not be sufficiently improved. On the other hand, this thickness is 0.2μ
If it exceeds m, it takes time and cost for sputtering, which is not preferable.

Next, a plating resist is formed on a predetermined portion of the thin metal layer, and an electrolytic copper plating layer is formed by plating using a copper sulfate electrolytic plating bath. The reason for choosing electrolytic plating as the method of forming the copper plating layer is that electrolytic plating is faster than electroless plating, and simpler plating equipment is sufficient, so it is suitable for mass production and lower cost. This is because there is an advantage.

Further, the copper sulfate electrolytic plating bath is excellent in the throwing power of plating, and therefore has an advantage that a coating film can be uniformly deposited on a portion such as a side wall portion of a via hole.

In addition to the copper sulfate electrolytic plating baths mentioned above, for example, a copper pyrophosphate bath, a copper cyanide bath or the like can be used as the electrolytic plating bath. Further, since the electrolytic copper plating layer is a metal layer that functions as a substantial conductor layer for conducting electricity, it is formed to be thicker than the other three layers. In light of the above,
It is preferable that the copper plating layer is formed within a thickness range of 3 μm to 15 μm.

In the case where the thin metal layer is formed by sputtering of iron, at least one electrolytic plating bath selected from a copper pyrophosphate electrolytic plating bath or a copper cyanide electrolytic plating bath is used as a pre-process of the electrolytic copper plating layer forming process. It is preferable to perform a step of forming an electrolytic copper plating thin layer on the metal thin layer using the above method.

The reason is that unless such a thin layer is formed, a chemical substitution reaction easily occurs in the copper sulfate bath on the surface of the iron thin film, and the adhesion between the copper thin film and the underlying iron thin film is reduced. Because. In this case, the thickness of the thin electrolytic copper plating layer formed is preferably about 0.1 μm to 0.5 μm.

It is desirable to add a brightening agent to a copper sulfate electrolytic plating bath for forming an electrolytic copper plating layer. The reason for adding the brightener is that the variation in the in-plane film thickness of the electrolytic copper plating layer obtained by this method is small. In addition, the thin film crystal is dense and the uniformity of the film in the via hole becomes excellent.

A metal plating layer is formed on the electrolytic copper plating layer using a plating bath containing at least one metal selected from nickel, cobalt, chromium, and palladium.

Since these metals do not react with the photosensitive resin like copper, the reaction between the two can be prevented by interposing the metal between the electrolytic copper plating layer and the photosensitive resin. is there. It is also preferable to add a brightener to the metal plating bath.

In this case, the thickness of the metal plating layer is 0.5 μm.
It is preferable that the thickness is about m to 2.0 μm. This thickness is 0.
If the thickness is less than 5 μm, the effect of preventing copper diffusion may not be sufficiently obtained. On the other hand, if this thickness is 2.0μ
If it exceeds m, the deposition accuracy of the conductor pattern is reduced due to the deposition of plating in the lateral direction, and a suitable pattern cross-sectional shape may not be obtained.

In addition, among the plating baths containing metals listed above, it is particularly preferable to select an electrolytic plating bath containing nickel. The reason is that the nickel electrolytic plating bath is relatively inexpensive, and therefore, it is preferable to use the nickel electroplating bath in reducing the production cost.

Next, the plating resist is peeled off, and the thin metal layer and the thin chromium layer exposed from the portion are removed by etching. By this processing, unnecessary portions in the metal layer are cut and removed, and as a result, a first-layer conductor pattern including a plurality of types of metal layers is obtained. In this case, it is preferable to use a hydrochloric acid aqueous solution or the like as an etching solution capable of simultaneously dissolving chromium, iron, and nickel from the viewpoint of simplifying the manufacturing process.

The above process is repeated as necessary to form a third-layer and subsequent conductor patterns and insulating layers, whereby a desired thin-film multilayer wiring board is manufactured. The thin-film multilayer wiring board of the present invention obtained in this way is characterized in that the conductor pattern is basically formed through sputtering as a dry process and electrolytic plating as a wet process. Further, the chromium thin layer and the metal thin layer constituting the conductor pattern are extremely thinner than the electrolytic copper plating layer and the electrolytic metal plating layer. Moreover, the present invention is characterized in that the electrolytic copper plating layer occupying the main part in the conductor pattern is formed using a copper sulfate electrolytic plating bath having a high film forming rate.

Therefore, unlike the conventional case in which the conductor pattern is formed only by sputtering, the conductor pattern can be formed at lower cost.
Moreover, according to the manufacturing method of the present invention, even when a conductor pattern is finally formed by etching, it is sufficient to remove only an extremely thin metal film, so that strict condition control is not required as in the conventional case. . Therefore, according to the present invention, it is possible to relatively easily form a conductor pattern.

Further, in the present invention, since the copper sulfate electrolytic plating bath having excellent throwing power is used, a plating film can be securely adhered to the side wall of the via hole. For this reason, the connection reliability between the layers by the via holes is reliably improved.

[0037]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to FIGS.
This will be described in detail with reference to FIG. [Embodiment 1] First, the procedure for manufacturing the thin-film multilayer wiring board of Embodiment 1 will be described in detail with reference to FIGS. 1 (a) to 1 (d) and FIG.

Step (1): As a ceramic sintered body substrate, an AlN substrate (Al
N: Y ₂ O ₃ = 96: 4) 1 was selected, and a first Ni thin film conductor pattern C 1 was formed on the AlN substrate 1.

Step (2): Using a spin coater, a photosensitive polyimide resin (UR-5100, manufactured by Toray Industries, Ltd.) to be an insulating layer I1 was applied on the AlN substrate 1 so as to have a thickness of 32 μm.

Step (3): After prebaking the photosensitive polyimide resin, exposure and development were performed, and the photosensitive polyimide resin was further cured at 380 ° C. for 30 minutes. By the above processing, the first insulating layer I having a thickness of 16 μm and having the via hole 2 having a diameter of 30 μm is formed.
1 was obtained (see FIG. 1 (a)).

Step (4): Using a vacuum sputtering apparatus (CFS-8EP manufactured by Tokuda Seisakusho), reverse sputtering was performed on the insulating layer I1 in an argon atmosphere. At that time, the gas pressure was set to 0.8 Pa, and the sputtering time was set to 2 minutes.

Next, a 0.1 μm thin Cr layer L1 was formed on the insulating layer I1 by the same vacuum sputtering apparatus. On the Cr thin layer L1, a 0.17 .mu.m Fe thin layer L2
Was formed (see FIG. 1 (b)). In this embodiment, Cr
In the sputtering, the gas pressure was set to 0.8 Pa, and the sputtering time was set to 10 minutes. In the case of Fe sputtering, the gas pressure is set to 0.6.
Pa, and the sputtering time was 20 minutes.

Step (5): Fe is applied by a spin coater.
Photoresist (OMR-8, manufactured by Tokyo Ohka) on the thin layer L2
3/60 cp) so as to have a thickness of 2.5 μm, and dried. Thereafter, the photoresist was subjected to pre-baking, exposure / development, and post-baking, thereby producing a channel-shaped plating resist 3 having an L / S of 30 μm / 30 μm.

Then, the surface of the plating resist 3 was inspected under an optical microscope, and the plating resist 3 was obtained.
The following step was performed after confirming that was excellent in accuracy.

Step (6): The surface of the insulating layer I1 was activated by immersion in a 10% aqueous sulfuric acid solution, and then electrolytic copper plating was performed in the following copper cyanide electrolytic plating bath. Then, a 0.5 μm thick electrolytic C is placed on the Fe thin layer L2.
A u-plated layer L3a was formed.

Cuprous cyanide: 40 g / l to 60 g / l,
Rossel salt 5 g / l to 15 g / l, sodium cyanide: 6
0 g / l to 80 g / l, cathode current density: 1.5 A / dm ^2-
3.0 A / dm ² Bath temperature: 35 ° C to 45 ° C, Plating time: 2 minutes.

Step (7): After the AlN substrate 1 was washed with water to remove the plating bath, electrolytic copper plating was performed using a copper sulfate electrolytic plating bath described below.
Then, a thickness of 4.0 μm is further formed on the electrolytic Cu plating layer L3a.
m of electrolytic Cu plating layer L3 was deposited.

Sulfuric acid: 180 g / l to 230 g / l, copper sulfate 40 g / l to 60 g / l, chloride ion: 30 mg / l to 60 mg / l
l, brightener: 4ml / l-10ml / l, cathode current density:
1.0 A / dm ^{2 to} 3.0 A / dm ² , bath temperature: 24 ° C. to 30 ° C.
Plating time: 8 minutes.

In this example, "Kapalaside GS" manufactured by Nippon Schering Co., Ltd. was used as a brightening agent for the plating bath. Step (8): Next, after the AlN substrate 1 was washed with water to remove the plating bath, electrolytic plating using the following electrolytic nickel plating bath was performed. Then, an electrolytic Ni plating layer L4 having a thickness of 1.0 μm was deposited on the electrolytic Cu plating layer L3 (see FIG. 1 (c)).

Nickel sulfate: 240 g / l to 280 g / l,
Boric acid 30 g / l to 40 g / l, nickel chloride: 30 g / l
~ 45 g / l, brightener: small amount, cathode current density: 1.
0 A / dm ² -2.5 A / dm ² , pH = 3.8-4.2, bath temperature: 55 ° C.-60 ° C., plating time: 2 minutes.

In this example, "Nical PC-" manufactured by Meltex Co., Ltd. was used as a brightening agent for the plating bath.
3 "was used. Step (9): Here, the plating resist 3 was stripped by dipping in an OMR stripper, and then the Fe thin layer L2 and the Cr thin layer L1 were etched with a 50% hydrochloric acid aqueous solution. Then, the Fe exposed by peeling of the plating resist 3 is removed.
By simultaneously removing the thin layer L2 and the Cr thin layer L1, a conductor pattern C2 consisting of a total of five layers, L1, L2, L3a, L3, and L4, was obtained (see FIG. 1 (d)).

Step (10): Steps (2) to (9) are repeated to finally form four conductor patterns C1 to C4 and three layers on the AlN substrate 1 as shown in FIG. A thin-film multilayer wiring board having the insulating layers I1, I2, and I3 was manufactured.

Various characteristics of the thin-film multilayer wiring board obtained by the above-described series of steps (breakage of a conductive pattern and occurrence of short-circuit, cross-sectional shape, pull strength, and connection state of via holes) were examined. Table 1 shows the results.

Observation under a microscope revealed no problems such as disconnection or short-circuit in the conductor patterns C2 to C4 of each layer. Further, the conductor patterns C2 to
The cross-sectional shape of C4 was very good, and there was almost no spreading in the width direction. Moreover, the conductor patterns C2 to C4 were also excellent in surface gloss and smoothness.

Further, when the pull strength was measured, it was 3.1 kg.
/ Mm ² , and the conductor patterns C2 to C2
4, it was found that excellent adhesion was secured. Also, as a result of the observation, it was confirmed that each metal layer was uniformly formed in the via hole 2 and the connection state of the via hole was good.

As described above, it was concluded that the conductor patterns C2 to C4 of the thin-film multilayer wiring board of Example 1 had excellent formation accuracy and reliability despite being fine. Reach. Further, according to the manufacturing method of the first embodiment, such fine conductor patterns C2 to C4
Can be formed easily and at low cost. [Embodiment 2] First, the procedure for manufacturing the thin-film multilayer wiring board of Embodiment 2 will be described in detail with reference to FIG.

Step (1): An Al ₂ O ₃ substrate (Al ₂ O ₃ = 93%) 4 was selected as a ceramic sintered body substrate, and a first Ni thin film was formed on the Al ₂ O ₃ substrate 4. The conductor pattern C1 was formed.

Step (2): By using a spin coater, a photosensitive polyimide resin (UR-3100, manufactured by Toray Industries, Ltd.) serving as an insulating layer I1 is formed on the Al ₂ O ₃ substrate 4 so as to have a thickness of 20 μm. Applied.

Step (3): After prebaking the photosensitive polyimide resin, exposure and development were performed, and the photosensitive polyimide resin was further subjected to a curing treatment at 380 ° C. for 30 minutes. By the above processing, the first insulating layer I having a thickness of 10 μm and having the via hole 2 having a diameter of 20 μm is formed.
Got 1

Step (4): Using a vacuum sputtering apparatus (CFS-8EP manufactured by Tokuda Seisakusho), reverse sputtering was performed on the insulating layer I1 in an argon atmosphere. At that time, the gas pressure was set to 0.8 Pa, and the sputtering time was set to 2 minutes.

Next, a 0.1 μm thin Cr layer L 1 was formed on the insulating layer I 1 by the same vacuum sputtering apparatus. On the Cr thin layer L1, a 0.05 μm Ni thin layer L2 as a thin metal layer was formed by the same vacuum sputtering apparatus.
Was formed. In the present embodiment, in the case of Cr sputtering, the gas pressure was set to 0.8 Pa, and the sputtering time was set to 10 minutes. In Ni sputtering, the gas pressure was set to 0.3 Pa, and the sputtering time was set to 3 minutes.

Step (5): Ni is applied by a spin coater.
Photoresist (OMR-8, manufactured by Tokyo Ohka) on the thin layer L2
3/150 cp) to a thickness of 3.5 μm and dried. Thereafter, the photoresist was subjected to pre-bake, exposure / development, and post-bake to produce a channel-shaped plating resist 3 having an L / S of 10 μm / 10 μm.

Then, the surface of the plating resist 3 was inspected under an optical microscope, and the plating resist 3 was obtained.
The following step was performed after confirming that was excellent in accuracy.

Step (6): Immediately after the surface of the insulating layer I1 was activated by immersion in a 10% aqueous sulfuric acid solution, electrolytic copper plating was performed in the following copper sulfate electrolytic plating bath. Then, an electrolytic Cu plating layer L3 having a thickness of 6.0 μm was formed on the Ni thin layer L2.

Sulfuric acid: 180 g / l to 230 g / l, copper sulfate 40 g / l to 60 g / l, chloride ion: 30 mg / l to 60 mg / l
1, brightener: 4 ml / l to 10 ml / l cathode current density: 1.0 A / dm ^{2 to} 3.0 A / dm ² , bath temperature: 24 ° C. to 30 ° C., plating time: 10 minutes.

In this example, "Kapalaside GS" manufactured by Nippon Schering Co., Ltd. was used as a brightener. Step (7): Next, after the Al ₂ O ₃ substrate 4 was washed with water to remove the plating bath, electrolytic plating was performed using the following electrolytic nickel plating bath. And
A 1.0 μm thick electrolytic Ni plating layer L4 was deposited on the electrolytic Cu plating layer L3 (see FIG. 3).

Nickel sulfate: 240 g / l to 280 g / l,
Boric acid 30 g / l to 40 g / l, nickel chloride: 30 g / l
~ 45 g / l, brightener: small amount, cathode current density: 1.
0 A / dm ² -2.5 A / dm ² , pH = 3.8-4.2, bath temperature: 55 ° C.-60 ° C., plating time: 2 minutes.

In this example, "Nical PC-" manufactured by Meltex Co., Ltd. was used as a brightening agent for the plating bath.
3 "was used. Step (8): After the plating resist 3 was peeled off by the OMR peeling solution, the Ni thin layer L2 and the Cr thin layer L1 were etched with a 70% hydrochloric acid aqueous solution. Then, the Ni thin layers L2 and C exposed by peeling the plating resist 3 are removed.
By simultaneously removing the thin layer L1 and L1, L2
, L3, L4, a conductor pattern C2 consisting of a total of four layers was obtained.

Step (9): Steps from the above step (2)
(8) is repeated, and finally Al _TwoO_ThreeOn board 4
The four conductor patterns C1 to C4 and the three insulating layers I1,
A thin-film multilayer wiring board having I2 and I3 was manufactured.

Table 1 shows the results of the same investigation as in Example 1 conducted on the thin film multilayer wiring board obtained by the above series of steps. Observation under a microscope showed no problems such as disconnection or short-circuit in the conductor patterns C2 to C4 of each layer.

Further, the cross-sectional shapes of the conductor patterns C2 to C4 were very good, and there was almost no spreading in the width direction. Moreover, the conductor patterns C2 to C4 are
The surface gloss and smoothness were also excellent.

Further, when the pull strength was measured, it was 2.6 kg.
/ Mm ² , and the conductor patterns C2 to C2
4, it was found that excellent adhesion was secured. Also, as a result of the observation, it was confirmed that each metal layer was uniformly formed in the via hole 2 and the connection state of the via hole was good.

As described above, although the conductor patterns C2 to C4 of the thin-film multilayer wiring board of the second embodiment are finer than those of the first embodiment, they have excellent formation accuracy and reliability. Is reached. Further, according to the manufacturing method of the second embodiment, it is concluded that such extremely fine conductor patterns C2 to C4 can be formed easily and at low cost.

[0074]

[Table 1]

The present invention is not limited to the above embodiment, but can be modified as follows. For example, (a) it is possible to achieve a configuration in which the number of layers is further increased by adding a build-up layer to the thin-film multilayer wiring boards of the first and second embodiments. In addition, it is of course possible to form build-up layers on both the front and back surfaces of the ceramic sintered body substrate.

(B) The photosensitive resin for forming the insulating layers I1 to I4 may be other than the resin used in the first and second embodiments, and the method of coating, exposing and developing. Can be appropriately replaced with another method.

(C) The electrolytic metal plating layer L4 is formed after the peeling and etching, instead of the method of Embodiments 1 and 2 in which the electrolytic resist plating layer L4 is formed before the peeling of the plating resist 3 and the etching removal of the exposed portion. May be formed. Further, an electroless metal plating layer may be formed instead of forming the electrolytic metal plating layer L4.

[0078]

As described above in detail, according to the thin-film multilayer wiring board and the method of manufacturing the same of the present invention, it is possible to easily and inexpensively form a fine conductor pattern excellent in accuracy and reliability. It has an excellent effect that it can be done.

[Brief description of the drawings]

FIGS. 1A to 1D are partial schematic cross-sectional views illustrating a manufacturing process of a thin-film multilayer wiring board according to a first embodiment.

FIG. 2 is a partial schematic cross-sectional view showing a thin-film multilayer wiring board in Example 1.

FIG. 3 is a partial schematic cross-sectional view for explaining a manufacturing process of a thin-film multilayer wiring board in Example 2.

[Explanation of symbols]

1 ... AlN substrate as a ceramic substrate, 3 ... plating resist, 4 ... Al ₂ O ₃ substrate as a ceramic substrate, I1, I2, I3 ... (photosensitive resin) insulating layer, C
1, C2, C3, C4 ... (metallic) conductor pattern, L
1 ... Chromium (Cr) thin layer, L2 ... Fe as metal thin layer
L3, L3a: electrolytic copper (Cu) plating layer; L4: electrolytic nickel (Ni) plating layer as an electrolytic metal plating layer.

Claims (4)

(57) [Claims] An insulating layer made of a photosensitive resin (I1, I2, I3).
) And metal conductor patterns (C1, C2, C3, C4)
) Are alternately laminated on a ceramic substrate (1, 4), wherein the thin chromium layer (L1) formed on the photosensitive resin insulating layers (I1, I2, I3) ), A thin metal layer (L2) formed on the thin chromium layer (L1) and made of at least one metal selected from iron and nickel, and a thin metal layer (L2) formed on the thin metal layer (L2). And a metal plating layer (L4) formed on the electrolytic copper plating layer (L3, L3a) and formed of at least one metal selected from nickel, cobalt, chromium, and palladium. ). A thin-film multilayer wiring board having a conductor pattern (C2, C3, C4) comprising 2. A method of manufacturing a thin-film multilayer wiring board comprising at least the following steps (a) to (f): (a) On a ceramic substrate (1, 4) having a conductor pattern (C1) Forming an insulating layer (I1) made of a photosensitive resin on the insulating layer (I1) by sputtering; and (c) forming a chromium thin layer (L1) on the insulating layer (I1) by sputtering. Layer (L1)
A step of forming a thin metal layer (L2) made of at least one kind of metal selected from iron and nickel, and (d) forming a plating resist (3) on a predetermined portion of the thin metal layer (L2). Forming an electrolytic copper plating layer (L3) on the thin metal layer (L2) using a copper sulfate electrolytic plating bath; and (e) at least one metal selected from nickel, cobalt, chromium, and palladium. Using a plating bath containing
Metal plating layer (L4) on the electrolytic copper plating layer (L3)
(F) stripping the plating resist (3) and removing the thin metal layer (L2) and the thin chromium layer (L1) exposed from the portions by etching to obtain a predetermined Forming conductive patterns (C2, C3, C4); 3. In the case where the thin metal layer (L2) is formed by sputtering of iron, as a step prior to the step of forming an electrolytic copper plating layer (L3), select from a copper pyrophosphate electrolytic plating bath or a copper cyanide electrolytic plating bath. 3. The thin-film multilayer wiring board according to claim 2, wherein a step of forming an electrolytic copper plating thin layer (L3a) on said thin metal layer (L2) using at least one type of electrolytic plating bath is performed. Production method. 4. A thin film multilayer wiring board according to claim 2, wherein a brightener is added to said copper sulfate electrolytic plating bath for forming said electrolytic copper plating layer (L3). Manufacturing method.