JP3215729B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP3215729B2 JP3215729B2 JP32337092A JP32337092A JP3215729B2 JP 3215729 B2 JP3215729 B2 JP 3215729B2 JP 32337092 A JP32337092 A JP 32337092A JP 32337092 A JP32337092 A JP 32337092A JP 3215729 B2 JP3215729 B2 JP 3215729B2
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- electric field
- semiconductor device
- silicon wafer
- oxygen concentration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 15
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 10
- 239000001301 oxygen Substances 0.000 claims description 10
- 229910052760 oxygen Inorganic materials 0.000 claims description 10
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 4
- 239000001257 hydrogen Substances 0.000 claims description 4
- 229910052739 hydrogen Inorganic materials 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 239000002344 surface layer Substances 0.000 claims description 3
- 230000005684 electric field Effects 0.000 description 17
- 230000015556 catabolic process Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 239000002244 precipitate Substances 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005247 gettering Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
- Non-Volatile Memory (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＩＣ、ＬＳＩ、ＵＬＳ
Ｉなどで用いられる、高電界下で動作可能な絶縁膜（酸
化膜、窒化膜、複合膜など）を有する半導体装置に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to IC, LSI, ULS
The present invention relates to a semiconductor device having an insulating film (an oxide film, a nitride film, a composite film, or the like) operable under a high electric field, which is used in I.
【０００２】[0002]
【従来の技術】ＩＣ、ＬＳＩ、ＵＬＳＩなどは、ＣＺ、
ＭＣＺまたはＦＺ法などにより育成されたシリコン単結
晶から２００〜８００μｍの厚さに切り出したシリコン
ウェーハを用い、熱酸化、ＣＶＤなどにより絶縁膜や電
極などの回路要素を形成したものであり、電子または正
孔の動きを制御することにより動作する。これらのデバ
イスのうち、例えば電気的に書き込み可能な不揮発性メ
モリ（Ｅ2 ＰＲＯＭ）などでは、酸化膜を介したフロー
ティングゲートへのキャリアのトンネル注入・放出を制
御することにより、データの書き込み・消去を行う。こ
のようなキャリアの注入・放出は、外部からの５Ｖ程度
の電圧では十分に起こらないため、チップ内に設けた昇
圧回路により１０Ｖ以上の電圧を発生させている。した
がって、Ｅ2 ＰＲＯＭの酸化膜には、通常のＤＲＡＭや
ＳＲＡＭと異なり、１０ＭＶ／ｃｍ以上の高電界が印加
される。2. Description of the Related Art ICs, LSIs, ULSIs, etc. are CZ,
Circuit elements such as insulating films and electrodes are formed by thermal oxidation, CVD, or the like using a silicon wafer cut to a thickness of 200 to 800 μm from a silicon single crystal grown by the MCZ or FZ method or the like. It operates by controlling the movement of holes. Among these devices, for example, an electrically writable nonvolatile memory (E 2 In a PROM or the like, data writing / erasing is performed by controlling tunnel injection / emission of carriers into a floating gate through an oxide film. Such a carrier injection / emission does not sufficiently occur at a voltage of about 5 V from the outside, so a voltage of 10 V or more is generated by a booster circuit provided in the chip. Therefore, E 2 Unlike a normal DRAM or SRAM, a high electric field of 10 MV / cm or more is applied to the oxide film of the PROM.
【０００３】[0003]
【発明が解決しようとする課題】従来は、シリコンウェ
ーハ表面を熱酸化することにより形成された膜厚２０ｎ
ｍの酸化膜を絶縁膜として用いてＭＯＳキャパシタを構
成している。しかし、従来の酸化膜では電界ストレスを
加えたときに絶縁膜が破壊される割合（絶縁破壊の割
合）は、２〜９ＭＶ／ｃｍで約６０〜８０％、１２〜１
４ＭＶ／ｃｍでほぼ１００％に達する。酸化膜が薄くな
り、使用時の電界強度が高くなるほど、酸化膜の耐圧が
劣化して信頼性が低下する。また、Ｅ2 ＰＲＯＭなどで
は高電界による酸化膜の劣化のために、データの書き込
み消去回数が１００００回程度である。このように酸化
膜の耐圧を劣化させる大きな要因として、シリコン表面
付近に存在する酸素析出物が挙げられる。Conventionally, a film thickness of 20 n formed by thermally oxidizing the surface of a silicon wafer.
A MOS capacitor is formed by using an oxide film of m as an insulating film. However, in a conventional oxide film, the rate at which the insulating film is broken when an electric field stress is applied (the rate of dielectric breakdown) is about 60 to 80% at 2 to 9 MV / cm, and 12 to 1 MV / cm.
It reaches almost 100% at 4 MV / cm. As the oxide film becomes thinner and the electric field strength during use increases, the withstand voltage of the oxide film deteriorates, and the reliability decreases. Also, E 2 In a PROM or the like, the number of times of writing and erasing data is about 10,000 due to deterioration of an oxide film due to a high electric field. A major factor that deteriorates the breakdown voltage of the oxide film is an oxygen precipitate existing near the silicon surface.
【０００４】このためシリコンウェーハ上に酸素濃度を
低減可能なエピタキシャル成長膜を形成し、デバイス活
性領域として使用するなどの対策がとられていた。しか
し、このウェーハではエピタキシャル層を形成しなけれ
ばならないため、必然的に製造コストが高騰する。しか
も、エピタキシャル成長層に特有の各種の結晶欠陥が残
存するという問題がある。Therefore, measures have been taken such as forming an epitaxially grown film capable of reducing the oxygen concentration on a silicon wafer and using it as a device active region. However, since an epitaxial layer must be formed on this wafer, the manufacturing cost inevitably increases. In addition, there is a problem that various crystal defects specific to the epitaxial growth layer remain.
【０００５】本発明は以上のような課題を解決するため
になされたものであり、高電界下でも耐圧が高く、しか
も電界ストレスを繰り返し受けても耐圧が劣化しない酸
化膜を有する半導体装置を提供することを目的とする。The present invention has been made to solve the above problems, and provides a semiconductor device having an oxide film which has a high withstand voltage even under a high electric field and which does not deteriorate even when repeatedly subjected to an electric field stress. The purpose is to do.
【０００６】[0006]
【課題を解決するための手段】本発明の半導体装置は、
酸素濃度が１．３×１０18ａｔｏｍｓ／ｃｍ3 以上のシ
リコンウェーハを水素雰囲気下において１０００℃以上
の高温で熱処理することにより得られた、表面層のデバ
イス活性領域における酸素濃度が２×１０17ａｔｏｍｓ
／ｃｍ3 以下であるシリコン基板と、その表面に形成さ
れた熱酸化により形成された絶縁膜とを具備したことを
特徴とするものである。According to the present invention, there is provided a semiconductor device comprising:
Oxygen concentration is 1.3 × 10 18 atoms / cm 3 The oxygen concentration in the device active region of the surface layer obtained by heat-treating the above silicon wafer at a high temperature of 1000 ° C. or more in a hydrogen atmosphere is 2 × 10 17 atoms.
/ Cm 3 It is characterized by comprising a silicon substrate as described below and an insulating film formed on the surface thereof by thermal oxidation.
【０００７】本発明において使用されるシリコンウェー
ハは、熱処理前の酸素濃度が１．３×１０18ｃｍ-3以上
である。このようなシリコンウェーハを、水素雰囲気下
において１０００℃以上の高温で熱処理すると、ウェー
ハ内部に酸素析出物（バルクマイクロディフェクト、Ｂ
ＭＤ）が形成される。この酸素析出物は、酸化膜特性の
劣化要因となる金属不純物に対するゲッタリング効果を
有する。また、表面層のデバイス活性領域における酸素
濃度は２×１０17ａｔｏｍｓ／ｃｍ3 以下となる。した
がって、このようなシリコン基板の表面に熱酸化により
形成された絶縁膜は、１０ＭＶ／ｃｍ以上の電界強度で
も十分な耐圧を有し、電界ストレスを繰り返し受けても
耐圧が劣化しない。The silicon wafer used in the present invention has an oxygen concentration of at least 1.3 × 10 18 cm -3 before heat treatment. When such a silicon wafer is heat-treated at a high temperature of 1000 ° C. or more in a hydrogen atmosphere, oxygen precipitates (bulk microdefect, B
MD) is formed. The oxygen precipitate has a gettering effect on metal impurities that cause deterioration of the oxide film characteristics. The oxygen concentration in the device active region of the surface layer is 2 × 10 17 atoms / cm 3. It is as follows. Therefore, an insulating film formed on the surface of such a silicon substrate by thermal oxidation has a sufficient withstand voltage even at an electric field strength of 10 MV / cm or more, and does not deteriorate even if it is repeatedly subjected to an electric field stress.
【０００８】[0008]
【実施例】以下、本発明の実施例を説明する。Embodiments of the present invention will be described below.
【０００９】チョクラルスキー法により引き上げられた
シリコン単結晶から切り出されたシリコンウェーハを１
００％水素雰囲気中、１０００℃以上の高温で熱処理し
た。このシリコンウェーハを熱酸化し、その表面に膜厚
約２０ｎｍの酸化膜を形成した。この酸化膜の上にポリ
シリコンのゲート電極を形成し、ＭＯＳ（金属−酸化膜
−シリコン）構造を形成した。A silicon wafer cut out of a silicon single crystal pulled by the Czochralski method is
Heat treatment was performed at a high temperature of 1000 ° C. or more in a 00% hydrogen atmosphere. This silicon wafer was thermally oxidized to form an oxide film having a thickness of about 20 nm on its surface. A gate electrode of polysilicon was formed on this oxide film to form a MOS (metal-oxide-silicon) structure.
【００１０】図３に示すように、これらの試料に対して
基板−ゲート電極間に電圧を印加して酸化膜に電界スト
レスを加え、酸化膜の耐圧を評価した。この際、図４に
示すように、電界ストレスは、２ＭＶ／ｃｍから１４Ｍ
Ｖ／ｃｍまで０．５ＭＶ／ｃｍずつステップ状に上げて
いった。このとき、故障判定電流を１．５μＡとし、故
障率を解析した。図１に解析結果を示す。As shown in FIG. 3, a voltage was applied between the substrate and the gate electrode to apply an electric field stress to the oxide film, and the breakdown voltage of the oxide film was evaluated. At this time, as shown in FIG. 4, the electric field stress ranges from 2 MV / cm to 14 M / cm.
It was raised in steps of 0.5 MV / cm to V / cm. At this time, the failure determination current was set to 1.5 μA, and the failure rate was analyzed. FIG. 1 shows the analysis results.
【００１１】図１から明らかなように、ウェーハのほぼ
全域（９５％）で１４ＭＶ／ｃｍまで印加しても故障し
ないことが確認できた。さらに、故障していない酸化膜
に、１４ＭＶ／ｃｍの電界ストレスを１００秒間印加し
続けても、破壊に至らなかった。As is clear from FIG. 1, it was confirmed that no breakdown occurred even when the voltage was applied up to 14 MV / cm over almost the entire area (95%) of the wafer. Further, even when an electric field stress of 14 MV / cm was continuously applied for 100 seconds to a non-failed oxide film, the oxide film was not broken.
【００１２】従来使用されているシリコンウェーハにつ
いて同様の試験を行った結果を図２に示す。図２から明
らかなようにほとんどの酸化膜が８〜１２ＭＶ／ｃｍで
破壊しており、１４ＭＶ／ｃｍの電界ストレスに耐える
ものはなかった。FIG. 2 shows the result of a similar test performed on a conventionally used silicon wafer. As is apparent from FIG. 2, most of the oxide films were broken at 8 to 12 MV / cm, and none of them could withstand the electric field stress of 14 MV / cm.
【００１３】以上のように本発明の半導体装置例えばメ
モリを構成する酸化膜は、高電界下でも絶縁膜の絶縁性
が劣化しない。したがって、メモリの消去・書き込みの
回数は、従来は１００００回程度であったのと比較する
と、大幅に増加する。As described above, the insulating property of the insulating film of the oxide film forming the semiconductor device such as the memory of the present invention does not deteriorate even under a high electric field. Therefore, the number of times of erasing / writing of the memory is greatly increased as compared with about 10,000 times in the past.
【００１４】[0014]
【発明の効果】以上詳述したように本発明の半導体装置
は、これを構成する酸化膜が高電界下でも耐圧が高く、
しかも電界ストレスを繰り返し受けても耐圧が劣化しな
いため、極めて信頼性が高い。As described above in detail, the semiconductor device of the present invention has a high withstand voltage even when the oxide film forming the same is under a high electric field.
In addition, since the withstand voltage does not deteriorate even if the electric field stress is repeatedly applied, the reliability is extremely high.
【図１】本発明の実施例におけるＭＯＳ半導体装置の絶
縁膜の耐圧分布を示す図。FIG. 1 is a diagram showing a breakdown voltage distribution of an insulating film of a MOS semiconductor device according to an embodiment of the present invention.
【図２】従来のＭＯＳ半導体装置の絶縁膜の耐圧分布を
示す図。FIG. 2 is a diagram showing a breakdown voltage distribution of an insulating film of a conventional MOS semiconductor device.
【図３】ＭＯＳ半導体装置の耐圧の測定回路を示す図。FIG. 3 is a diagram showing a circuit for measuring the breakdown voltage of a MOS semiconductor device.
【図４】ＭＯＳ半導体装置に加える電界強度を示す図。FIG. 4 is a diagram showing an electric field intensity applied to a MOS semiconductor device.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平５−102112（ＪＰ，Ａ) 特開 平３−82125（ＪＰ，Ａ) 特開 平２−177542（ＪＰ，Ａ) 特開 平４−245631（ＪＰ，Ａ) 特開 平５−335301（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/316 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-5-102112 (JP, A) JP-A-3-82125 (JP, A) JP-A-2-177542 (JP, A) JP-A-4-112 245631 (JP, A) JP-A-5-335301 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 21/316
Claims (1)
ｃｍ3 以上のシリコンウェーハを水素雰囲気下において
１０００℃以上の高温で熱処理することにより得られ
た、表面層のデバイス活性領域における酸素濃度が２×
１０17ａｔｏｍｓ／ｃｍ3 以下であるシリコン基板と、
その表面に形成された熱酸化により形成された絶縁膜と
を具備したことを特徴とする半導体装置。1. An oxygen concentration of 1.3 × 10 18 atoms /
cm 3 The oxygen concentration in the device active region of the surface layer obtained by heat-treating the above silicon wafer at a high temperature of 1000 ° C. or more in a hydrogen atmosphere is 2 ×
10 17 atoms / cm 3 A silicon substrate that is:
A semiconductor device comprising: an insulating film formed on the surface by thermal oxidation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32337092A JP3215729B2 (en) | 1992-12-02 | 1992-12-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32337092A JP3215729B2 (en) | 1992-12-02 | 1992-12-02 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06177121A JPH06177121A (en) | 1994-06-24 |
| JP3215729B2 true JP3215729B2 (en) | 2001-10-09 |
Family
ID=18154012
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32337092A Expired - Fee Related JP3215729B2 (en) | 1992-12-02 | 1992-12-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3215729B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09306904A (en) * | 1996-05-20 | 1997-11-28 | Mitsubishi Electric Corp | Semiconductor device |
-
1992
- 1992-12-02 JP JP32337092A patent/JP3215729B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06177121A (en) | 1994-06-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3119997B2 (en) | Method for manufacturing semiconductor device | |
| KR930000310B1 (en) | Manufacturing method of semiconductor device | |
| US5393683A (en) | Method of making semiconductor devices having two-layer gate structure | |
| US5757063A (en) | Semiconductor device having an extrinsic gettering film | |
| KR0165717B1 (en) | Semiconductor device and manufacturing method | |
| JPH06196716A (en) | Method for growing high quality oxide film | |
| JPH02301131A (en) | Manufacture of semiconductor device | |
| JP3288796B2 (en) | Semiconductor device | |
| JP3215729B2 (en) | Semiconductor device | |
| KR100266426B1 (en) | Semiconductor device and method for manufacturing | |
| US5854505A (en) | Process for forming silicon oxide film and gate oxide film for MOS transistors | |
| JPH07193059A (en) | Method for manufacturing semiconductor device | |
| JPH03257828A (en) | Manufacture of semiconductor device | |
| JP3338915B2 (en) | Method for manufacturing semiconductor device | |
| JP3041066B2 (en) | Insulating film forming method | |
| JP3041065B2 (en) | Insulating film forming method | |
| JP3140023B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP3429567B2 (en) | Method for manufacturing MOS semiconductor device | |
| Lee et al. | Effects of rapid thermal processing on thermal oxides of silicon | |
| Otsuka et al. | The effect of substrate materials on holding time degradation in MOS dynamic RAM | |
| JP2504558B2 (en) | Method of forming thermal oxide film | |
| Ormond et al. | Reliability of SiO 2 gate dielectric with semi-recessed oxide isolation | |
| KR960007641B1 (en) | Manufacturing method of semiconductor device | |
| JPS5892268A (en) | Manufacture of semiconductor device | |
| JPH0990416A (en) | Method of manufacturing liquid crystal display device and method of manufacturing thin film transistor used therein |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080727 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080727 Year of fee payment: 7 |
|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080727 Year of fee payment: 7 |
|
| R371 | Transfer withdrawn |
Free format text: JAPANESE INTERMEDIATE CODE: R371 |
|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080727 Year of fee payment: 7 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080727 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090727 Year of fee payment: 8 |
|
| LAPS | Cancellation because of no payment of annual fees |