JP3215934B2 - Microprocessor development support equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor development support device such as an emulation device.

[0002]

2. Description of the Related Art In a microprocessor development support apparatus for monitoring and analyzing each terminal of a microprocessor,
If the target microprocessor can handle data whose bit width is larger than the data bus, or if the data bus can handle one data by using the divided time, develop this finally handled data It is not easy for a support device to monitor.

For example, when 32-bit data is handled on a 16-bit data bus, a microprocessor accesses 16-bit data to a specific address, and then transfers the remaining 16-bit data to an address obtained by adding "2". to access. In contrast to this operation, when the development support device causes a break in the microprocessor, an event is stored in the first address and the address +2 is added (the event is a matching condition of the bus monitored by the development support device).
Is set so that a break occurs when these two events occur consecutively (sequential event).

[0004] The above-mentioned break means that the operator of the development support apparatus interrupts the processing of the microprocessor for an arbitrary operation of the microprocessor, in general, the access of a specific address, and the development support apparatus sends the break to the microcontroller. This means that the processor is placed in a controllable monitor state.
This is realized by monitoring the bus of the microprocessor and when the conditions match, the development support apparatus generates an interrupt in the microprocessor and changes the processing of the microprocessor to the processing for the development support apparatus. .
The operator analyzes the internal state of the microprocessor in the monitor state.

[0005]

However, in the above-mentioned conventional microprocessor development support device, two event detection circuits are required, and hardware is increased. When the accessed data is one specific value, the data matching condition may be set for each event as shown in FIG. 24, but as shown in FIG.
In the case of the data range condition, the event cannot be set in any combination.

SUMMARY OF THE INVENTION In view of the above circumstances, the present invention provides a microprocessor which divides data having a bit width larger than the data bus width into a plurality of bus cycles and can access the outside without providing a plurality of event detection circuits. An object of the present invention is to provide a microprocessor development support device capable of detecting an event.

[0007]

SUMMARY OF THE INVENTION A microprocessor development support apparatus according to the present invention is a microprocessor used for a microprocessor which is capable of dividing data having a bit width larger than a data bus width into a plurality of bus cycles and accessing the outside. In the development support device, data storage means for storing data having a bit width larger than the data bus width and outputting the same to an event detection circuit, and a current value when a current value of a specific signal in a bus state is different from a previous value. And outputs the same to the event detection circuit. On the other hand, when the current value matches the previous value, the previous value is held and output to the event detection circuit, and the same result is output to the control means. Rate means and the difference between the previous address and the current address is the maximum that the microprocessor can access. When the number of bytes is equal to or more than the number of bytes, the current address is accumulated and output to the event detection circuit. On the other hand, when the difference between the previous address and the current address is less than the maximum number of bytes, the previous address is held and output to the event detection circuit. An address storage comparator for outputting the result to the control unit; and determining that the input result is the same bus cycle when the difference between the addresses is less than the maximum value due to state match, and Control means for instructing the rate means and the address storage comparator means to retain the previous value and for instructing the data storage means to store both the previous data and the current data.

Further, in a microprocessor development support apparatus used for a microprocessor which can divide data having a bit width larger than a data bus width into a plurality of bus cycles and can access the same externally, a bit width larger than the data bus width is provided. Data storage means for storing the data of the specified signal in the bus state and outputting the current value to the event detection circuit when the current value of the specific signal in the bus state is different from the previous value. When the value matches the previous value, the previous value is held and output to the event detection circuit, and the above-mentioned result is output to the control means. The state accumulation comparator means, and the data bus size request signal output from the microprocessor. , The peripheral response size signal, and the address representing the bit width of the data bus as a power of two. Means for detecting the number of bytes actually accessed by the lower bits, and accumulating the number of bytes and accumulating the current address when the value added to the previous address does not match the current address, and storing this in the event detection circuit. On the other hand, if they match, the previous address is held and output to the event detection circuit, and the result of the mismatch is output to the control means. When they match, it is determined that the bus cycle is the same, the state storage comparator means and the address storage comparator means are instructed to hold the previous value, and the data storage means stores both the previous data and the current data. And control means for instructing

In the above-mentioned second configuration, the apparatus further comprises means for storing information relating to the maximum number of bytes that can be handled by the microprocessor, and the control means sets the accumulated number of bytes of the access exceeding the maximum number of bytes. In such a case, the configuration may be such that the same bus cycle is not determined.

[0010] In the second or third configuration,
The data storage means includes a storage unit capable of storing and updating data in units of the divided bit width corresponding to a microprocessor capable of dividing and using the bit width of the data bus. Based on the size signal, a selection signal indicating which data of the data bus is to be stored in which storage unit of the data storage unit is generated, and an update indicating which storage unit is to be updated based on the accumulated number of access bytes. Data storage control means for generating signals and outputting these signals to the data storage means may be provided.

[0011] In the fourth configuration, the data storage control means may select and update a pattern corresponding to the first method of locating lower data at a lower address, and a second pattern allocating lower data at a higher address. It is possible to cause the data storage means to generate a selection and update pattern corresponding to the system, and may be configured to switch between the first pattern and the second pattern based on the arrangement system identification signal.

In any one of the first to fifth configurations, the apparatus further includes means for outputting a signal indicating that a device other than the microprocessor has used the bus of the microprocessor, and the control means includes means for outputting the signal. The number of bytes accessed in the set bus cycle is set to "0", and the state mismatch and the address mismatch or the maximum value comparison result are ignored. It may be configured that the data is not updated in the cycle.

[0013]

According to the first configuration, it is determined whether or not the bus cycle is the same based on a change in a specific signal and an address in the current bus state with respect to the previous time. Since both the previous data and the current data held in the storage means are output to the event detection circuit, the divided bus cycle is treated equivalent to one bus cycle, and the event detection circuit is set to one. It becomes possible.

According to the second configuration, the disadvantages of the first configuration can be eliminated. In the first configuration, for example, when the same address is accessed by another data access, if the state matches the previous state, it is determined that the same bus cycle is present. Therefore, it is possible to accurately determine the delimitation of the bus cycle. In this configuration, however, in the present configuration, successive bus cycles are detected by adding the actually accessed size to the address, so that it is possible to accurately determine the delimitation of the bus cycle.

According to the third configuration, the disadvantage of the second configuration can be eliminated. In the second configuration, for example, when a bus cycle in which addresses are added according to the access size continues, it is not possible to determine the delimitation of the bus cycle. However, in this configuration, the maximum byte that can be handled by the microprocessor is Means for storing information about the number, and when the accumulated number of bytes of the access exceeds the maximum number of bytes, even if a state match results in an address match, the same bus cycle is used. Since the determination is not made, the break of the bus cycle can be accurately determined.

According to the fourth configuration, since data can be stored and updated in divided bit width units, the bit width of the data bus accessed at one time can be further divided and used. It can also handle access methods.

According to the fifth configuration, a selection and update pattern corresponding to the first method of arranging lower data at a lower address, and a second pattern of arranging lower data at an upper address.
Since the selection and update patterns corresponding to the above-mentioned method are switched based on the arrangement method identification signal, both types of microprocessors can be supported.

According to the sixth configuration, the number of bytes accessed in the bus cycle in which a signal indicating that a device other than the microprocessor has used the bus of the microprocessor is set to "0", and the state of the state is changed. Since the mismatch and the address mismatch are ignored and the data is not updated in the bus cycle in which the above signal is output, it is necessary to accurately determine a bus cycle delimiter even in the case of direct memory access or the like. Can be.

[0019]

【Example】

(Embodiment 1) Hereinafter, the present invention will be described with reference to the drawings showing the embodiment.

FIG. 1 is a block diagram showing a microprocessor development support device according to the present invention. This development support device includes a bus state storage comparator block 1, an address storage comparator block 2, and a data storage block 3, and these blocks 1 to 3 are controlled by a controller 4. Then, each signal (bus state, address,
The size and data are output to one event detection circuit 5 via the above-described blocks 1 to 3 and the controller 4.

FIG. 2 is a block diagram showing a specific configuration of each of the above blocks.

Bus state storage comparator block 1
Includes a multiplexer 1a, a register 1b, a bit comparator 1c, and a mask register 1d.

The MPU is connected to the B terminal of the multiplexer 1a.
The state is such that the output of the register 1b is input to the A terminal, and the select signal (NEW) is input from the controller 4 to the S terminal.

The MPU state includes RWB (“1”: read, “0”: write) indicating read / write, and PDB (“1”: “1”:
Program, “0”: data, SIZE (“1”: 1) indicating the data size to be accessed in the bus cycle
6 bits, "0": 8 bits), and the above output signal and SACK ("1": 16 bits, "0": 8 bits) indicating the data bus size of the peripheral device accessed by the address.

A multiplexer 1 is provided in the register 1b.
The output of (a) (MPU state) is held, and the held value is output to the bit comparator 1c and to the event detection circuit 5 as a state output.

The bit comparator 1c determines whether the MPU state in the current bus cycle matches the MPU state in the previous bus cycle from the register 1b, and outputs the determination result to the controller 4. . Note that the bit comparator 1c
It is determined that only the bits specified by the mask register 1d match.

The address storage comparator block 2 comprises:
It includes a multiplexer 2a, a register 2b, and a comparator 2c.

The MPU address is input to the B terminal of the multiplexer 2a, and the output of the register 2b is input to the A terminal. The multiplexer 2a
A select signal from the controller 4 is input to the S terminal of the controller 4.

The register 2b holds the output (MPU address) of the multiplexer 2a, outputs the held value to the comparator 2c and the A terminal of the multiplexer 2a, and outputs the value to the event detection circuit 5 as an address output.

The comparator 2c compares the MPU address in the current bus cycle with the MPU address in the previous bus cycle from the register 2b, and outputs the result to the controller 4. The address comparison is a magnitude comparison. If the value obtained by subtracting the previous value from the current address value is less than the maximum number of bytes accessible by the target processor ("4" when 32 bits = 4 bytes), the same value is obtained. It is determined as a bus cycle.

The data storage block 3 includes an H-side register 3
a and an L-side register 3b. These registers 3
MPU data is held in a and 3b, and this is output to the event detection circuit as a data output. In each register, data holding and new data accumulation are controlled by a command from the controller 4.

In the above configuration, the MPU state of the microprocessor is stored in the register 1b through the multiplexer 1a. At the same time, the MPU address is stored in the register 2b through the multiplexer 2a,
MPU data is stored in registers 3a and 3b.

In the next bus cycle, the bit comparator 1c compares the MPU state with the previously stored value. When all the bits specified by the mask register 1d match, it is determined that the same bus cycle as the previous time, that is, one data is divided and accessed.

In the comparator 2c, the MPU
The address is also compared with the previously stored value. In this comparison, as described above, if the value obtained by subtracting the previous value from the current address value is less than the maximum number of bytes accessible by the target processor ("4" when 32 bits = 4 bytes), the same value is obtained. It is determined as a bus cycle.

When the controller 4 determines that the bus cycle is the same based on the MPU state and the MPU address, the data on the data bus is stored in the registers 3a and 3b due to the difference from the address value stored in the register 2b. Is stored. In this case, the controller 4 outputs a select signal to the multiplexers 1a and 2a so that the A side is selected. Therefore, MP
In the U state, the previous value is held in the register 1b when the multiplexer A selects the A side, and the previous value is held in the register 2b when the A side is selected in the multiplexer 2a. .

On the other hand, if it is not determined that the bus cycle is the same, the controller 4 controls the multiplexers 1a and 2a.
In response to a, a select signal is output so that the B side is selected. Accordingly, in the MPU state, the current value is stored in the register 1b when the multiplexer B selects the side B, and the current value is stored in the register 2b when the multiplexer B selects the side B in the multiplexer 2a. Is done. The MPU data is stored in both the registers 3a and 3b (H, L).

FIG. 3 illustrates an MPU state storage state, an MPU data storage state, and the like when the processing is performed as described above. In this example, in cycle 5, a 32-bit data read from address 2,000 to “12345678h”
In cycle 8 from address 3000 "876654321h"
, And a 32-bit data write “9abcdef0” is supplied to the event detection circuit 5 to the address 3004 in cycle 10.

That is, the MPU bus state, the MPU address, and the MPU data are stored in the registers 1b, 2b, 3a, 3
b, and the matching conditions are determined. If the controller 4 determines that the bus cycle is the same, M
The contents stored in the registers 3a and 3b for storing PU data are treated as one 32-bit data in the same bus cycle, and supplied to the event detection circuit 5.
As described above, the divided bus cycle can be treated as equivalent to one bus cycle, so that only one event detection circuit 5 is required. The same applies to the case where the data is a range specification.

However, in the above configuration, when the same address is accessed by another data access, there is a disadvantage (defect 1) that a cycle break cannot be determined. Further, it is not possible to cope with an access method in which the bits and the width of the data bus to be accessed at one time are further divided and used (defect 2).

For example, as shown in FIG. 4, address 2002 is accessed by another data access in cycle 5, but this is performed in the above-described apparatus.
This is determined to be the same bus cycle as the address 0 access. In cycles 7, 8, and 9, "ba876543h" is accessed from address 3001, but this is not supported.

(Embodiment 2) An embodiment capable of solving the above-mentioned disadvantages 1 and 2 will be described below. Note that members having the same functions as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.

FIG. 5 shows a development support apparatus according to the present embodiment, and FIG. 6 shows an addition value generator of the controller 4.

The controller 4 inputs the MPU request size (SIZE), the peripheral response size (SACK), and the lower two bits of the address to the access size detection unit 4a in the addition value generation unit. The access size detector 4a detects how many bytes are accessed by the current bus cycle based on the above signals. The access data size (hereinafter referred to as access size) is determined by the register 4a, the adder circuit 4c, and the register 4d.
Accumulation is performed during the same bus cycle, and how many bytes have been accessed from the first access address of the same bus cycle is retained.

The address storage comparator block 2 is provided with an adder circuit 2d and a bit comparator 2e instead of the comparator 2c of the first embodiment.
The adder circuit 2d adds an addition value (access size) output from the adder circuit 4c of the controller 4 to the previous address stored in the register 2b. Then, the bit comparator 2e compares whether or not the added value matches the address of the next bus cycle.

That is, in the first embodiment, whether or not the same bus cycle is determined based on whether the value obtained by subtracting the previous value from the current address value is less than the maximum number of bytes accessible by the target processor. 2, the MPU request size (SI
ZE) or the like, an address for the same bus cycle is determined, and when this address matches the address of the next bus cycle, the address is determined to be the same bus cycle. 20 in cycle 5
When address 02 is accessed, the address determined as the same cycle is address 2004, and they do not match. Therefore, it is prevented that cycle 5 is determined to be the same bus cycle as access to address 2000 in cycle 3 (defect 1). Will be done.

In the controller 4 having the configuration shown in FIG. 6, if the bus cycle in which the addresses are added according to the access size continues, it is impossible to determine the break of the bus cycle.

Therefore, as shown in FIG. 7, the maximum number of bytes that can be accessed by the microprocessor at one time is stored in the maximum value register 4e, and the maximum number of bytes and the access size are compared by the comparator 4f. The point in time when the maximum value is exceeded can be determined as a break of the bus cycle. The OR circuit 4g outputs a delimiter signal (New) to each block or the like based on the output of the comparator 4f and the address and state mismatch signals.

FIG. 8 is a circuit diagram that embodies the configuration of FIG. In the figure, A0 and A1 are the lower 2 bits of the MPU address, LT is the setting signal of the maximum access register,
RESB is an initialization signal, C0 and C1 are address addition values, C2 is an event size signal, and New is a bus cycle delimiter signal (select signal to the multiplexer of each block).

As shown in FIG. 9, the MPU request size is determined by a combination of SIZE1,0 signals, and the peripheral response size is determined by a combination of SACK1,0 signals.
The maximum access size is represented by a combination of signals DI1 and DI0.

Next, a configuration for eliminating the defect 2 will be described.

The data storage block (hereinafter referred to as a data storage endian conversion block) 3 controls data storage for each byte (8 bits).
In the figure, the data of the 32-bit data bus is divided into eight bits (HH, HL, LH, LL), and four registers 3h to 3h.
k (HH, HL, LH, LL). That is, the multiplexer 3c selects which 8 bits of the 32-bit data are stored in which of the registers 3h to 3k, and also selects the multiplexers 3d to 3g.
(HH, HL, LH, LL) controls whether a signal from the controller 4 holds the value of each of the registers 3h to 3k or changes the value to the current data bus value from the multiplexer 3c.

The multiplexer 3c stores data (HH, HL, L) in units of 8 bits of a 32-bit data bus.
H, LL) in registers 3h-3k (HH, HL, LH,
LL) is stored in the lower 2 bits of the MPU address.
It is determined by the bits (A0, A1).

That is, for example, as shown in FIG.
= 0, A0 = 1, the register 3h (HH) stores 8-bit data HL (HL is data 16 to 23), and the register 3i (HL) stores 8-bit data LH (LH is data 8).
To 15) are stored in the register 3j (LH) by the 8-bit data L.
Switching is performed so that L (LL is data 0 to 7) and 8-bit data HH (HH is data 24 to 31) are stored in the register 3k (LL).

More specifically, the multiplexer 3c has the configuration shown in FIG.
As shown in FIG. 1, each of the data registers is constituted by four multiplexers.
It is controlled by the selection signals of B3 and SA2, SA3. Note that SB0 to SB3 and SA2 and SA3 are generated by a data accumulation control unit 4m described later.

The selection of the multiplexers 3g to 3e is determined by the access size (addition value).
It becomes a combination like C1 and C0 in the figure are access sizes (addition values), and C1, C0 and NE
Based on the W signal, the data accumulation control means 4m generates NEW0-NEW2 signals for selecting the multiplexers 3d-3g.

FIG. 13 is a circuit diagram showing the data storage control means 4m incorporated in the controller 4. In the figure, A0 and A1 are the lower 2 bits of the current microprocessor address, OA0 and OA1 are the lower 2 bits of the address stored in the register 2b, NEW is a delimiter signal,
NEW0 is a multiplexer 3g (LL) selection signal, NE
W1 is a multiplexer 3f (LH) selection signal, NEW2
Is a multiplexer 3e (HL) selection signal. Also,
The multiplexer 3d (HH) is always selected to be changed.

SACK0,1 are peripheral response sizes,
The selection of each of the data registers 3h to 3k is changed according to the size (SACK0, 1) of the peripheral device as shown in FIG.

According to the above configuration, as shown in FIG. 15, it is possible to cope with accessing "ba876543h" from address 3001 in cycles 7, 8, and 9.

That is, in cycle 7, SIZE becomes "0".
(SIZE0 = SIZE, SIZE1 = 0), the MPU request size is 8 bits according to FIG.
K is "1" (SACK0 = SACK, SACK1 = 0)
Therefore, the peripheral response size is 16 bits according to FIG. Also, SACK is “1” and A1 = 0, A0 =
As shown in FIG. 10, the registers 3h to 3k are:
LL, LH, LL, LH, and C1 = 1 and C0 = 0 in the immediately preceding cycle 6. However, since NEW is “1”, the registers 3h to 3k are updated, updated,
Update, update. Therefore, the contents of the registers 3h to 3k are 21, 43, 2 because the data is "4321".
1,43.

In cycle 8, similarly, registers 3h to 3h
3k becomes LL, LH, LL, LH, and in the immediately preceding cycle 7, C1 = 0, C0 = 1, and N
Since the EW is “0”, the registers 3h to 3h are shown in FIG.
k is updated, updated, updated, and none, respectively. Therefore, the contents of the registers 3h to 3k are "876
Since it is 5 ", it becomes 65, 87, 65, 43.

In cycle 9, similarly, registers 3h to 3h
3k becomes LL, LH, LL, LH, and in the immediately preceding cycle 8, C1 = 1 and C0 = 1, and N
Since the EW is “0”, the registers 3h to 3h are shown in FIG.
k is updated, none, none, none. Therefore, the contents of the registers 3h to 3k are ba, 87, 65, and 43 because the data is "dcba".

FIG. 16A is a diagram for explaining a little endian system in which lower byte data is placed at a lower address on a memory. The above embodiment has a configuration corresponding to this little endian microprocessor. Therefore, as shown in FIG. 2B, the big endian system in which the lower byte data is placed at the upper address cannot be used as it is.

(Embodiment 3) An embodiment that can support both the little endian system and the big endian system will be described below.

FIG. 17 shows the selection contents of the registers 3h to 3k corresponding to the big endian system. FIG. 18 also shows whether or not the registers 3h to 3k are updated to support the big endian system.

FIG. 19 shows the circuit configuration of the data storage control means 4m in the controller 4 for that purpose. This circuit configuration is configured by adding multiplexer function parts 40 and 41 to the circuit configuration of FIG. Then, these multiplexer function parts 40 and 41 are controlled by a BIG (signal which becomes "H" level at the time of big endian) which is an arrangement method identification signal, whereby the multiplexers 3d to 3g (HH, HL, LH, LL) are controlled. The selection pattern has been changed.

Thus, the little endian system and the video
Both end-end type microprocessors can be supported.

The microprocessor bus cycle includes:
In addition to the normal bus cycle used and controlled by the microprocessor, there are bus cycles in which peripheral devices use and control the bus of the microprocessor. This includes direct memory access (DMA) and the like, which occurs regardless of the bus cycle used by the microprocessor. In FIG. 20, although the DMA bus cycle is performed in cycle 4, in the configuration described above, the change in the address and status causes the cycles 3, 4, 5 to occur.
Are determined to be different bus cycles.

(Embodiment 4) An embodiment in which a bus cycle can be accurately determined even when a bus cycle such as the DMA is inserted will be described below.

FIG. 21 is a block diagram of the controller 4 according to this embodiment. Further, FIG.
FIG. This controller 4 has a configuration in which gate circuits 4i and 4j are added to the controller 4 of FIG. The output of the access size detection circuit 4a is input to one input of the gate circuit 4i, and the comparison inhibit signal (DISCMP) is input to the other input. Then, the gate output is output to the register 4b.

The address and state mismatch signal is input to one input of the gate circuit 4j, and the above-mentioned comparison inhibit signal is input to the other input. The gate output is output to one input of the OR circuit 4g.

[0071] Comparative inhibit signal becomes "H" level when the bus cycle of DMA or the like other than the microprocessor is detected. At this time, the access size is forcibly set to "0", and the mismatch between the address and the state is ignored. As a result, the bus cycle is determined in such a manner that the DMA cycle is ignored.

FIG. 23 is a circuit diagram showing the data storage control means 4m according to this embodiment. This data accumulation control means 4m is provided with the above-mentioned comparison inhibit signal (DISCMP)
And an update prohibition circuit 42 operated by
In the A-cycle, signals NEW0 to NEW3 are generated so that the registers 3h to 3k are not updated.

As described above, the bus cycle of the DMA or the like is configured to be ignored. Therefore, even when the access of the DMA or the like is made, the break of the bus cycle can be accurately determined.

[0074]

As described above, according to the first configuration, the divided bus cycle is treated equivalently to one bus cycle and can be processed by one event detection circuit, so that the hardware is simplified. Is done. Further, with the second configuration, it is possible to prevent the determination of the same bus cycle when accessing the same address by another data access, and to accurately determine the delimitation of the bus cycle. Further, according to the third configuration, even when bus cycles in which addresses are added according to the access size continue, it is possible to accurately determine the delimitation of the bus cycle.
Further, the fourth configuration can cope with an access method in which the bit width of the data bus accessed at one time is further divided and used. Further, the fifth configuration can support both the microprocessor of the first system in which the lower data is arranged at the lower address and the microprocessor of the second system in which the lower data is arranged at the upper address. Further, according to the sixth configuration,
For example, there is an effect that a break of a bus cycle can be accurately determined even when direct memory access or the like is performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an outline of a microprocessor development support device of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a microprocessor development support device according to the first embodiment.

FIG. 3 is a signal relation diagram showing an MPU state storage state, an MPU data storage state, and the like processed by the configuration of FIG. 2;

FIG. 4 is a signal relation diagram illustrating a defect due to the configuration of FIG. 2;

FIG. 5 is a block diagram illustrating a configuration of a microprocessor development support device according to a second embodiment;

FIG. 6 is a block diagram showing an addition value generator in the controller of FIG. 5;

FIG. 7 is a block diagram illustrating another example of an addition value generation unit in the controller of FIG. 5;

FIG. 8 is a circuit diagram showing a specific configuration of FIG. 7;

FIG. 9 is a signal relation diagram showing a relation between a signal name described in the circuit diagram of FIG. 8 and an MPU request size and the like.

FIG. 10 is a signal relationship diagram showing a relationship between A0 and A1 signals and register selection described in the circuit diagram of FIG. 13;

11 is an explanatory diagram showing a relationship between four multiplexers constituting a third multiplexer of the data storage block of FIG. 5, and signals SA2, 3 and signals SB0 to SB3 shown in the circuit diagram of FIG. 13; is there.

12 is a signal relation diagram showing a relation between C0 and C1 signals described in the circuit diagram of FIG. 13 and whether or not a register is updated;

FIG. 13 is a circuit diagram showing data accumulation control means.

14 is a signal relation diagram showing a relation between A0, A1 signals and SACK0, 1 and register selection described in the circuit diagram of FIG. 13;

FIG. 15 is a signal relation diagram showing an MPU state storage state, an MPU data storage state, and the like processed by the configuration of the second embodiment shown in FIGS. 5 to 15;

FIG. 16A is an explanatory diagram showing a little endian system, and FIG. 16B is an explanatory diagram showing a big endian system.

FIG. 17 is a view showing a third embodiment and showing a big end.
A0 according to the circuit diagram of FIG. 19 when Ian scheme, A
FIG. 3 is a signal relation diagram showing a relation between one signal and SACK0,1 and register selection.

FIG. 18 is a view showing a third embodiment and showing a big end.
C0 according to the circuit diagram of FIG. 19 when Ian method, C
FIG. 9 is a signal relation diagram showing a relation between one signal and whether or not a register is updated;

FIG. 19 is a circuit diagram showing data accumulation control means in the microprocessor development support device of the third embodiment.

FIG. 20 is a signal relation diagram showing an MPU status and the like in a state where a DMA is entered during the same bus cycle.

FIG. 21 is a block diagram illustrating an addition value generation unit and the like of a controller in a microprocessor development support device according to a fourth embodiment.

FIG. 22 is a circuit diagram showing a specific configuration of the controller of FIG. 21.

FIG. 23 is a circuit diagram showing data accumulation control means in the microprocessor development support device of the fourth embodiment.

FIG. 24 shows a conventional example, and includes events 1 and 2.
FIG. 4 is a signal relation diagram showing a relation between data, address, and data.

FIG. 25 shows a conventional example, and is a signal relation diagram showing a relation between events 1 and 2, addresses and data in data range specification.

[Explanation of symbols]

Reference Signs List 1 bus state storage comparator block 1a first multiplexer 1b register 1c bit comparator 2 address storage comparator block 2a second multiplexer 2b register 2c controller 3 data storage (data storage endian conversion) block 3a register (H) 3b register (L) 3c Third multiplexer 3d to 3g multiplexer (HH, HL, LH, L
L) 4 controller 4a access size detecting means 4a 4e maximum value register 4m data accumulation controlling means

Claims (6)

(57) [Claims] 1. A microprocessor development support device used for a microprocessor which is capable of dividing data having a bit width larger than a data bus width into a plurality of bus cycles and accessing the data externally, wherein the bit width larger than the data bus width A data storage means for storing the data of the specified signal in the bus state and outputting the current value to the event detection circuit when the current value of the specific signal in the bus state is different from the previous value. When the value coincides with the previous value, the previous value is held and output to the event detection circuit, and the above-mentioned difference result is output to the control means. If the number of bytes that can be accessed by the processor is more than the maximum, the current address is stored and When the difference between the previous address and the current address is smaller than the maximum number of bytes, the previous address is held and output to the event detection circuit, and the result is output to the control means. Rate means, when the input result is a state match and the address difference is less than the maximum value, it is determined that the bus cycle is the same,
Control means for instructing the state accumulation comparator means and the address accumulation comparator means to retain the previous value, and instructing the data accumulation means to store both the previous data and the current data. Characteristic microprocessor development support device. 2. A microprocessor development support device used for a microprocessor which is capable of dividing data having a bit width larger than a data bus width into a plurality of bus cycles and accessing the data externally, wherein the bit width larger than the data bus width Data storage means for storing the data of the specified signal in the bus state and outputting the current value to the event detection circuit when the current value of the specific signal in the bus state is different from the previous value. When the value coincides with the previous value, the previous value is held and output to the event detection circuit, and the above-mentioned result is output to the control means. The state accumulation comparator means, and the data bus size request signal output by the microprocessor. , The peripheral response size signal, and the address under which the bit width of the data bus is expressed by a power of 2 Means for detecting the number of bytes actually accessed by the order bit, and accumulating the above number of bytes and accumulating the current address when the value added to the previous address does not match the current address, and storing this in the event detection circuit. On the other hand, when the address matches, the address is stored and output to the event detection circuit when the previous address is held, and the result of the mismatch is output to the control means. When they match, it is determined that the bus cycle is the same, the state storage comparator means and the address storage comparator means are instructed to hold the previous value, and the data storage means stores both the previous data and the current data. And a control means for instructing the microprocessor development support device. . And means for storing information relating to the maximum number of bytes that can be handled by the microprocessor. The control means, when the accumulated number of bytes of the access exceeds the maximum number of bytes, controls the same bus cycle. 3. The apparatus according to claim 2, wherein the determination is not made.
2. The microprocessor development support device according to 1. 4. The data storage means includes a storage unit capable of storing and updating data in units of the divided bit width corresponding to a microprocessor which can use the data bus by dividing the bit width. In addition, a selection signal indicating which data on the data bus is to be stored in which storage unit of the data storage unit is generated based on the peripheral response size signal, and which storage unit is updated with the accumulated number of access bytes. 4. The microprocessor development support device according to claim 2, further comprising a data accumulation control unit that generates an update signal indicating whether the operation is to be performed and outputs these signals to the data accumulation unit. 5. A data accumulation control unit comprising: a selection and update pattern corresponding to a first method for locating lower data at a lower address; and a selection and update pattern corresponding to a second method for allocating lower data at an upper address. 5. The data storage device according to claim 4, wherein the data storage means can generate the pattern and switch between the first pattern and the second pattern based on the arrangement mode identification signal. Microprocessor development support device. 6. A device for outputting a signal indicating that a device other than the microprocessor has used the bus of the microprocessor, and the control unit determines the number of bytes accessed in the bus cycle in which the signal was output. 0 "and ignores state mismatch and address mismatch, and the data storage means is configured not to update data in the bus cycle in which the signal is output. The microprocessor development support device according to any one of claims 1 to 5, wherein