JP3216614B2 - Method for manufacturing semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to relates to a <br/> a method of manufacturing a semiconductor memory equipment, in particular, a semiconductor memory device having a suitable CUB or COB structure DRAM and a manufacturing method thereof.

[0002]

2. Description of the Related Art Referring to FIGS.
Capacitor Over Bitline Using S Transistor (Capacitor Over Bitlin)
e; An example of a conventional semiconductor memory device having a COB) structure and a method of manufacturing the same will be described. FIG. 5 is a plan view, and FIG.
It is sectional drawing of the -B 'line. FIG. 5A is a plan view in which only a field oxide film is formed, and FIG. 5B is a schematic plan view when a portion up to a capacitor is formed.

First, as shown in FIG. 6A, a field oxide film 32 (about 5000 mm thick) and a gate oxide film 33 (about 500 mm thick) are formed on a P-type silicon semiconductor substrate 31.
Å) is formed, and then the polycrystalline silicon film 34 (having a thickness of about 3000
Ii) is deposited, and a gate electrode is formed by using a photolithography technique and a dry etching technique. Next, FIG.
As shown in (b), a first interlayer film 35 made of a PSG film (about 5000 Å in thickness) is formed on the entire surface by a normal vapor deposition method.

Subsequently, as shown in FIG. 6C, a contact hole for forming a bit line is formed by a normal photo-etching process, and the polysilicon containing phosphorus is removed by a normal gas phase. It is formed on the entire surface by a growth method and fills the holes. Then, the bit line 36 is formed by a photo etching technique. Further, as shown in FIG.
Second interlayer film 37 made of PSG film (about 5000 厚)
Is formed over the entire surface by a normal vapor deposition method, and then a hole for a capacity contact is formed by a photoetching process.
Polysilicon containing phosphorus is formed on the entire surface by a normal vapor phase growth method, and the holes are filled. Then, the capacitor contact electrode 38 is formed by a photo etching technique.

[0005] Finally, a capacitance film 39 for accumulating charges is formed. FIG. 6B shows a planar structure when the capacitor is manufactured. In this drawing, an interlayer insulating film is not drawn for easy understanding of the structure. Further, the capacity portion is drawn by a solid frame. However, in the above-described method, when forming the capacitor contact hole, the distance between the gate electrode and the gate electrode is kept at a certain value or more, and the capacitor is manufactured with the limit of the design rule. There is a problem that a predetermined withstand voltage cannot be obtained in some cases because the contact hole is exposed to LOCOS. In addition, after forming the first and second interlayer insulating films 35 and 37, a capacitor contact hole is formed, so that etching is performed. There is a drawback that damage due to is formed in the semiconductor substrate 31.

[0006]

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned disadvantages of the prior art, and in particular, to form a groove for element isolation and an electrode for a capacitor contact in a self-aligned manner. is to provide a novel semiconductor memory equipment manufacturing method which makes it possible to reduce the distance between the capacitor contact and the gate electrode to a thickness of the sidewall.

[0007]

Since the present invention SUMMARY OF] is to achieve the above object, basically, Ru der should be adopted technical construction as described below.

[0008] A first aspect of the method of manufacturing a semiconductor memory device according to the present invention is a capacitor over bit line.
A method for manufacturing a semiconductor memory device having a gate structure, comprising:
Side walls made of a first silicon oxide film on the side walls of the poles
A first step of forming a silicon nitride layer and a silicon nitride
Second step of sequentially forming a film and a second silicon oxide film
With the second silicon oxide film in a self-aligned manner.
A third step of forming a groove for element separation in the substrate;
After forming the isolation groove, the second silicon oxide film is removed.
And a fourth step of allowed to expose the silicon nitride film, wherein
Using the exposed silicon nitride film, select only in the trench
To a fifth step of forming an oxide film, the silicon nitride
A sixth step of removing the film, and a polycrystalline polysilicon
A seventh step of forming a silicon film , and the polycrystalline silicon film
Is etched on both sides of the gate electrode,
Self-align a pair of contacts adjacent to the sidewall
And an eighth step of forming them together.
And a second aspect is that the one of the contacts
Ninth step of connecting the bit line and the other contact
Include a tenth step of connecting the capacitor contact
It is characterized by the following.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory device according to the present invention comprises a side wall made of an insulating film formed on a side wall of a gate electrode, and a bit line formed on both sides of the gate electrode in contact with the side wall. A contact and a capacitor contact are provided, and a trench for element isolation is formed between the capacitor contact and the capacitor contact.

Since the bit line contact and the capacitor contact are formed in a self-aligning manner, and the trench for element isolation is also formed in a self-aligning manner, it is necessary to bring the gate electrode and the capacitor contact as close as possible. In addition, the overlap between the contact and the element isolation region can be minimized. Therefore, the degree of integration can be further improved.

[0011]

EXAMPLES Hereinafter, a specific example of a manufacturing <br/> method for producing a semiconductor memory equipment according to the present invention in detail with reference to the drawings.
FIG. 1 is a plan view showing the structure of a specific example of a semiconductor memory device according to the present invention. FIG. 2 is a cross-sectional view taken along line AA ′ of FIG. , Sidewall 7 made of an insulating film formed on the sidewall of gate electrode 6
And a semiconductor memory device comprising a bit line contact 16 and a capacitor contact 16A formed on both sides of the gate electrode 6 in self-alignment with the side wall 7, and the capacitor contact 16A A semiconductor memory device in which a trench 12 for element isolation is formed in a self-alignment manner between the capacitor contact 16A and the capacitor contact 16A is shown. Hereinafter, the present invention will be described in more detail.

First, as shown in FIG. 1A, an element isolation region 2 is formed on a P-type silicon substrate 1 to a thickness of 5000 ° by thermal oxidation or a trench technique. Next, FIG.
As shown in FIG. 1A, an oxide film 3 constituting a gate electrode is formed to a thickness of 500.degree. By thermal oxidation, and a polycrystalline silicon film 4 as a conductive film is formed to a thickness of 5000.degree.
Formed to a thickness of Then, phosphorus which is an n-type conductivity type impurity is added, and an insulating film 5 which is an interlayer insulating film is grown to a thickness of 5000 ° by a normal vapor deposition method. Then, a gate electrode 6 (FIG. 1) is formed by a photoetching technique.

Next, a silicon oxide film is grown to a thickness of 2000.degree. By a normal vapor phase growth method, and this silicon oxide film is etched back until the interlayer insulating film 5 is exposed. The wall 7 is formed. After that, the silicon nitride film 8 and the silicon oxide film 9 are formed at 500 °
成長 grows in thickness (FIG. 2B).

As shown in FIG. 2 (c), a photoresist film 10 is applied and patterned, and as shown in FIG. 2 (d), using the photoresist film 10 as a mask, a silicon film on the element isolation region 11 is formed. The oxide film 9 is etched.
Next, as shown in FIG. 2E, the exposed silicon nitride film 8 and the silicon substrate 1 are selectively etched with respect to the silicon oxide film 9 by an anisotropic etching method. A groove 12 is formed.

As shown in FIG. 3A, a silicon oxide film 9 is formed.
Is etched by an isotropic wet or dry etching method, for example, an HF wet etching method or a CF4 plasma etching method to expose the silicon nitride film 8. Subsequently, a silicon oxide film 13 of about 200 ° is formed only on the bottom and side walls of the groove 12 by a thermal oxidation method at 850 ° C. This silicon oxide film 13 becomes a part of the insulating material filling the trench 12. The formation of the silicon oxide film 13 may be performed before the oxide film 9 is removed by etching.

Then, as shown in FIG. 3B, the silicon nitride film 8 is etched with hot phosphoric acid. FIG. 1B is a plan view at this time. Next, as shown in FIG. 3 (c), a polycrystalline silicon film 14, which is a conductive film, is grown by a normal vapor deposition method so as to be thinner than 2500 ° which is the sum of the thicknesses of the oxide film 9 and the silicon ticker film 8. Phosphorus, which is an n-type conductivity type impurity, is added. At this time, a polycrystalline silicon film to which an n-type impurity can be added during growth may be used.

Then, as shown in FIG. 3D, the polycrystalline silicon film 14 is etched back to
A contact 15 is formed in contact with. FIG. 1C is a plan view at this time. To make the plane structure easy to understand,
The polycrystalline film remaining in the groove 12 is not drawn. Then, FIG.
(D) The contact 15 is etched by a photo-etching technique, and an independent bit line contact 16 is formed.
And a contact 16A for a capacity contact is formed.

Then, as shown in FIG. 3E, a first interlayer insulating film 17 is formed, and a bit wiring 18 is formed.
Subsequently, a second interlayer film 19 is formed, and a second capacitor contact 20 and a capacitor insulating film 21 are formed. As described above, up to the capacity portion of the semiconductor memory device is completed. FIG. 1E is a plan view at this time. In this figure, the bit wiring 18 is added to FIG. 1C, and the interlayer insulating films 17 and 19 are not drawn so that the planar structure can be easily understood. Further, the capacity portion is drawn as a solid frame 21.

FIG. 4 shows another embodiment of the present invention, in which polycrystalline silicon 14 is etched in a strip shape in a direction perpendicular to the word lines, and is further etched back to form independent contacts 16, 16A. Is shown.

[0020]

The method of manufacturing a semiconductor memory equipment according to the present invention is, since it is configured as described above, by forming the electrodes for the groove and the capacitor contact for element isolation in a self-aligned manner, The distance between the capacitor contact and the gate electrode can be reduced to the thickness of the sidewall, and therefore,
It has become possible to further improve the degree of integration.

In the present invention, since the second capacitor contact only needs to be connected to the first capacitor contact, it is necessary to increase the misalignment margin in alignment and exposure for forming the second capacitor contact. It has excellent effects such as improving the degree of integration while facilitating manufacturing.

[Brief description of the drawings]

FIG. 1 is a plan view during a manufacturing process of a method for manufacturing a semiconductor memory device according to the present invention.

FIG. 2 is a cross-sectional view during a manufacturing step of the method for manufacturing a semiconductor memory device according to the present invention.

FIG. 3 is a sectional view of the manufacturing process following FIG. 2;

FIG. 4 is a cross-sectional view showing another manufacturing step of the semiconductor memory device according to the present invention.

FIG. 5 is a plan view illustrating a conventional technique.

FIG. 6 is a cross-sectional view illustrating a manufacturing process of a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 P-type silicon substrate 2 Element isolation region 3 Oxide film 4 Polycrystalline silicon film 5 Interlayer insulating film 6 Gate electrode 7 Side wall 8 Silicon nitride film 9 Silicon oxide film 10 Photoresist film 11 Element isolation region 12 Trench for element isolation DESCRIPTION OF SYMBOLS 13 Silicon oxide film 14 Polycrystalline silicon film 15 Contact 16 Contact for bit line 16A Capacitance contact 16 Second interlayer insulating film 17 First interlayer film 18 Bit line 19 Second interlayer film 20 Capacitive contact 21 Capacitive insulating film

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/108 H01L 21/822 H01L 21/8242 H01L 27/04

Claims (2)

(57) [Claims] (1)Capacitor over bit line structure
Manufacturing method of a semiconductor memory device, On the side wall of the gate electrode, a silicon oxide film is formed.
A first step of forming a wall; A silicon nitride film and a second silicon oxide film are formed on the entire surface of the substrate.
A second step of sequentially forming The device is self-aligned with respect to the second silicon oxide film.
A third step of forming a separation groove in the substrate; After forming the trench for element isolation, a second silicon oxide
Fourth step of removing the film and exposing the silicon nitride film
When, Using the exposed silicon nitride film, only in the trench
A fifth step of selectively forming an oxide film; A sixth step of removing the silicon nitride film; Seventh step of forming a polycrystalline polysilicon film over the entire surface of the substrate
When, By etching the polycrystalline silicon film,
On both sides of the gate electrode, adjacent to the sidewall
An eighth step of forming the contacts in a self-aligned manner; A method for manufacturing a semiconductor memory device, comprising: (2)Connect a bit line to the one contact
A ninth step, Tenth connecting capacitor contact to the other contact
Process and 2. The semiconductor memory device according to claim 1, comprising:
Manufacturing method.