JP3217667B2 - ATM communication control method and device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device used for asynchronous transfer mode (hereinafter referred to as ATM) communication, and more particularly to a communication control method for an ATM adaptation layer (hereinafter referred to as AAL) layer. It concerns the device.

[0002]

2. Description of the Related Art ATM communication uses a fixed length A of 53 bytes.
This is performed on the basis of a packet called a TM cell. As shown in FIG. 8, the ATM cell has a 5-byte ATM header composed of GFC, VPI, and the like, and a payload of 48-byte communication data.

When the length of data to be transferred is variable, it is necessary to control switching in a cell switch forming a communication network by software. However, ATM
In communication, data has a fixed length, and switching can be realized by hardware. For this reason, the ATM communication has an advantage that an extremely high communication speed can be achieved. ATM communication uses a virtual circuit (hereinafter referred to as V
This is performed by transferring ATM cells on a C (virtual circuit)), and one communication control device is required to control tens to hundreds of thousands of VCs.

In the ATM communication, a protocol hierarchy as shown in FIG. 9 is used. An ATM layer 102, an AAL layer 103, and a data link layer 104 exist in order from the lowest physical layer 101. Here, the ATM layer 102 is 53
This layer controls the transfer of byte-length ATM cells. The AAL layer 103, which is provided immediately above the ATM layer 102, converts a frame composed of communication data of variable length into a 53-bit A
It plays the role of disassembling and assembling into TM cells.

[0005] There are several types of provisions regarding the AAL layer 103.
The provision of AL5 is important. FIG. 10 shows the correspondence between the basic structure of the AAL5 frame and ATM cells. A
The AL5 frame is data C provided from the upper layer.
PCS-SDU, PAD, C corresponding to control field
It has PI, UU, LENGTH, and FCS. Here, the CPCS-SDU has a variable length of 1 to 65,535 bytes, and the entire length of the AAL5 frame is defined as an integral multiple of 48 bytes. Therefore, in order to adjust the length of the entire frame, the PAD field is set to 0 to 47.
Specified as a variable length byte.

[0006] The AAL5 frame is divided into 48 bytes from the front, and each becomes a payload of an ATM cell. The entire AAL frame is divided into a maximum of 1366 ATM cells. Such an ATM
It is rare that cells are continuously communicated by one VC. In many cases, ATM cells belonging to a plurality of VCs are time-division multiplexed and communicated. Therefore, a communication control device that receives an ATM cell needs to use the header of the received ATM cell to make a determination on the following items, such as which VC the ATM cell belongs to, and distribute the ATM cell. (1) Identification of the VC to which the ATM cell belongs (2) Identification of the type of AAL layer (3) If the type of AAL layer is AAL5, identification of whether the cell includes the beginning, middle, or end of the frame (4) Specifying the address of the receiving buffer in which cell data is to be stored (5) Performing various error determinations (for example, when the AAL layer is AAL5, the number of cells constituting one frame exceeds the maximum value) To determine whether or not each item has a V
A management table for managing the reception status of C is used. FIG. 11 shows a configuration of a general management table. As described above, the management table is often stored in a memory in a one-dimensionally arranged state in order to collectively manage the reception states of a plurality of VCs. The size of the table for controlling one VC is 16 to 32 bytes.

When specifying the VC to which the AAL cell in item (1) belongs, the VC is specified by obtaining the management table number using the values of VPI and VCI. When the management table number is determined, the real address of the memory is determined using this value, and the management table stored at the real address of the memory is read. Based on the contents of this management table,
Various processes are performed.

[0008]

By the way, recent communication control devices need to control many VCs, for example, thousands of channels. In this case, a management table corresponding to the number of channels is required, and the storage capacity reaches several tens of kilobytes. Therefore, it is impossible to implement the AAL5 communication control device with one integrated circuit with the current circuit technology, and the management table is stored in the external memory.

Further, every time an ATM cell is received, a corresponding one of a plurality of VC management tables stored in an external memory is read out, and the contents are updated.
I was writing back to memory. Therefore, there were the following problems. (1) It is necessary to access the external memory for each ATM cell, and the amount of data transfer with the external memory becomes enormous. (2) In order to transfer the management table from the external memory at high speed, the data transfer width must be widened and the number of clocks required for one transfer must be reduced. Was. (3) In addition to the management table, a buffer for storing control data, communication data, and the like is allocated to the external memory. For this reason, it is necessary to perform arbitration so that buses do not conflict with access to the management table and access to control data and the like, but this is complicated. (4) The timing at which access to the management table occurs is not constant. Therefore, it is necessary to design the timing when the received ATM cell is transferred and the block performs the detailed analysis of the protocol, but this design has conventionally been difficult. (5) When accessing the management table, it must be set in consideration of the order of reading and writing so as not to cause inconsistency, but it has conventionally been difficult. This will be specifically described below. In AAL5 frame,
It is necessary to perform a cyclic redundancy check (hereinafter referred to as CRC) operation. The CRC operation is performed by performing a CRC operation on a cell immediately before the ATM cell.
This is performed depending on the RC intermediate value. Therefore, the CRC calculation cannot be started until the reading of the management table is completed. Therefore, the CRC related to the ATM cell
Completion of the operation is later than the completion of the ATM cell reception. As a result, the update of the CRC intermediate value can be performed only after a certain time has elapsed since the end of the ATM cell. That is, the management table must be read immediately after the start of the reception of the ATM cell, but cannot be written immediately after the reception of the cell has been completed. In the presence of such restrictions, if ATM cells "A" and "B" belonging to the same VC are received continuously, the cell "A" must be updated before the writing of the update data to the cell "A" is completed. Conventionally, it has been difficult to avoid inconsistency such as reading the management table of “B”.

The present invention has been made in view of the above circumstances, and has as its object to provide an ATM communication control method and apparatus capable of solving the above problems and improving the efficiency of the entire system.

[0011]

An ATM communication control device according to the present invention is a device for controlling a plurality of virtual communication lines to receive an ATM cell, and extracts address information contained in the received ATM cell. A line specifying means for specifying any one of the virtual communication lines, a first memory storing a management table including information for controlling the respective virtual communication lines, and a first memory stored in the first memory. A second memory for copying and storing any of the management tables, an ATM cell storage unit for storing the received ATM cells, and reading the management table from the second memory; Protocol processing means for performing protocol processing of the ATM cell and outputting a processing end signal when the protocol processing is completed;
A management table transfer unit that transfers the management table between the first memory and the second memory; and a management unit that controls a virtual communication line specified by the line identification unit among the virtual communication lines. Determining means for determining whether or not a table is stored in the second memory; counting means for counting the number of ATM cells stored in the ATM cell storing means; Management table control means for controlling the management table transfer means according to the count value of the count means and the processing status of the protocol processing means, wherein the management table control means specifies that the determination means If it is determined that the management table for controlling the specified virtual communication line is not stored in the second memory, the management table is read from the first memory. The reads the management table second
When the protocol processing means outputs the processing end signal and the count value of the counting means indicates that the ATM cell is not stored in the ATM cell storing means, the reception is performed. A management table related to the ATM cell for which processing has been completed, which is stored in the second memory, is transferred to the first memory and written.

Here, the management table control means may be configured so that the protocol processing means outputs the processing end signal, and the count value of the counting means is that the ATM cell is not stored in the ATM cell storage means. After a lapse of a predetermined time from the point in time, the management table for the ATM cell, which is stored in the first memory, may be transferred to the first memory and written.

Further, the ATM cell storage means includes
The management table for the TM cell may store information on the address stored in the second memory together with the ATM cell.

[0014] In the ATM communication control method of the present invention, a step of extracting address information included in a received ATM cell to specify one of the virtual communication lines, and controlling each of the virtual communication lines. Storing the management table containing the information of the above in the first memory, copying any of the management tables stored in the first memory and storing the same in the second memory; Storing the management table in the cell storage means, reading the management table from the second memory and storing the management table in the ATM cell storage means;
Performing protocol processing of an M cell in protocol processing means, transferring the management table between the first memory and the second memory by management table transfer means, Determining whether a management table for controlling the virtual communication line specified by the line specifying unit is stored in the second memory; and determining whether the number of ATM cells stored in the ATM cell storage unit is Counting, and if a management table for controlling the virtual communication line specified by the line specifying means is not stored in the second memory, the management table is read from the first memory to read the second To the memory, the protocol processing means completes the protocol processing, and the count value When the M cell storage means indicates that the ATM cell is not stored, the second
Transferring and writing a management table stored in the memory for the ATM cell for which the protocol processing has been completed to the first memory.

Here, the operation of transferring the management table stored in the second memory to the first memory and writing the same is performed when the protocol processing means completes the protocol processing and the count value is stored in the ATM cell storage means. The above A
This may be performed after a predetermined time has elapsed from the time point indicating that no TM cell is stored.

Further, the ATM cell storage means stores the AT
When storing the M cells, the management table for the ATM cells may store the address information stored in the second memory together with the ATM cells.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. Here, the communication control device has a transmission function and a reception function. However, since the present invention relates to the reception function, the description of the transmission function not directly involved is omitted.

FIG. 1 shows a configuration of an ATM communication control device according to the present embodiment. In this device, the CPU 1 and the main memory 2 are connected to an ATM communication device 3 via a system bus 6, and the ATM communication device 3 is connected to an external first memory 4. The ATM communication device 3 is connected to the transmission line 16 and the reception line 17 via the physical layer control means 5. The transmission line 16 and the reception line 17 generally use optical fibers in an ATM network, and data transfer is performed by bit serial.

The CPU 1 sends A via the ATM communication device 3
It transmits and receives necessary communication data using a TM communication network.

The main memory 2 stores communication data in AAL5
-Store according to the SDU format. This communication data is accessed from the CPU 1 or the ATM communication device 3.

The first memory 4 stores a management table for all VCs used by the ATM communication device 3. Each management table is stored in the first memory 4 in a one-dimensional array structure as described later, and the management table number identifies which VC is related. This management table number corresponds to the subscript of the array.

The physical layer control means 5 converts the data format between the data format in the ATM communication device 3 and the bit serial format in the transmission line 16 or the reception line 17.

The ATM communication device 3 has a transmission block and a reception block. The reception block has a physical layer interface unit 9, a VC identification unit 10, a VCT cache control unit 11, a VCT transfer unit 14, a VCT cache unit 13, a reception cell FIFO unit 12, and a protocol processing unit 8.

The physical layer interface means 9 is connected to the physical layer control means 5, and receives an ATM cell transferred from the reception line 17 and inputted through the physical layer control means 5. Then, the physical layer interface means 9 is connected to the ATM
The VPI / VCI field is extracted from the cell.

The VC specifying means 10 outputs the extracted VP
Based on the I · VCI field, it is determined whether or not the VC is handled by the ATM communication device 3. Further, a management table number stored in the first memory 4 is calculated.
The calculation method may be, for example, using only the value of VCI, or may be obtained by extracting lower bits of a predetermined number of bits from VCI and VPI and concatenating them. The obtained management table number is given to the VCT cache unit 13. Further, if the VC identification means 10 determines that the ATM cell can be received, the physical layer interface means 9 sends the received cell FIFO to the reception cell FIFO.
The ATM cell is transferred to the means 12.

The reception cell FIFO means 12 is provided with not only ATM cells but also a cache index value to be described later. These ATM cells and cache index values are transmitted from the reception cell FIFO unit 12 to the protocol processing unit 8.
Given to. Here, the reception cell FIFO means 12
The difference in frequency between the operation clock in the physical layer control means 5 and the operation clock in the ATM communication device 3 is absorbed. Further, time adjustment is performed until a management table is prepared in the VCT cache control unit 11 described later.

The VCT cache means 13 stores a plurality of VCs
Are temporarily stored in the management table corresponding to the respective items. What has the same content as the management table described with reference to FIG. 11 is stored in the VCT cache unit 13 in the format as shown in FIG. Here, the format of the management table shown in FIG. 2 is different from that shown in FIG. 11 in the following points. As shown in FIG. 11, the management tables stored in the first memory 4 are VC management tables VC # 0, VC # 1,.
They are arranged in order. On the other hand, as shown in FIG.
The CT cache unit 13 stores the management table 15 in the first memory 4 transferred by the VCT transfer unit 14 under the control of the VCT cache control unit 11 described later. Therefore, unlike the first memory 4, each management table stored is identified by the cache index # 0, # 1, # 2,. Here, the correspondence between the management table number in the first memory 4 and the cache index in the VCT cache unit 12 is represented by VCT
The cache control means 11 makes the determination.

The VCT transfer means 14 calculates the address where the management table 15 is stored in the first memory 4 using the management table number given from the VCT cache means 13. And VCT cache means 1
The data is transferred to and from the address in the VCT cache means 13 indicated by the cache index managed by 3.

The protocol processing unit 8 includes a reception cell FIFO
When a valid ATM cell exists in the means 12, the protocol processing required for reception is started. This protocol processing has the following contents. The ATM cell data and the cache index are output from the reception cell FIFO unit 12 to the protocol processing unit 8. This cache Inde
The VCT cache unit 13 is accessed using the value of x to obtain a reception state variable. If the reception state variable indicates “before starting frame assembly”, the contents of the management table of the VCT cache unit 13 are initialized. Then, the area of the receiving buffer for writing the payload of the ATM cell is stored in the main memory 2.
Write the payload after securing it inside. Then, the information such as the address at the time of writing is written to the management table in the VCT cache unit 12. As the reception state variable, information that “frame is being assembled” is set.

When the reception state variable is "this frame is being assembled"
Is calculated, the address of the main memory 2 is calculated based on the address of the reception buffer and the remaining capacity indicated in the management table, and the payload is written to this address. Then, the receiving buffer address and the remaining capacity are updated. Further, the CRC intermediate value and the CPM of the subsequent ATM cell are calculated from the payload of the currently processed ATM cell.
The RC intermediate value is calculated, and the CRC intermediate value is updated.

If the ATM cell is located at the end of the AAL5 frame, it is necessary to perform an assembly completion process for the AAL5 frame. Specifically, PAD
There is a length check, a CRC-32 check, and the like, and this processing result is notified to the CPU 1. Thereafter, the reception state variable is set to “before starting frame assembly”.

In this embodiment, the ATM cell is AAL5
Although the case of belonging to a frame is described as an example, the case of belonging to another type may be used. In this case, protocol processing corresponding to the frame to which the ATM cell belongs is performed.

When the protocol processing in the protocol processing section 8 is completed, a protocol processing end signal is transferred from the protocol processing section 8 to the VCT cache means 13, and the processing of the ATM cell is completed. When this process is completed, the management table of the ATM cell in the VCT cache unit 13 becomes unnecessary, and is written back to the area of the management table 15 in the first memory 4 using the VCT transfer unit 14.

The VCT cache control means 11 determines whether or not a management table matching the management table number calculated by the VC specifying means 10 is stored in the VCT cache means 13. Then, the necessary management table is
The data is read out using the CT transfer means 14. At this time, VCT
The cache control unit 11 outputs the cache index value to the reception cell FIFO unit 12. Where Cache In
The dex value indicates the number of the input of the management table to the VCT cache.

The detailed configuration of the VCT cache control means 11 is as shown in FIG. 3, and includes a management table transfer instructing means 11a, a processing target cell number counter 11b, and a coincidence detecting means 11c.

The coincidence detecting means 11c is provided for each entry # 0, # 1, # 2,... For the VCT cache means 13 to store a plurality of ATM cells. Then, the flag indicating whether the corresponding entry of the VCT cache unit 13 is valid or invalid, and the number of the management table currently stored when the entry is valid are held. If the entry is valid, the match detection means 11c outputs the entry validity display signal 11n.
Is output to the processing target cell number counter 11b described later.

The coincidence detecting means 11c is activated when given a management table number signal 11f and a search instruction signal 11d output from the VC specifying means 10. Then, the management table number held by each entry and V
If the management table number output from the C specifying unit 10 matches, the matching signal 11p for the entry is output to the processing target cell number counter 11b. If none of the management table numbers match, no match signal 11p is output.

The processing target cell number counter 11b has a VCT
It counts the number of unprocessed cells among the received cells using the cache. When the coincidence signal 11p is received from the coincidence detecting means 11c, the count value is incremented by +1. When the protocol processing end signal 11e output from the protocol processing unit 8 is given, -1
Decrement. Then, when the count value becomes "0", it outputs a processing end signal 11q indicating that the unprocessed cell no longer exists to the management table transfer instructing means 11a.

The management table transfer instructing means 11a receives the search instruction signal 11d from the VC specifying means 10 and outputs the coincidence signal 11p from the coincidence detecting means 11c. It determines that the management table to be stored is stored in the VCT cache means 12, and outputs a hit signal 11g and a cache index signal 11i.

Here, the cache index signal 11i is
The entry number of the cache is shown. Here, the search instruction signal 11d indicates to the management table transfer instructing means 11a that when the VC identification means 10 outputs a new management table number, whether the number is stored in the VCT cache means 13 is searched. Used to get started. Further, the match signal 11p is the search instruction signal 11
d has a valid value after being given to the coincidence detecting means 11c and starting operation. Therefore, the management table transfer instructing means 1
In 1a, it is necessary to perform a procedure of checking the value of the match signal 11p after the search instruction signal 11d is given.

On the contrary, the coincidence signal 1 is output from the coincidence detecting means 11c.
When 1p is not output, the management table is VC
It is found that the data is not stored in the T cache means 13. Therefore, the management table management instructing means 1a outputs the cache index signal 11i indicating the entry number of the unused cache. Entry number # corresponding to this cache Index among the coincidence detecting means 11c
Management table numbers are set in the areas 0 to n. Further, the management table transfer instructing means 11a sends a transfer instruction signal 11h for instructing reading to the VCT transfer means 1.
4 is output. VCT transfer means 14 outputs transfer end signal 11
j, the entry valid display on / off control signal 11m is changed to "O" indicating that the entry is valid.
N "state, and outputs the re-examination instruction signal 11k to the coincidence detecting means 11c.

Since the entry valid display signal 11n is set to ON, the coincidence detecting means 11c outputs the coincidence signal 11p to the processing target cell number counter 11b. The subsequent operation is the same as the operation when the above-mentioned entry exists, and the description is omitted.

When the protocol processing end signal 11e is input to the processing target cell counter 11b and the processing end signal 11q is input from the processing target cell counter 11b to the management table transfer instructing means 11a, the reception cell belonging to the management table It is found that all the processes have been completed. In this case, a cache index signal indicating a cache entry number is output from the management table transfer instructing means 11a, and a transfer instruction signal 11h for instructing the VCT transfer means 14 to write is output. The entry valid display signal 11n is turned off. Conversely, the processing end signal 11q is the processing target cell number counter 11
b, if this signal is not input to the management table transfer instructing means 11a, this signal is not output. At least one reception cell to be processed using the management table is stored in the reception cell FIFO means 12. Turns out. Therefore, the transfer instruction signal 11h for instructing writing is not output from the management table transfer instructing means 11a.

The operation of this embodiment having such a configuration will be described below. FIG. 4 is a flowchart showing an operation procedure when ATM cells belonging to the same VC are continuously received. (1) Step 101 (ATM cell reception) An ATM cell is input to the physical layer interface means 9 in the ATM communication device 3 via the physical layer control means 5. The physical layer interface means 9 extracts the VPI / VCI field contained in the input ATM cell and transfers it to the VC specifying means 10. (2) Step 102 (VC specification) VC specifying means 1 given a VPI / VCI field
0 generates a management table number and determines whether or not the ATM cell can be received. When determining that the reception is possible, the VC identification unit 10 notifies the physical layer interface unit 9 of the determination. Further, the VC specifying means 10
The management table number signal 11f and the search instruction signal 11d are given to the VCT cache control means 11. (3) Step 103 (ATM to reception FIFO means)
Cell input) The physical layer interface unit 9 transfers the ATM cell to the reception cell FIFO unit 12. (4) Step 104 (VCT cache start operation) The VCT cache control unit 11 searches for an entry that matches the management table number held in the match detection unit 11c. If there is such an entry, the match detecting means 11c corresponding to this entry
Is output to the corresponding processing target cell number counter 11b and the management table transfer instructing means 11a. The processing target cell number counter 11b that has received the coincidence detection signal 11p increments the count value by +1. Upon receiving the match detection signal 11p, the management table transfer instructing means 11a sets the cache In corresponding to the entry in question.
The dex number is output as the cache index signal 11i,
At the same time, a hit signal 11g is output.

The entry corresponding to the management table number is 1
If no match is found, the match signal 1 is output from the match detection means 11c.
1p is not output at all. In such a case, the AT
This means that the management table corresponding to the M cell is not stored in the VCT cache unit 13. Therefore, the number of an unused entry is found, and a management table number is set for that entry. Further, the management table transfer instructing means 11a stores the number in the cache index signal 11
i, and the transfer instruction signal 11h is
Output to transfer means 14. Subsequent read operations are:
This is performed in a later step 108. (5) Step 105 (A to the reception FIFO means 12)
When the ATM cell is input to the reception cell FIFO unit 12 and a hit signal 11g is received from the management table transfer instructing unit 11a, the physical layer interface unit 9 sets the cache in.
The dex signal 11i is written into the reception cell FIFO means 12. Thus, the input of the ATM cell to the reception FIFO unit 12 is completed. (6) Step 106 (Operation of Protocol Processing Unit) The protocol processing unit 8 checks the output from the reception cell FIFO unit 12. If a valid ATM cell has been output, the protocol processing is performed by accessing the entry of the VCT cache means 13 using the cache index number indicated by the cache index signal 11i output therewith. ATM cell data is
The data is written to the main memory 2 from the protocol processing unit 8 via the system bus 6. When the processing in the protocol processing unit 8 is completed, the cache index signal 11i and the protocol processing end signal 11e are transmitted to the VCT cache control unit 1.
Given to one. (7) Step 107 (VCT cache end operation) The VCT cache control unit 11
Receives the protocol processing end signal 11e output from the CPU, the count value of the processing target cell number counter 11b corresponding to the cache index signal 11i indicated by this signal is decremented by -1. When the count value becomes "0", there is no ATM cell belonging to the same VC in the reception cell FIFO means 12.
Then, the cache index signal 11i and the transfer instruction signal 11h are output from the management table transfer instruction means 11a to the VCT transfer means 14. (8) Step 108 (reading of management table) The VCT transfer means 14 given the cache index signal 11i and the transfer instruction signal 11h uses the given management table number signal 11f to perform management in the first memory 4. Create an address for Table 15. Using this address, the management table data stored in the first memory 4 is read and written into the area of the designated cache index number in the VCT cache means 13. After this, the VCT transfer means 14 sends the physical layer interface means 9
And the VCT cache control means 11 are notified that the operation has been completed. In the VCT cache control unit 11 notified of this, the management table transfer instructing unit 11a
Outputs the entry valid display on / off control signal 11m to turn on the entry valid display signal 11n.

Here, the entry valid display signal 11n is
It is used to indicate that usable data is stored in the VCT cache unit 13. Further, it outputs the re-examination instruction signal 11k to the coincidence detecting means 11c.

Here, the reexamination instruction signal 11k is VCT
The signal indicating the end of data storage in the cache unit 13 is used for the following reason. The situation where the VCT transfer means 14 stores new management data means that the data managed by the VC
In this situation, the match has not yet been stored in the cache unit 12, and the match detection unit 11c has not output a match signal.
At the stage of storing the management data in the VCT cache unit 13, the management table transfer instructing unit 11a sets the management table number corresponding to the cache index in which the management data is to be stored in the coincidence detection unit 11c.

When the management data is stored in the VCT cache unit 13, the coincidence detecting unit 11c must output the coincidence signal 11p. Therefore, this retest instruction signal 11k is given to the coincidence detecting means 11c, and VC
It is instructed to check whether or not the management table number output by the specifying means 10 matches the management table number held by the match detection means 11c. The operation after the re-examination instruction signal 11k is given to the coincidence detecting means 11c is as follows.
And the control of the operation can be performed centrally.

It is assumed that the management table number is matched with the coincidence detecting means 1.
If the coincidence detecting means 11c immediately outputs the coincidence signal 11p after setting to 1c, there is a possibility that a problem may occur in the timing of the count-up operation in the processing target cell number counter 11b and the operation in the protocol processing unit 8. Therefore, the management table is stored in the VCT cache unit 13.
After that, the reinspection instruction signal 11k is supplied to the coincidence detecting means 11c so that the coincidence signal 11p is output. That is, after the management table is actually stored in the VCT cache unit 13, the re-inspection instruction signal 11k indicating that the storage operation has been completed is sent to the coincidence detection unit 1.
1c, the count-up operation in the processing target cell number counter 11b and the activation of the protocol processing operation in the protocol processing unit 8 are started.

In the processing target cell number counter 11b,
The count value is incremented by +1 and the hit signal 11
g is generated and output by the management table transfer instructing means 11a. Thereafter, the cache entry becomes valid. (9) Step 109 (writing to the management table) The VCT transfer means 14 sends the management table transfer instruction means 11
The entry of the VCT cache means 13 is read using the cache index signal 11i given from a to obtain a management table number signal 11f. The address of the management table 15 in the first memory 4 is created from the value of the management table number, and the contents of the cache entry are written in the first memory 4. When the writing is completed, the VC transfer means 14
Notifies the VCT cache control unit 11 that the writing to the management table has been completed. The VCT cache control means 11 turns off the corresponding entry valid display signal 11n. Since this entry is in an unused state, it can be a target when the management table is written by the VCT transfer unit 14 next time. (10) Step 110 (continuous reception to the same VC) When ATM cells belonging to the same VC are received continuously or for a very short time, the processing is performed according to the procedure shown in FIG. Will be Here, the same steps as those described with reference to FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted.

When ATM cells belonging to the same VC are received continuously or in a very short time, the received cell FIF
It is highly probable that these ATM cells are stored in the O means 12. At this time, the count value of the processing target cell number counter 11b increases by the number j of the accumulated ATM cells.
j has been incremented. In such a case, no data transfer is performed between the management table 15 on the first memory 4 and the VCT cache unit 13, and step 11
0, the VCT cache control means 11
The cache unit 13 is accessed. Thereby, AT
The usage rate of the memory bus between the M communication device 3 and the first memory 4 is reduced.

As described above, according to the first embodiment, in addition to the first memory 4 provided externally, the VCT cache means 13 which can be accessed at a high speed is provided. Only when the corresponding management table is not stored in the VCT cache unit 13, the first memory 4 is accessed to read the management table. Then, the number of the ATM cells belonging to the VC which have not yet been subjected to the reception processing are counted in the reception cell FIFO means 12. Only when the processing of all the ATM cells is completed, the first memory is counted. 4, the management table is written. As a result, the frequency of accessing the first memory 4 is greatly reduced as compared with the related art, and it is possible to improve the efficiency of the entire system without obstructing other data transfer.

Furthermore, conventionally, as described above, it has been difficult to make settings so as not to cause inconsistency in the timing of the operation of reading and writing the management table in the externally provided memory. On the other hand, in the present embodiment, since the VCT cache unit 13 accessed by the protocol processing unit 8 requiring the management table always stores the latest management table, inconsistency may occur between reading and writing. Therefore, it is easy to set the control timing.

Next, a second embodiment of the present invention will be described. In the above-described first embodiment, when an ATM cell is received and the reception processing is performed in the protocol processing unit 8, it is immediately decremented in step 106. For this reason, when ATMs are not continuously received by the same VC, the count value of the processing target cell number counter 11b is set to “0”, and it is difficult to sufficiently distinguish the unused entries from unused entries. It is. That is, VCT
When valid data is stored in the cache means 13, the entry valid display signal 11n is in the ON state. However, the timing at which this signal 11n is turned off is important.

Since a plurality of cache entries are provided, the entry valid display signal 1
It is desirable to turn on 1n. This is because it is more likely that the cache can be reused when a subsequent cell is received. Conversely, if the entry valid display signal 11n is immediately turned off, reading and writing of data from the first memory 4 occurs every time a subsequent cell is received, and access efficiency is reduced. Therefore, it is necessary to delay the timing of turning off the entry valid display signal 11n.

Although the VCT cache means 13 has a plurality of entries, the number is limited.
Therefore, when an ATM cell is received by a VC exceeding the total number of entries, it is necessary to invalidate the old entry and load the management table 15 in the first memory 4 relating to the newly received VC.

Conventionally, as an algorithm for replacing an entry, for example, LRU (least recently used) is used.
d) method was used. In the LRU method, an entry accessed at the earliest time is invalidated, and a management table for a newly received VC is stored. However, according to this method, in order to determine at what time each entry is used, a means of recording a usage history for each entry and determining which is the oldest is required.
Therefore, the load on hardware or software for enabling such processing increases.

In the second embodiment, the entry replacement process is realized without increasing the load on the hardware or software. FIG. 6 shows a detailed configuration of the VCT cache control means in the ATM communication control device according to the present embodiment. Here, the VCT according to the first embodiment shown in FIG.
The same components as those of the cache control unit are denoted by the same reference numerals, and description thereof is omitted.

In comparison with the first embodiment, in the present embodiment, an idle time counter 11r is provided between the management table transfer instructing means 11u and the processing target cell number counter 11b.
The management table transfer instructing means 11
The difference is that a new operation is added to u. The counting operation of the idle time counter 11r is defined by whether the value of the activation signal 11t given from the processing target cell number counter 11b is logic “1” or “0”.
The activation signal 11t becomes logic “1” when the value of the processing target cell number counter is “0”, and the value of the counter is “0”.
In other cases, the logic becomes "0". The timing at which the count value is decremented is defined by a cell clock having a fixed cycle. The count operation procedure of the processing target cell number counter 11b is as shown in FIG.

When the activation signal 11t is logic "0",
The count value Cnt is set to an initial value “0”. When the activation signal 11t becomes logic "0", the count value Cnt is set to a predetermined value n. While the activation signal 11t is at logic "1", the count value Cnt is decremented by one assuming the idle time. Then, when the count value Cnt becomes "0", it outputs a processing end signal 11q and gives it to the management table transfer instructing means 11a. In addition, during the decrement, the activation signal 11t becomes logic “0”.
, The count value Cnt returns to n.

The management table transfer instructing means 11 u
Management table transfer instructing means 11a in the embodiment
Performs the same operation as that of the protocol processing end signal 11e.
Is given as follows. The protocol processing end signal 11e is a processing target cell number counter 11b.
And the count value of the counter 11b is "0"
And the unprocessed AT in the reception cell FIFO means 12
When the M cell no longer exists, the activation signal 11t is set to a value of “1”. When the start signal 11t is input to the idle time counter 11r, the predetermined value n
Starts decrementing one by one. Until the count value Cnt becomes “0”, the idle time counter 11r does not output the processing end signal 11q to the management table signal transfer instructing unit 11u. Therefore, the management table transfer instructing unit 11u does not determine that the entry has become invalid. When the count value Cnt is decremented to "0", the idle time counter 11r outputs a processing end signal 11q. Thereby, the management table transfer instructing unit 11u determines that the entry is invalid. Then, it outputs the cache entry number as the cache index signal 11i, outputs the transfer instruction signal 11h to the VCT transfer means 14, and outputs the entry valid display off control signal 11m to the coincidence detection means 11c. As a result, the entry valid display signal 11n output from the coincidence detecting means 11c is turned off.

While the idle time counter 11r is decrementing from the initial value n, the count value Cn
If a new ATM cell is received at a point in time when t has not reached “0”, the entry validity indication signal 11n
Is in the ON state. In this case, the entry can be determined to be valid, and the VCT cache unit 1
3 can be used.

As described above, according to the second embodiment,
The following effects are obtained in addition to the effects obtained by the above-described first embodiment. Only when an ATM cell is not received by the same VC until the count value Crt of the added idle time counter 11r elapses a predetermined time that is decremented from n to “0”,
The entry is determined to be invalid, and the management table 15 stored in the first memory 4 can be accessed. Conversely, before the fixed time elapses, A
When the TM cell is received, the entry is valid, and the access to the first memory 4 is not performed. As a result, the frequency of access to the first memory can be reduced. Further, when the count value Crt becomes “0” after a certain period of time, the entry becomes invalid because the entry valid display signal 11n is turned off. As a result, necessary entries can be secured in case an ATM cell is received by a new VC.

The above-described embodiment is merely an example, and does not limit the present invention. For example, FIG. 1, FIG. 3 or FIG.
Is an example, and it is not always necessary to provide all of these elements.

[0065]

As described above, in the ATM communication control method and apparatus according to the present invention, the first memory is provided outside the apparatus, the second memory is provided inside the apparatus, and the management table corresponding to the received cell is provided. Only when the data is not stored in the second memory, the data is read from the first memory, and the management table is stored in the first memory when all the reception processes of the cells belonging to the VC have been completed. It is possible to greatly reduce the frequency of accessing one memory and improve the processing efficiency of the entire system. In addition, since the latest management table is always stored in the second memory accessed by the processing unit that performs the protocol processing, a difference occurs between the timing of writing or reading the management table and the protocol processing unit 8. The control procedure is simplified without any problems.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of an ATM communication control device according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing contents of a management table used in the control device.

FIG. 3 is a circuit diagram showing a configuration of a VCT cache control unit in the control device.

FIG. 4 is a flowchart showing a procedure of a reception process of the control device.

FIG. 5 is a flowchart showing a procedure of processing when ATM cells are continuously received by the same VC in the same VC within a predetermined time in the control device.

FIG. 6 is a circuit diagram showing a configuration of a VCT cache control unit in an ATM communication control device according to a second embodiment of the present invention.

FIG. 7 is an explanatory diagram showing a count operation of an idle time counter in the VCT cache control means.

FIG. 8 is an explanatory diagram showing the structure of an ATM cell.

FIG. 9 is an explanatory diagram showing a protocol hierarchy in ATM communication.

FIG. 10 is an explanatory diagram showing the correspondence between AAL5 frames and ATM cells.

FIG. 11 is a circuit diagram showing a configuration of a conventional ATM communication control device.

[Explanation of symbols]

 Reference Signs List 1 CPU 2 Main memory 3 ATM communication device 4 First memory 5 Physical layer control means 6 System bus 7 Reception ATM cell bus 8 Protocol processing unit 9 Physical layer interface means 10 VC cache control means 11 VCT cache control means 11a Management table transfer instructing means 11b Target cell number counter 11c Coincidence detecting means 11r Idle time counter 12 Received cell FIFO means 13 VCT cache means 14 VCT transfer means 15 Management table 16 Transmission line 17 Receive line

Claims (6)

(57) [Claims] 1. An ATM communication control device for controlling a plurality of virtual communication lines to receive an ATM cell, extracting address information contained in the received ATM cell and specifying one of the virtual communication lines. A first memory for storing a management table including information for controlling each of the virtual communication lines; and copying and storing one of the management tables stored in the first memory. A second memory, an ATM cell storage unit for storing the received ATM cells, reading the management table from the second memory, and performing a protocol process on the ATM cells stored in the ATM cell storage unit; A protocol processing means for outputting a processing end signal when the processing is completed; and a communication between the first memory and the second memory. A management table transfer unit for transferring a table; and determining whether a management table for controlling the virtual communication line specified by the line specifying unit among the virtual communication lines is stored in the second memory. Determining means; counting means for counting the number of ATM cells stored in the ATM cell storing means; determining result of the determining means, count value of the counting means, and processing status of the protocol processing means. And a management table control means for controlling the management table transfer means. The management table control means includes a management table for controlling the virtual communication line identified by the line identification means by the determination means. If it is determined that the management table is not stored in the memory, the management table is read from the first memory and the second memory is read. Transferred to the protocol processing unit outputs the processing end signal, and the count value of said counting means in the ATM cell storage unit AT
When indicating that the M cell is not stored, the management table related to the ATM cell, which is stored in the second memory, is transferred to the first memory and written. ATM communication control device. 2. The management table control means checks that the protocol processing means outputs the processing end signal and that the count value of the counting means does not store the ATM cell in the ATM cell storage means. 2. The method according to claim 1, wherein after a predetermined time has elapsed from the indicated time point, the management table stored in the second memory, which is a management table for the ATM cell, is transferred to the first memory and written. The ATM communication control device as described in the above. 3. The ATM cell storage unit according to claim 1, wherein said ATM cell storage means stores information of an address at which a management table relating to said ATM cell is stored in said second memory together with said ATM cell. ATM communication control device. 4. An ATM communication control method for controlling a plurality of virtual communication lines to receive an ATM cell, wherein address information contained in the received ATM cell is extracted to specify one of the virtual communication lines. And storing a management table including information for controlling each of the virtual communication lines in a first memory; and copying any of the management tables stored in the first memory to a second memory. Storing the ATM cells in a memory; storing the received ATM cells in an ATM cell storage means; reading the management table from the second memory; and performing protocol processing of the ATM cells stored in the ATM cell storage means. A step performed by a protocol processing means, and a management table transfer procedure between the first memory and the second memory. Transferring the management table, and determining whether or not a management table for controlling the virtual communication line specified by the line specifying unit among the virtual communication lines is stored in the second memory. A step of counting the number of ATM cells stored in the ATM cell storage means; and a management table for controlling the virtual communication line specified by the line specification means stored in the second memory. If not, the management table is read from the first memory and transferred to the second memory. The protocol processing means completes the protocol processing and the count value is stored in the ATM cell storage means. Indicates that the ATM cell is not stored, the ATM cell stored in the second memory ATM communication control method characterized by comprising the step of writing to transfer the management table related to said first memory. 5. In the step of transferring and writing a management table related to the ATM cell stored in the second memory to the first memory, the protocol processing means terminates the protocol processing and Transferring the management table from the second memory to the first memory after a lapse of a predetermined time since the count value indicates that the ATM cell is not stored in the ATM cell storage means; 5. The ATM communication control method according to claim 4, wherein: 6. The method according to claim 1, wherein said step of storing said ATM cell comprises storing information of an address stored in said second memory together with said ATM cell in said management table relating to said ATM cell. The ATM communication control method according to claim 4 or 5, wherein