JP3219081B2 - Inverter fault diagnosis method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is directed to a multi-configuration inverter whose capacity is increased by connecting a single inverter or a plurality of unit inverters in parallel. , I
The present invention relates to a method for diagnosing a failure of an inverter for confirming presence / absence of an abnormality in a power semiconductor element such as a GBT and a gate drive power supply system element and identifying an abnormal part.

[0002]

2. Description of the Related Art As a conventional fault diagnosis apparatus for an inverter of this type, there is known an inverter whose basic circuit configuration is illustrated in the circuit diagrams of FIGS. Note that the two figures illustrate a case where the capacity is increased by a parallel multiplex configuration of three unit inverters, and the following description relating to the two figures will generally refer to the parallel connection of n unit inverters. In the case of multiplexing according to the above, the expansion can be similarly applied.

FIG. 3 showing a first embodiment of the prior art is an example in which three unit inverters are connected in parallel to each other on both input and output sides of each main circuit and multiplexed. The unit inverter will be referred to as an inverter unit in the following description. 11 ₁ to 11 ₃ without the same circuit configuration respectively, in FIG. 3, the inverter unit for outputting the required controlled alternating current load circuit 5 which forms a series connection with, for example, inductive coil and a capacitor to a common load is there.

[0004] The unit 11₁Let's take an example
For example, 14 is a rectifier having three-phase AC as its input, C_fIs the
Rectifier output voltage smoothing capacitor, Q₁~ Q_FourIs semiconductor
MOSFET as an example of a device, 22₁Is for each FET
A gate drive power supply that supplies gate drive power to
You. 3₁~ 3_FourIs the above element Q₁~ Q_FourCorresponding to each
A gate drive circuit provided as
22₁Supply of gate drive power from the
Switching order command signal necessary for inverter operation
Received a specified gate signal at a specified time.
Each corresponding element Q ₁~ Q_FourTo give.

Furthermore 20 ₁ to 20 ₄ are fault detection circuit provided corresponding to the FET respective elements Q ₁ to Q _4, it is constituted by a resistor and a photocoupler corresponding FE
Detects the presence or absence of a voltage between the drain and the source forming the opening and closing part of the T element, and detects the voltage between the drain and the source during normal inverter operation.
If the source-to-source voltage is always zero, the FET element is assumed to be in a short-circuit fault state between the drain and the source, and the detection result of the voltage is given to the fault display circuit 17 via the photocoupler.

[0006] Note that the to the fault display circuit 17 detects the signal input of a voltage presence or absence of the all of the fault detection circuit in each inverter unit 11 ₁ to 11 ₃ of the all FET device in the fault condition is identified Is displayed. Next, FIG. 4 showing a second embodiment of the prior art differs from FIG. 3 only in the connection of the rectifier of the DC intermediate circuit in the three inverter units. That each inverter unit shown in FIG. 3 11 ₁ to 11 ₃ 3 pairs of smoothing capacitor C _f in respective DC intermediate circuit and is integrated three sets of rectifier 14 to a pair of common rectifier 4 in each of the DC intermediate circuit Are connected in parallel with each other and the rectifier 4
In this way, the inverter units 11 _{1 to} 11 ₃ are respectively charged by 21 ₁ to 2 _1.
1 ₃ is obtained by sign change. The failure diagnosis of each element of the FET is the same as in the case of FIG.

[0007]

In the conventional fault diagnosis apparatus, as shown in FIGS. 3 and 4, in order to identify a faulty element among a plurality of semiconductor elements in each inverter unit, the fault diagnosis apparatus is used. Each semiconductor device has its own dedicated fault detection circuit, which increases the number of fault detection circuits and the number of wires between related devices. Had to be priced.

Further, with respect to the failure diagnosis function, the conventional failure diagnosis apparatus can determine the short-circuit state of each semiconductor element itself, but cannot determine the failure of related elements such as the gate drive circuit. Since the inverter units are connected in parallel at the respective rectifier inputs or at both the positive and negative terminals of the respective DC intermediate circuit smoothing capacitors and also at the respective inverse converter outputs, the inverter units are connected in parallel. If both the upper and lower arms of the bridge configuration are in a short-circuit state, the DC intermediate voltage in all inverter units is lost, and each of the semiconductor elements is erroneously displayed as being in a fault state, and the fault diagnosis function itself is lost, If one of the upper and lower arms is short-circuited, the inverter unit to which the short-circuited arm belongs is specified. There is a problem that can not.

When the upper and lower arms are short-circuited, the inverter is naturally protected by another overcurrent protection function or the like. In view of the above, the present invention aims at miniaturization and reduction of the number of wirings between related devices, and in terms of its failure determination function, specifies all of the semiconductor devices by classifying each device itself and its gate control system related element. It is an object of the present invention to provide a method of diagnosing a fault of an inverter which can perform the fault diagnosis.

[0010]

Means for Solving the Problems To achieve the above object, a method for diagnosing a fault of an inverter according to the present invention has the following configuration. That is, 1) The invention according to claim 1 is a method for diagnosing a failure of an inverter for determining a failure of a plurality of semiconductor elements constituting a main circuit of an inverter and a related part thereof. A gate drive power determining means for detecting an excessive or insufficient state of a gate drive power from a predetermined value with respect to each of the semiconductor elements and determining a failure with respect to each semiconductor element and its gate drive system related element; and a rectifier output voltage in a DC intermediate circuit of the inverter. The smoothing capacitor is charged with a predetermined DC constant current, and the length of time required for the charging voltage of the capacitor to reach the predetermined value is detected from the predetermined value to thereby make the semiconductor an arm element. And a charging state determining means for determining an arm short-circuit state in the bridge configuration. In accordance with the result of the gate drive power determination and the result of the charge state determination, the semiconductor element in a failure state and its gate drive system related element are specified. Also, 2) the invention according to claim 2 is directed to a multi-configuration inverter composed of a plurality of unit inverters connected in parallel,
A fault diagnosis method for an inverter for performing fault determination of a plurality of semiconductor elements constituting a main circuit of each unit inverter and a related part thereof, wherein at the time of the fault diagnosis, a gate drive power for the semiconductor element is calculated from a predetermined value. Gate drive power determining means for detecting an excessive or under state of each of the semiconductor elements and determining a failure relating to each semiconductor element and its gate drive related elements, and a rectifier output voltage smoothing capacitor in the DC intermediate circuit of the inverter is connected to a predetermined DC constant. An arm short-circuit state in the bridge configuration in which the semiconductor is used as the arm element is determined by detecting the length of time required for the charging voltage of the capacitor to reach the predetermined value and at the same time from the predetermined value while charging the capacitor with the current. Charge state determination means, and the gate drive power determination result by the both determination means and Shall specific semiconductor device and a gate drive system associated element in the fault condition in accordance with the electrostatic status decisions performed for all of the unit inverter.
Further, 3) the invention according to claim 3 is the inverter failure diagnosis method according to claim 1 or 2, wherein the gate drive power judging means sets both the ON state and the OFF state of a gate drive signal for each of the semiconductor elements. In the above, the predetermined failure determination as described above is performed. 4) The invention according to claim 4, wherein in the fault diagnosis method for the inverter according to claim 1 or 2, the state of charge is determined by turning off all gate drive signals for the respective semiconductor elements in the bridge configuration. And a sequential ON command state in accordance with a predetermined order, the semiconductor elements belonging to the arm in the short-circuit state are specified. 5) The invention according to claim 5 is the inverter failure diagnosis method according to any one of claims 1 to 4, further comprising failure display means for respectively displaying the failure states specified as described above. Shall consist of

For example, MOSF as a power semiconductor element
In ET, if the drain and source of the element are broken for some reason and short-circuited, the gate and source of the element will also be short-circuited in most cases. Therefore, when the gate drive signal is applied to the FET element in the short-circuit state, the gate drive power input to the element becomes larger than the normal value. That is, it is possible to detect the short-circuit state of the FET element by comparing the gate drive power with the value at the time of normal operation.

A gate drive system of the FET element includes, for example, a gate drive power supply that supplies gate drive power, and a gate drive circuit that operates by receiving power supply from the drive power supply and a gate drive signal to the element. In the case where the gate drive power is off when the gate drive signal for the FET element is off, the gate drive power supply or the gate drive circuit itself may be faulty if the gate drive power is too large or too small compared to the predetermined value. Further, a failure may occur in a portion other than the element such as a contact failure or a short circuit between wirings in a wiring path from the gate drive power supply to the FET element.

That is, the MOSFET or SIT, I
In a power semiconductor device such as a GBT, by comparing the gate drive power with a predetermined value of the gate drive signal in both the ON and OFF states of the gate drive signal for the semiconductor device, whether a failure has occurred in the semiconductor device itself or in the semiconductor device itself. It is possible to determine whether the element is in the gate drive power supply system element other than the semiconductor element.

A voltage type inverter generally has a DC intermediate circuit comprising an AC input rectifier circuit and an output voltage smoothing capacitor, and an inverse converter comprising a plurality of semiconductor elements forming a bridge. Further, a time constant for charging the capacitor is defined by a power supply path from the inversion section to the load circuit, an equivalent resistance value and an equivalent inductance of the load circuit itself, and a capacitance of the capacitor.

Therefore, the charging time constant is determined in both states when the semiconductor elements constituting the inverse conversion unit are performing on / off operations in a predetermined order and when all the semiconductor elements are in the off state. Correspondingly, they have different predetermined values, and if the charging time constants corresponding to the two states are different from the respective predetermined values, this is due to an abnormality in any of the time constant-related parameters. It will be.

The change of the charging time constant as described above is related to the time required for the capacitor terminal voltage to reach a predetermined value by charging the capacitor whose residual charge has been reduced to zero with a predetermined DC constant current. This becomes possible by determining the difference from the predetermined time. If the charging time constant becomes smaller than the predetermined value when all of the semiconductor elements are in the off state, depending on the degree, the simultaneous time in the in-phase or out-of-phase upper and lower arms in the bridge configuration of the inverting unit is changed. This indicates a short circuit, and when the upper and lower arms are not simultaneously short-circuited, it is possible to specify an abnormal arm by sequentially turning on the semiconductor elements constituting the bridge in a predetermined order.

The present invention is directed to a multi-configuration inverter whose capacity is increased by connecting a single inverter or a plurality of inverter units in parallel, and a gate drive power for each semiconductor element constituting a bridge in each of the inverters. The determination of whether the failure site is in the semiconductor element itself or in the element of the gate drive power supply system other than the semiconductor element and the identification of the inverter unit to which it belongs are performed by the determination of By determining the required charging time in DC constant current charging of the smoothing capacitor, it is possible to specify an abnormal semiconductor element in the inverter unit or to specify a simultaneous short-circuit phase of the upper and lower arms.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the circuit diagram of FIG. 1 and the flowchart of FIG. In FIG. 1, components having the same functions as those of the embodiment of the prior art shown in FIGS. 3 and 4 are denoted by the same reference numerals. Figure 1 is the circuit diagram shown in and FIG. 4 shows an embodiment of the present invention, a gate drive power supply 22 ₁
To 22 ₃ and the control circuit 16 and the failure detection circuit in each inverter unit with the respective changes with respect to the fault display circuit 17 to change by performing a function addition each 20
Deprived of ₁ to 20 _4, and further by adding a constant current source 8, and the following each change of the units 21 ₁ to 21 ₃ to sign changes as each 1 ₁ to 1 _3.

[0019] That is added as function to add emits a signal indicating the gate drive power value output of each of the drive power source for the gate drive power supply 22 _{1-22 3,} obtained by sign change as each 21 _{to 24} is there. Further, the control circuit 6 supplies an instruction signal of an inverter operation during normal synchronous parallel operation to the three inverter units, and receives a command of the failure determination display circuit 7 during the failure diagnosis operation so that each of the inverter units is controlled. , A gate drive signal is given to each semiconductor element in a predetermined order, and the control circuit 16 is added with the function for the failure diagnosis operation.

Next, the constant current source 8 charges each of the smoothing capacitors C _f of each of the inverter units with a predetermined DC constant current, and the terminal voltage of the capacitors is designated by a constant voltage diode or the like by the charging. When the predetermined voltage is reached, the arrival signal is supplied to the failure determination display circuit 7 via a photocoupler or the like. Further, the failure determination display circuit 7 includes the inverter units 11 ₁ to 11.
1 receives a signal of the respective output gate drive power values from each of the gate drive power supply _{21 to 24} in the _3, the inverter unit with abnormal semiconductor element via the comparison between the predetermined value of the respective power values Identify and set the constant current source 8
Performs a specific abnormality semiconductor in the inverter unit that determines the length of its required value of the time required until the signal generated in the abnormal state of the receiving said charge reaching signal regarding capacitor C _f from is there.

Next, a failure diagnosis operation performed by each element having the above-described various functions will be described below with reference to the flowchart of FIG. First, each of the inverters is controlled by a command signal from the control circuit 6 which receives an instruction from the failure determination display circuit 7.
Semiconductor elements in the unit _{1 1 ~1 3} (MOSFE
T) Q ₁ to Q ₄ is performed in the failure determination display circuit determines the gate drive power value is normal or not the output to the gate signal to all off and no state in the gate drive power supply 21 _{to 24} were against, In the event of an abnormality, the inverter unit to which the abnormality occurrence site belongs is identified on the assumption that contact failure of each gate drive power supply, each gate drive circuit or signal line has occurred.

Next, in the same manner, each of the aforementioned semiconductor elements Q ₁
The appropriateness of the gate drive power value output of each gate drive power supply ₂₁ to ₂₄ in a state that no all on the gate driving signal to to Q ₄ determines in the failure determination display circuit, a semiconductor which is in short-circuit state The inverter unit having the element is specified. Subsequently, the control circuit 6 and the constant current source 8 having received the instruction from the failure determination display circuit 7 previously turn off the gate drive signals for the respective semiconductor elements Q _{1 to} Q ₄ in a state where they are all turned off. Each of the capacitors whose residual charges have been reduced to zero is charged with a predetermined DC constant current, and the failure determination display circuit determines whether the time required for the capacitor terminal voltage due to the charging to reach the predetermined value is appropriate. If charging is not possible and the required time is long, it is determined that the fault condition in the specified inverter unit is a simultaneous short circuit of the in-phase upper and lower arms in the bridge configuration, and if charging is possible, In the state where the gate drive signals according to a predetermined order are applied to the semiconductor elements Q _{1 to} Q ₄ , the same capacitor charging as described above is performed, and the charging time for each time is calculated. Suitability is determined by the failure determination display circuit, and a semiconductor element in a failure state is specified.

[0023]

According to the present invention, a single inverter or a multi-configuration inverter whose capacity is increased by connecting a plurality of inverter units in parallel is intended. By judging the appropriateness of the value, it is determined whether the failure site is in the semiconductor element itself or in a gate drive power supply system element other than the semiconductor device, and the inverter unit having the failure site is specified. Further, by determining the required charging time by the DC constant current charging of the smoothing capacitor as described above, it is possible to specify an abnormal semiconductor element in the abnormal inverter unit or to specify a simultaneous short-circuit phase of the upper and lower arms. With this configuration, in terms of its failure determination function, all the semiconductor elements that make up the circuit The device itself can be separated from its gate control system related elements to enable identification of a failure site, and also to be possible to reduce the size and cost by reducing the number of wires between related devices. Can be.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a fault diagnosis device for an inverter according to an embodiment of the present invention.

FIG. 2 is a flowchart corresponding to FIG. 1;

FIG. 3 is a circuit diagram of an inverter failure diagnosis apparatus according to a first embodiment of the prior art.

FIG. 4 is a circuit diagram of an inverter failure diagnosis apparatus according to a second embodiment of the prior art.

[Explanation of symbols]

1 _n inverter unit (n = 1, 2, 3) 2 _n gate drive power supply (n = 1, 2, 3) 3 _n gate drive circuit (n = 1, 2, 3, 4) 4 rectifier 5 load circuit 6 Control circuit 7 Failure judgment display circuit 8 Constant current source 11 _n Inverter unit (n = 1, 2, 3) 16 Control circuit 17 Failure display circuit 20 _n Failure detection circuit (n = 1, 2, 3, 4) 21 _n Inverter unit (n = 1,2,3) 22 _n Gate drive power supply (n = 1,2,3) C _f Rectification voltage smoothing capacitor Q _n Semiconductor device such as MOSFET (n = 1,2,3)
3)

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-60-118065 (JP, A) JP-A-63-99778 (JP, A) JP-A-1-126172 (JP, A) JP-A-1- 129170 (JP, A) JP-A-4-135077 (JP, A) JP-A-3-269268 (JP, A) JP-A-3-94036 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H02M 7/48 G01R 31/02 G05F 1/10 304 H02M 7/537

Claims (5)

(57) [Claims] 1. A method for diagnosing a fault in an inverter for determining a fault in a plurality of semiconductor elements constituting a main circuit of the inverter and related parts, the method comprising the steps of: A gate drive power determining means for detecting an over- or under-state from the value and performing failure determination on each semiconductor element and its gate drive-related elements, and a capacitor for smoothing a rectifier output voltage in a DC intermediate circuit of the inverter by a predetermined amount. An arm short-circuit state in the bridge configuration in which the semiconductor is used as the arm element is detected by detecting the length of time required for the charging voltage of the capacitor to reach the predetermined value while detecting the length of the required time until the charging voltage of the capacitor reaches the predetermined value. Charge state determining means for determining the gate drive power by the two determination means. A charging state semiconductor device is in the failure state determination result and in accordance with, and failure diagnosis method of an inverter, which comprises carrying out a specific its gate drive system related elements. 2. A method of diagnosing a fault in an inverter, which is intended for a multi-configuration inverter composed of a plurality of unit inverters connected in parallel, and determines a fault in a plurality of semiconductor elements constituting a main circuit of each unit inverter and related parts thereof. In the failure diagnosis, a gate drive power determination for detecting an excessive or insufficient state of a gate drive power for the semiconductor element from a predetermined value and performing a failure determination for each semiconductor element and its gate drive system related element. Means for charging a capacitor for smoothing the rectifier output voltage in the DC intermediate circuit of the inverter with a predetermined DC constant current, and increasing or decreasing the time required for the charged voltage of the capacitor to reach the predetermined value from the predetermined value. To determine the arm short-circuit state in the bridge configuration using the semiconductor as the arm element. Made and a charging state determining means,
An inverter for performing identification of a faulty semiconductor element and its gate drive system related element for all of the unit inverters in accordance with the gate drive power determination result and the charge state determination result by the two determination means. Fault diagnosis method. 3. The method for diagnosing a fault in an inverter according to claim 1, wherein said gate drive power judging means determines said predetermined fault in both ON and OFF states of a gate drive signal for each of said semiconductor elements. A fault diagnosis method for an inverter, wherein the fault diagnosis is performed. 4. A fault diagnosis method for an inverter according to claim 1, wherein said charge state determination means is sequentially turned on in accordance with a predetermined order in a state in which all gate drive signals for each semiconductor element in said bridge configuration are turned off. A fault diagnosis method for an inverter, characterized in that a semiconductor element belonging to an arm in a short-circuited state is specified in both states. 5. A method for diagnosing a fault in an inverter according to claim 1, further comprising fault display means for displaying each of the fault states specified as described above. Fault diagnosis method.