JP3219984B2 - Phase locked oscillator and communication device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase-locked oscillator for outputting an output wave synchronized with an externally inputted reference oscillation wave, and a communication device.

[0002]

2. Description of the Related Art FIG. 21 shows, for example, "Frequency Synthesizers".
ers), Third Edition, pp. 379-380, Badim
By Manarswitt (Vadim Manassew)
t), John Willy and Sons Publishing (Joh
n Wiley & Sons), wherein 1 is a phase-locked oscillator (hereinafter, referred to as a PLL). 2 is an input terminal for inputting a reference oscillation wave fin from the outside, 3 is a phase comparator for outputting an error signal corresponding to the phase difference between the reference oscillation wave and the feedback signal wave fm from the multiplier 6, and 4 is the error thereof. A loop filter 5 for reducing high-frequency noise of the signal and an output wave fout 5 based on the error signal passed through the loop filter 4
Voltage-controlled oscillator (hereinafter, referred to as VCO) that outputs
Is a multiplier for multiplying the frequency of the output wave of the VCO 5 by N, 7 is V
Output terminal for outputting the output wave of CO5.

Next, the operation will be described. In FIG. 21, when a reference oscillation wave fin is input from the outside to the input terminal 2, an output wave fin / N whose frequency is divided by N is output from the output terminal 7. To describe this operation in detail, the reference oscillation wave fin is supplied to the phase comparator 3 by V
The output signal fout of the CO 5 is compared in phase with the feedback signal wave fm multiplied by N by the multiplier 6. An error signal Vout corresponding to the phase difference φ between the reference oscillation wave fin and the feedback signal wave fm is output from the phase comparator 3, further amplified by the loop filter 4, filtered, and subjected to VCO 5 as a frequency control voltage.
Is applied to

The PLL 1 stabilizes synchronization when the frequency of the reference oscillation wave fin coincides with the frequency of the feedback signal wave fm. Therefore, fin = fm = N · fout∵fout = fin / N (1) As described above, it is understood that the frequency of 1 / N of the reference oscillation wave fin is output from the PLL 1 and the PLL 1 operates as a frequency divider.

An advantage of operating the PLL 1 as a frequency divider is that the PLL 1 operates as a narrow-band band-pass filter with respect to the reference oscillation wave fin. Generally, assuming that the open loop gain of the PLL is G (s), FIG.
The transfer gain H (s) between the input and output terminals of the PLL 1 is as follows: H (s) = G (s) / [N ｛{1 + G (s)}] G (s) = N · Kv · Kp · F (s) ) / S (2). Here, Kv is the sensitivity of the VCO 5, Kp is the sensitivity of the phase comparator 3, F (s) is the gain of the loop filter 4, s
Is the angular frequency at s = jω.

According to equation (2), the pass characteristic of the PLL is as shown in FIG. In the figure, the loop band is | G (s) | =
This loop band is a pass band with respect to the center frequency. Therefore, as shown in FIG.
When an input wave including noise is input to the PLL, the noise component is attenuated in the output wave. As described above, since the frequency divider having the PLL configuration has not only a simple frequency dividing function but also a filtering function, for example, in satellite communication where the line noise is at a high level,
It is used for reproducing a reference frequency from a pilot signal.

As a phase comparator used in such a frequency divider having a PLL configuration, a general diode balanced mixer shown in FIG. 24 has been reported. In FIG. 24, 11 is a ring diode composed of four diodes 11a to 11d, 12a and 12b are baluns, 13 is an input terminal, 14 is a multiplier side terminal, and 15 is an output terminal. The input wave fin and the output wave N of the multiplier 6 are
Fout is supplied to the ring diode 11. The input wave fin and the output wave N · fout are analog-multiplied by the nonlinearity of the diodes 11a to 11d.
A mixed wave | fin−N · fout | of fin and N · fout | generated by the analog multiplication is synthesized by the balun 12 and output to the output terminal 15. On the other hand, fin and N.
Fout is canceled by the balun 12 and is not output to the output terminal 15. As described above, since the mixed wave | fin−N · fout | can be extracted without using a filter, there is an advantage that a small phase detector can be configured, and it is generally used.

[0008] In such a phase comparator, "Mixers as phase detector (Mixers as phase detector)" is used.
phase detector), Vol. 5, 1978
Diode 1 as described in
If the characteristics of 1a to 11d are not uniform, each diode 1
The rectified currents in 1a to 11d are not canceled out, resulting in a DC offset. This is the diode 1 shown in FIG.
1a to 11d inconsistency in DC characteristics or balun 12
This is due to the imbalance between a and 12b.

When operated as a PLL, as shown in FIG. 26, in the original ideal state, the DC gain of the loop filter is sufficiently high, so that the detection voltage Vpc is around 0 V and the phase difference φ is around 0 degree. Is the operating point. However, PL using a phase comparator with a DC offset
At L, the operating point moves to offset the DC offset Vdc. At this time, the detection voltage Vp for the phase difference φ
The sensitivity Kp of the phase comparator given by the derivative of c is lower than the sensitivity at the phase difference φ = 0. That is, the operating point and the sensitivity K of the phase comparator are determined by the value of the DC offset voltage Vdc.
p changes, and as a result, the transfer characteristics G (s), H of the PLL
(S) changes.

Generally, this DC offset voltage Vdc
In this case, the transfer characteristics of the PLL become unstable because the mixer varies depending on the variation of the mixer and the temperature of the same mixer. For example, as shown in FIG. 27, at a high temperature, the DC offset voltage Vdc increases due to an increase in the rectified current, so that the detection sensitivity Kp decreases, and the transfer characteristic G (s) decreases as is clear from the equation (2). Gain. As a result, at high temperatures, the loop band is narrowed as shown in FIG. 28, and the noise suppression characteristics fluctuate. Further, in the PLL having the conventional configuration, as shown in FIG. 29, a filter 20 for suppressing the spurious component is required at the output of the multiplier 6, and the device becomes large in some cases.

[0011]

Since the conventional phase-locked oscillator is configured as described above, the characteristics of the diodes 11a to 11d used in the phase comparator are not uniform, the variation of the mixer, Since the DC offset voltage Vdc changes due to a temperature change, the transfer characteristics of the PLL become unstable, the loop band becomes narrower, and the noise suppression characteristics fluctuate. In addition, a filter 20 for suppressing spurious components is required at the output of the multiplier 6, and there is a problem that the device becomes large in some cases. Further, when the number of multiplications N increases, the number of the multipliers 6 increases, so that there is a problem that the size of the apparatus becomes large and the price becomes high.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has as its object to obtain a phase-locked oscillator that suppresses a change in transfer characteristics due to a DC offset voltage and reduces the number of filters and multipliers. And It is another object of the present invention to provide a communication device that is small in size and suppresses fluctuations in noise characteristics.

[0013]

According to a first aspect of the present invention, there is provided a phase-locked oscillator which uses, as a phase comparator, an even harmonic mixer including an anti-parallel diode pair in which two diodes of opposite polarities are connected in parallel. It was what was.

A phase-locked oscillator according to a second aspect of the present invention uses an even harmonic mixer including a ring diode and a balanced / unbalanced conversion circuit as a phase comparator.

The phase-locked oscillator according to a third aspect of the present invention uses an external reference oscillation wave as a high-frequency signal of the even harmonic mixer, and outputs a local oscillation wave of the even harmonic mixer from the voltage controlled oscillator. It uses waves.

According to a fourth aspect of the present invention, there is provided a phase locked oscillator which uses an output wave from a voltage controlled oscillator as a high frequency signal of an even harmonic mixer and an external reference oscillation as a local oscillation wave of the even harmonic mixer. It uses waves.

According to a fifth aspect of the present invention, there is provided a phase locked oscillator in which a frequency divider is connected between a voltage controlled oscillator and an even harmonic mixer.

According to a sixth aspect of the invention, there is provided a phase locked oscillator in which a multiplier is connected between the voltage controlled oscillator and the even harmonic mixer.

According to a seventh aspect of the present invention, there is provided a phase locked oscillator, wherein a limiter is provided between at least one of the voltage controlled oscillator and the even harmonic mixer and the input side of the reference oscillation wave of the even harmonic mixer. Connected.

The phase-locked oscillator according to the present invention has a filter between at least one of the input between the voltage controlled oscillator and the even harmonic mixer and the input side of the reference oscillation wave of the even harmonic mixer. Connected.

According to a ninth aspect of the present invention, there is provided a phase locked oscillator in which a terminal resistor exceeding 50 ohms is connected to the output side of the even harmonic mixer.

According to a tenth aspect of the present invention, there is provided a communication device comprising:
A transmission signal of a wireless or wired line is input to a phase comparator of a phase locked oscillator according to any one of claims 1 to 9 as a reference oscillation wave.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. In FIG. 1, reference numeral 1 denotes a phase locked oscillator (hereinafter, referred to as a PLL). 2 is the reference oscillation f
The input terminal 3 for inputting in is a phase comparator that outputs an error signal corresponding to the phase difference between the reference oscillation wave fin and the feedback signal wave fm. In this embodiment, an even harmonic mixer is used. I have. Reference numeral 4 denotes a loop filter for reducing high-frequency noise of the error signal, reference numeral 5 denotes a voltage-controlled oscillator (hereinafter, referred to as VCO) that outputs an output wave fout based on the error signal passing through the loop filter 4, and reference numeral 7 denotes an output wave of the VCO 5. Output terminal.

Next, the operation will be described. The even harmonic mixer 30 is generally referred to as “harmonic mixing with an anti-parallel diode pair (Harm).
onic mixing with an antip
ararrell diode pair), 197
5 years Published by IEEE, IEE Trans on Microweb Theory and Techniques, Vol. 23, No. 8, pp. 667 to 673 (IEEE Trans. Microwav)
e theoryand techniques, vo
l. MTT-23, No. 8, p677 to p673) "
2 is shown in FIG.

In FIG. 2, 31 is a demultiplexing circuit, 32 is an anti-parallel diode pair (hereinafter referred to as APDP).
APDP 32 is composed of diodes 32a and 3a having opposite polarities.
2b are connected in parallel. Generally, this APD
A high-frequency signal (hereinafter, referred to as RF) and a local oscillation wave (hereinafter, referred to as LO) are added to P32 via a branching circuit 31, and an intermediate frequency signal (hereinafter, referred to as IF) is extracted. In this embodiment, a baseband signal (hereinafter, referred to as BB) is extracted instead of the IF.

When LO is applied to the even harmonic mixer 30, as shown in FIG.
Since a and 32b are turned on and current flows, the conductance increases every half cycle. Therefore, there are only odd-order harmonics of LO and even-order harmonics of conductance. And these two diodes 32a, 32b
Can suppress even-order harmonics of the LO and odd-order harmonics of the conductance, so that much higher suppression can be achieved as compared with a normal balanced mixer that depends on the characteristics of the balun. Incidentally, in the case of a microwave, the suppression is about 25 dB in a normal balanced mixer, but in the even harmonic mixer 32, the suppression is 50 to 60 dB. When the output frequency fout of the even harmonic mixer 30 is expressed by an equation,

Fout = | m · frf ± n · fp | (3) where m and n are integers and | m ± n | is an odd number frf is the RF frequency and fp is the LO frequency. Therefore, in a normally used order, fout = | frf−2fp | (4) Therefore, since it can be operated at half fp, most of the configurations including the reference literature are applied to a transceiver having a heterodyne configuration in a microwave, especially a millimeter wave.

[0028] Such even harmonic mixer 30 PLL1
FIG. 4 shows a frequency relationship when applied to the receiving device of FIG.
As it can be seen from equation (4), since the fout = 0 at the time of phase synchronization PLL1, LO (fp) is RF (fr
This is almost half the frequency of f). In other words, the function of the doubler is also used, so that one doubler is not required, and it is possible to reduce the size and cost.

[0029] Such even harmonic mixer 30 PLL1
, The DC offset of the even harmonic mixer 30 is m = 0 in equation (3), and m + n = 0 in n = 0.
Which is strongly suppressed because it can be regarded as an even order.
Moreover, as described above, compared to a normal mixer,
Since the value is reduced by 20 dB or more, the value becomes practically negligible. Therefore, it is possible to suppress the fluctuation of the PLL 1 due to the presence of the DC offset. Conventionally, there is no case where the even harmonic mixer 30 is applied to the phase comparator of the PLL 1 .
This time, by focusing on the low DC offset characteristic of the even harmonic mixer 30 and applying it to the phase comparator of the PLL 1, a new effect of stabilizing the phase locked loop has been found.

FIGS. 5 and 6 show specific configuration diagrams of the even harmonic mixer 30. FIG. In FIG. 5, 34 is an open-end stub, 35 is a short-circuited stub, 36 is an RF choke,
37 is a DC cut. In the figure, the open-end stub 34 and the short-circuit stub 35 are a quarter at the LO frequency.
Since the wavelength and the RF frequency are half the wavelength and are short-circuited or opened at the terminals of the anti-parallel diode pair 32, the RF and the LO can be separated. In addition, the RF and the BB are separated by the RF choke 36 and the DC cut 37.

In FIG. 6, reference numeral 38 denotes a lumped constant tip open stub, and 39 denotes a lumped constant tip short stub. FIG.
Is a circuit in which stubs are lumped and performs the same operation by appropriately setting values of inductors and capacitors. Similar effects can be obtained even when these mixers are used as the phase detector of PLL1 .

As described above, in this embodiment,
By using an even harmonic mixer capable of outputting a mixed wave of a doubled wave of the LO and RF as the phase detector, the LO can be reduced to の of the RF. Therefore, one doubler can be dispensed with, and the size and the cost can be reduced. Further, since only odd-order mixed waves are generated in principle, 0
The level of the DC offset, which is the next component, is extremely low, and fluctuations in the transfer characteristics of the phase locked loop due to temperature and the like can be avoided.

Embodiment 2 FIG. In the first embodiment, the even harmonic mixer using the anti-parallel diode pair 32 has been described, but the even harmonic mixer may be configured using a ring diode. FIG. 7 is a configuration diagram showing an even harmonic mixer using a ring diode. In the figure, reference numeral 40 denotes a balun for balanced / unbalanced conversion (balanced / unbalanced conversion circuit, 180-degree distributor); 41, a ring diode; Reference numeral 42 denotes a branching circuit for RF input and BB output.

Next, the operation will be described. In this even harmonic mixer, the LO input is connected to a balun 40 for balanced / unbalanced conversion.
And is added to the ring diode 41. A ring diode 4 that isolates the RF input wave from the LO terminal via the branching circuit 42
1 to the orthogonal node 43. Ring diode 41
The internally generated mixed wave of the second harmonic of the LO and the RF input wave is generated between the node 43 and the ground conductor, and can be extracted through the branching circuit 42. Therefore, it operates in the same manner as the configuration using the anti-parallel diode pair described in the first embodiment, and has the same effect. Further, since the LO and RF demultiplexing stubs are not used, an even harmonic mixer operating in a wide frequency band can be obtained, and the size can be reduced. Therefore, it is possible to increase the bandwidth and the size of the PLL.

In the above description, the even harmonic mixer using the ordinary ring diode 41 is shown. However, as shown in FIG. 8, an anti-parallel ring diode in which anti-parallel diode pairs 44a to 44d are connected in a ring shape is used. (Ring diode) 44, and a similar effect is obtained.

As described above, in this embodiment, by using the even harmonic mixer composed of the ring diode and the balun, the even harmonic mixer can be reduced in size and can have a wider band.

Embodiment 3 In this embodiment, as shown in FIG. 9, the LO terminal of the even harmonic mixer 30 of the first embodiment is connected to the VCO 5, the RF terminal is connected to the input terminal 2, and the output wave fo of the VCO 5 is connected.
In this configuration, the difference frequency component between the second harmonic of ut and the input wave fin is output from the even harmonic mixer 30. Since the PLL 1 operates so that 2fout = fin, eventually fout = fin / 2. Therefore, the PLL 1 as a whole has a function as a frequency divider, and the same effects as those of the first embodiment can be obtained with respect to miniaturization and stabilization of the PLL 1.

Embodiment 4 FIG. In this embodiment, as shown in FIG.
The LO terminal of the even harmonic mixer 30 of FIG.
The terminal is connected to the VCO 5, and the difference frequency component between the second harmonic of the external input wave fin and the output wave fout is output from the even harmonic mixer 30. 2f is as PLL1
In order to operate so that in = fout , after all, fou
t = 2 · fin. Therefore, the PLL 1 as a whole has a function as a multiplier, so that the size of the PLL 1 can be reduced.
The same effect as in the first embodiment can be achieved with respect to stabilization and the like.

Embodiment 5 In this embodiment, as shown in FIG.
The LO terminal of the even harmonic mixer 30 is connected to the input terminal 2 and the frequency divider 50 is connected between the VCO 5 and the RF terminal of the even harmonic mixer 30 to obtain a second harmonic of the external input wave fin. And a difference frequency component between the output wave fout and the N-frequency component fout / N is output from the even harmonic mixer 30. Since the PLL 1 operates so that fout / N = 2 fin, eventually fout = 2N · fin. Accordingly, the PLL 1 as a whole has a function as a multiplier, and the same effects as those of the first embodiment can be obtained with respect to miniaturization and stabilization of the PLL 1. FIG.
May be exchanged between the LO terminal and the RF terminal of the even harmonic mixer 30, and fout = N · fin / 2, but the other effects are exactly the same.

Embodiment 6 FIG. In this embodiment, as shown in FIG.
The RF terminal of the even harmonic mixer 30 is connected to the input terminal 2 and the multiplier 51 is connected between the VCO 5 and the LO terminal of the even harmonic mixer 30, so that an external input wave fin
And the output wave fout, the doubled wave 2N of the N multiplied wave N · fout
A configuration in which the fout difference frequency component is output from the even harmonic mixer 30; The PLL1 2N · fout = fi
n so that fout = fin /
(2N). Therefore, the PLL 1 as a whole has a function as a frequency divider, and the same effects as those of the first embodiment can be obtained with respect to miniaturization and stabilization of the PLL 1.
Further, the LO terminal and the RF terminal of the even harmonic mixer 30 in FIG. 12 may be exchanged, and fout = 2 · fin / N, but the other effects are exactly the same.

Embodiment 7 FIG. FIG. 13 shows the conversion loss of the even harmonic mixer 30 with respect to the local oscillation power. The ordinary fundamental wave mixer has a saturation characteristic and a stable conversion loss with respect to the local oscillation power is obtained, but the even harmonic mixer 30 is not stable. This is because in the anti-parallel diode pair 32, when the local oscillation power is increased, the time during which both the diodes 32a and 32b are turned on becomes longer, and finally both the diodes 32a and 32b are turned on, so that nonlinearity is lost. It is a phenomenon that occurs. Therefore, if the local oscillation power fluctuates due to temperature, etc., the PLL
1 has a problem that the transmission gain greatly varies. Further, the output level changes linearly with respect to the RF level input to the even harmonic mixer 30, and the transmission gain of the PLL 1 also largely fluctuates.

Therefore, in the PLL 1 according to this embodiment, as shown in FIG. 14, limiters 52a and 52b are provided at both the RF and LO input terminals of the even harmonic mixer 30, and the input level to the even harmonic mixer 30 is adjusted. The fluctuation is suppressed. FIG. 15 shows a characteristic diagram of the limiters 52a and 52b.
As a result, the even harmonic mixer 30 with limiter shown in FIG.
The characteristics of are that the limiters 52a, 52b
Stabilizes with the effect of In addition, since many harmonics are emitted from the limiters 52a and 52b, as shown in FIG.
May be provided to suppress harmonics. Further, in the above description, the limiters 52a and 52b are provided at both the RF and LO input terminals of the even harmonic mixer 30. However, depending on the amount of change in the signal level, either one of them may have the same effect.

Embodiment 8 FIG. If an unnecessary wave is present in the input wave to the even harmonic mixer 30,
Since higher-order mixing is performed in the even harmonic mixer 30, spurious may occur in a band in some cases. Therefore, the filter 54 is provided to both the RF and LO input terminals of the even harmonic mixer 30 in PLL1 shown in FIG. 18,
Unnecessary waves input to the even harmonic mixer 30 are suppressed.
Therefore, the PLL 1 has an effect that the level of the unnecessary wave can be suppressed. In the above description, the even harmonic mixer 3
Although the filter 54 is provided at both the RF input terminal and the LO input terminal of 0, depending on the unnecessary wave level of the input wave, either one of them may have the same effect.

Embodiment 9 Generally, when using a mixer, especially a diode mixer, as a detector,
As phase detector (Mixers asp
Hase detector), published in 1978 by WJ, Tech Note Vol. 5, Number 1 (Tech-n
ote vol. 5, no. 1)), the terminal voltage Vo is output to the baseband circuit.

This is because the diode mixer having the configuration shown in FIG. 24 is designed on the assumption that each terminal has 50 ohms. However, since a baseband circuit using an operational amplifier usually assumes a voltage transmission system instead of power transmission, it has no meaning other than matching to a 50-ohm termination resistor Zo. In addition, the even harmonic mixer 30 has a conversion loss of 1 due to the use of the second order as compared with a normal mixer.
It is about 3 dB higher than dB. Therefore, in the even harmonic mixer 30 of the PLL according to the present embodiment, the terminating resistance Zo is set to 50
The impedance is set to be higher than ohm, and the detection voltage Vo is intended to be improved.

FIG. 19 shows a PL according to the configuration of this embodiment.
3 shows a circuit of L1 . In the figure, 55 is a termination resistor Zo, and 56 is a buffer amplifier. FIG. 20 shows the detection voltage Vo with respect to the terminating resistor Zo. In the case of the even harmonic mixer 30, when the voltage is experimentally increased to about 200 ohms, the voltage is approximately doubled, and the operation has the same effect as the case where the conversion efficiency is improved. Accordingly, since the detection sensitivity Kp can be increased, there is an effect that the PLL 1 can be stabilized.

Embodiment 10 FIG. This embodiment is a communication device using the PLL 1 shown in the first to ninth embodiments. A transmission signal of a wireless or wired line, for example, a pilot signal transmitted from a satellite is input to the PLL 1 shown in the first to ninth embodiments as a reference signal. Then, the line noise included in the pilot signal is suppressed by the PLL 1, and a reference clock with low noise level can be output. Therefore,
Since the PLL 1 described in the first to ninth embodiments is applied, the phase synchronization can be stabilized, and the size and the price can be reduced, as in these embodiments.

[0048]

As described above, according to the first aspect of the present invention, an even harmonic mixer incorporating an anti-parallel diode pair in which two diodes of opposite polarities are connected in parallel is used as the phase comparator. With this configuration, the use of an even harmonic mixer capable of outputting a mixed wave of a doubled wave of a local oscillation wave and a signal wave eliminates the need for one doubler, thereby reducing the size and cost. effective. In addition, since only odd-order mixed waves are generated in principle, the level of the DC offset, which is the zero-order component, is extremely low, and there is an effect that fluctuations in the transfer characteristics of the phase locked loop can be avoided.

According to the second aspect of the present invention, an even harmonic mixer incorporating a ring diode and a balanced / unbalanced conversion circuit is used as the phase comparator.
There is an effect that the even harmonic mixer can be miniaturized and widened.

According to the third aspect of the present invention, an external reference oscillation wave is used as a high frequency signal of the even harmonic mixer, and an output wave from the voltage controlled oscillator is used as a local oscillation wave of the even harmonic mixer. With such a configuration, there is an effect that the entire phase-locked oscillator can operate as a frequency divider.

According to the fourth aspect of the present invention, the output wave from the voltage controlled oscillator is used as the high frequency signal of the even harmonic mixer, and the external reference oscillation wave is used as the local oscillation wave of the even harmonic mixer. With such a configuration, there is an effect that the entire phase-locked oscillator can operate as a multiplier.

According to the fifth aspect of the present invention, since the frequency divider is connected between the voltage controlled oscillator and the even harmonic mixer, there is an effect that the entire phase locked oscillator operates as a multiplier. .

According to the sixth aspect of the present invention, since the multiplier is connected between the voltage controlled oscillator and the even harmonic mixer, there is an effect that the entire phase locked oscillator operates as a frequency divider. .

According to the seventh aspect of the present invention, a limiter is connected between at least one of the voltage controlled oscillator and the even harmonic mixer and / or the input side of the reference oscillation wave of the even harmonic mixer. Thus, there is an effect of suppressing a change in the transfer characteristic of the phase locked oscillator due to a change in the level of the input wave of the even harmonic mixer.

According to the eighth aspect of the present invention, a filter is connected between at least one of the voltage controlled oscillator and the even harmonic mixer and / or the input side of the reference oscillation wave of the even harmonic mixer. , There is an effect of suppressing generation of unnecessary waves in the even harmonic mixer.

According to the ninth aspect of the present invention, since a terminating resistor exceeding 50 ohms is connected to the output side of the even harmonic mixer, the detection sensitivity is increased, and the stability of the phase synchronization is increased. It has the effect of suppressing noise.

According to the tenth aspect, the first aspect is provided.
To the phase comparator of the phase-locked oscillator according to any one of claims 9 to 10, wherein a transmission signal of a wireless or wired line is inputted as a reference oscillation wave, so that the device can be downsized. This has the effect of suppressing fluctuations in noise characteristics due to fluctuations in temperature and the like.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a phase locked oscillator according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing an even harmonic mixer used in the phase locked oscillator according to the first embodiment of the present invention.

FIG. 3 is a characteristic diagram of current and conductance of an anti-parallel diode pair.

FIG. 4 is a characteristic diagram showing a frequency relationship of a phase locked oscillator.

FIG. 5 is a configuration diagram specifically showing an even harmonic mixer used in the phase locked oscillator according to the first embodiment of the present invention;

FIG. 6 is a configuration diagram specifically showing an even harmonic mixer used in the phase locked oscillator according to the first embodiment of the present invention;

FIG. 7 is a configuration diagram showing an even harmonic mixer used in a phase locked oscillator according to a second embodiment of the present invention.

FIG. 8 is a configuration diagram showing an even harmonic mixer used in a phase locked oscillator according to a second embodiment of the present invention.

FIG. 9 is a configuration diagram showing a phase locked oscillator according to a third embodiment of the present invention.

FIG. 10 is a configuration diagram showing a phase locked oscillator according to a fourth embodiment of the present invention.

FIG. 11 is a configuration diagram showing a phase locked oscillator according to a fifth embodiment of the present invention.

FIG. 12 is a configuration diagram showing a phase locked oscillator according to a sixth embodiment of the present invention.

FIG. 13 is an explanatory diagram of conversion loss of the even harmonic mixer with respect to local oscillation power.

FIG. 14 is a configuration diagram showing a phase locked oscillator according to a seventh embodiment of the present invention.

FIG. 15 is a characteristic diagram of a limiter.

FIG. 16 is a characteristic diagram of an even harmonic mixer with a limiter.

FIG. 17 is a characteristic diagram of a spectrum of a limiter output.

FIG. 18 is a configuration diagram showing a phase locked oscillator according to an eighth embodiment of the present invention.

FIG. 19 is a configuration diagram of an output circuit of an even harmonic mixer of a phase locked oscillator according to a ninth embodiment of the present invention.

FIG. 20 is a characteristic diagram of a detection voltage with respect to a terminating resistor.

FIG. 21 is a configuration diagram showing a conventional phase locked oscillator.

FIG. 22 is a characteristic diagram of transfer characteristics of a conventional phase locked oscillator.

FIG. 23 is a characteristic diagram of an output spectrum of a conventional phase locked oscillator.

FIG. 24 is a configuration diagram showing a phase comparator used in a conventional phase locked oscillator.

FIG. 25 is a characteristic diagram of a static characteristic of the diode.

FIG. 26 is an explanatory diagram for explaining an influence of a DC offset.

FIG. 27 is a characteristic diagram illustrating the effect of temperature on transfer characteristics of a phase-locked oscillator.

FIG. 28 is a characteristic diagram illustrating the effect of temperature on transfer characteristics of a phase-locked oscillator.

FIG. 29 is a configuration diagram showing a conventional phase locked oscillator.

[Explanation of symbols]

1 phase locked oscillator, 5 voltage controlled oscillator, 30 even harmonic mixer, 32 anti-parallel diode pair, 3
2a, 32b Diode, 40 Balun for balanced / unbalanced conversion (balanced / unbalanced conversion circuit), 41 Ring diode, 44 Antiparallel ring diode (ring diode), 50 divider, 51 multiplier, 52a,
52b Limiter, 54 Filter, 55 Terminator.

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Mitsuhiro Shimozawa 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Inside Mitsubishi Electric Corporation (72) Inventor Shigeo Yamanaka 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric (56) References JP-A-57-185707 (JP, A) JP-A-59-91731 (JP, A) JP-A-51-60408 (JP, A) JP-A-49-70664 (JP, A) A) Hikaru 2-141110 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03L ^7/ 00-7/18 H03D ^7/ 00-7/02

Claims (10)

(57) [Claims] 1. A phase comparator for externally inputting a reference oscillation wave, and a voltage controlled oscillator for outputting an output wave, wherein a phase difference between the reference oscillation wave and a feedback signal wave from the voltage controlled oscillator is provided. The error signal output from the phase comparator,
In the phase-locked oscillator that outputs an output wave synchronized with the reference oscillation wave from the voltage-controlled oscillator based on the error signal, the phase comparator includes an anti-parallel diode pair in which two diodes of opposite polarities are connected in parallel. A phase-locked oscillator using a mixed even harmonic mixer. 2. A phase comparator for externally inputting a reference oscillation wave, and a voltage-controlled oscillator for outputting an output wave, wherein a phase difference between the reference oscillation wave and a feedback signal wave from the voltage-controlled oscillator is provided. The error signal output from the phase comparator,
In the phase-locked oscillator that outputs an output wave synchronized with the reference oscillation wave from the voltage-controlled oscillator based on the error signal, the phase comparator includes a ring diode and a balanced diode.
A phase-locked oscillator using an even harmonic mixer incorporating an unbalanced conversion circuit. 3. The method according to claim 1, wherein an external reference oscillation wave is used as a high-frequency signal of the even harmonic mixer, and an output wave from a voltage controlled oscillator is used as a local oscillation wave of the even harmonic mixer. The phase-locked oscillator according to claim 1 or claim 2. 4. The method according to claim 1, wherein an output wave from a voltage controlled oscillator is used as a high frequency signal of the even harmonic mixer, and an external reference oscillation wave is used as a local oscillation wave of the even harmonic mixer. The phase-locked oscillator according to claim 1 or claim 2. 5. The phase locked oscillator according to claim 1, wherein a frequency divider is connected between the voltage controlled oscillator and the even harmonic mixer. 6. The phase locked oscillator according to claim 1, wherein a multiplier is connected between the voltage controlled oscillator and the even harmonic mixer. 7. A limiter is connected between at least one of a voltage controlled oscillator and an even harmonic mixer and at least one of an input side of a reference oscillation wave of the even harmonic mixer. The phase-locked oscillator according to claim 6. 8. A filter is connected between at least one of the voltage controlled oscillator and the even harmonic mixer and at least one of the input side of the reference oscillation wave of the even harmonic mixer. Any one of claims 7
The phase-locked oscillator described in the paragraph. 9. The phase-locked oscillator according to claim 1, wherein a terminal resistance exceeding 50 ohms is connected to the output side of the even harmonic mixer. 10. A communication characterized in that a transmission signal of a wireless or wired line is input as a reference oscillation wave to the phase comparator of the phase-locked oscillator according to any one of claims 1 to 9. apparatus.