JP3221127B2 - Analog / digital conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog / digital conversion circuit for converting an analog signal into a digital signal, and more particularly, to an analog / digital conversion circuit for converting an analog signal into a digital signal in upper and lower order simultaneously. is there.

[0002]

2. Description of the Related Art Various conversion methods have been proposed for an analog / digital (hereinafter abbreviated as A / D) conversion circuit for converting an analog signal into a digital signal. A parallel (flash type) A / D conversion circuit that quantizes the amplitude so as to be equal to the number of conversion bits and converts the quantized signal into a digital code is often used.

Such a parallel type A / D conversion circuit can operate at high speed in principle. However, when the number of conversion bits is n, at least (2 ⁿ -1) comparators are required. 255 to get the 8 bit conversion code
Therefore, in order to obtain a high-resolution digital code, it is necessary to form tens of thousands of active elements by using an IC. Therefore, although the parallel A / D conversion circuit has an advantage that high-speed processing can be performed, there is a problem that power consumption and a chip area increase.

Therefore, when converting an analog signal into an n-bit digital signal, first, the analog signal is digitized by coarse quantization to obtain a high-order a-bit conversion code including the most significant digit (MSB). In order to reduce the error of the upper conversion code, that is, the quantization noise, the upper quantization range is further subdivided and quantified, and the lower b (na) bit conversion code including the least significant digit (LSB) is included. , A so-called serial-parallel A / D conversion circuit has been proposed.

FIG. 7 is a block diagram showing an outline of the serial / parallel A / D converter, and shows a circuit configuration for converting an analog signal into a 4-bit digital code. In FIG. 7, R ₁ ~R ₁₆ is the reference voltage _{V RT ~V RB (0~-2V} ) reference resistance element connected in series between the terminals of, C _u1 -C _u3 is to be translated one input terminal It is connected to the input line of the analog signal V _IN , and the other input terminal is connected to the reference resistance elements R ₁ to R ₁ .
The divided rough quantization level of the reference voltage at the R ₁₆ (V _4,
V _8, V ₁₂₎ connected to the upper comparator input line, B _u1 .about.B _u3 obtain complementary outputs of the upper comparator C _u1 -C _u3 buffer, A _u1 to A _u4 AND gate,
S _{b1 to} S _b12 are switching blocks arranged in a matrix of 4 rows and 3 columns, and C _{d1 to} C _d3 have one input terminal connected to the input line of the analog signal V _IN and the other input terminal connected to the switching block S. _b1 to S connected low-order comparator to the output terminal of _b12, E _u1 the upper comparator C
The differential result of the binary signal output from _u1 to _Cu3 is encoded and, for example, a 2-bit binary code (or 2
E _d1 indicates a lower-order encoder that converts the differential result of the binary signal output from the lower-order comparators C _{d1 to} C _d3 into a 2-bit binary code.

[0006] The switching block S _b1 ~S _b12, the output level "1" of the AND gate A _u1 ~A _u4 and "0"
On / off control is performed on a line basis in accordance with. In particular,
When "1" level signal from the AND gate A _u1 is output is controlled so that the switching block S _b1 to S _b3 is turned on, when the "1" level signal from the AND gate A _u2 is output Is the switching block S
_b4 to S _b6 are controlled to be turned on, when the "1" level signal from the AND gate A _u3 is output is controlled so that the switching block S _b7 to S _b9 is turned on, the AND gate when "1" level signal is output from the a _u4 is controlled so that the switching block S _b10 to S _b12 is turned on.

In a serial-parallel A / D conversion circuit having such a configuration, for example, as shown in FIG. 8, an analog signal V _IN is sampled at a rising point of a sampling pulse P _S , and the sampling voltage V _S is obtained. It is supplied to the upper encoder E _u1 and lower encoders E _d1.
In upper encoder E _u1, the sampling voltage V _S is supplied, fall time T of the clock signal CLK
_H (point delayed by τ _A ), the upper comparators _{Cu 1} to _Cu 3
The value signal output is the code signals D ₀ and D _{1 of the} upper 2 bits
Is converted and output. In the lower encoder _Ed1 , when the sampling voltage V _S is supplied, the clock signal CL
At the falling point T _{L of} K (point delayed by τ _B ), the binary signal outputs of the lower comparators C _{d1 to} C _d3 are converted into lower 2 bit code signals D ₂ and D ₃ and output.

More specifically, the reference resistance element R
₁ divided by rough quantization level of the reference voltage V ₄ in to R _16, V ₈ and V ₁₂ and the input analog signal V _IN is compared by the upper comparator C _u1 -C _u3. As a result of this comparison, if, for example, V ₄ <V _IN <V ₈ , the output of the upper comparator _{Cu 3} goes to the high level of the high potential (“1”), and the outputs of the upper comparators _{Cu 2} and _{Cu 3 go to} the low potential ( ("0")). Thus, the AND gate A _u1 to A output level _u4 is "1" only the output of the AND gate A _u2 is next, other AND gates A _u1, A _u3,
The output of _Au4 is "0". As a result, [01] is output from the upper encoder _Eu1 as a conversion code of the upper 2 bits.

Next, "1" output from the AND gate _Au2 in a state where the upper two bits of the conversion code are latched.
The level signal is input to the switching blocks S _{b4 to} S _b6 . Thereby, the switching blocks S _{b4 to} S _b6
Is turned on. With the switching blocks S _{b4 to} S _b6 being turned on, the sampled analog signal V _IN at the level of V ₄ <V _IN <V ₈ is further added to the resistance element R ₁ The reference voltages V ₅ , V ₆ , and V ₇ divided by R _{16 to} R ₁₆ respectively correspond to the switching blocks S
_The lower comparators C _d3 , C _d2 , _{b d} , S _b5 , S _b6
It is input to the other input terminal of C _d1 .

Lower comparator C_d3, C_d2, C_d1Then
Input reference voltage V_Five, V₆, V₇And one input terminal
Input analog signal V_INIs compared with
Position encoder E_d1Is output to As a result of this comparison,
For example, V₆<V_IN<V₇, The lower encoder E
_d1Outputs a conversion code [10] of lower 2 bits from
You.

As a result, the upper and lower encoders E
A 4-bit conversion code [0110] of the analog signal V _IN is output from _u1 and _Eu2 .

[0012]

The serial / parallel A / D conversion circuit is required when performing 4-bit A / D conversion because the conversion code is divided into upper and lower 2 bits and output. The number of comparators can be reduced to six. Also, when performing 8-bit A / D conversion, for example, as described above, a parallel A / D conversion circuit requires 255 comparators, but in the case of this serial-parallel A / D conversion circuit, Has an advantage that (2 ⁴ -1) × 2 = 30 pieces can be obtained by making the upper and lower bits each 4 bits.

However, since the code conversion is performed in two stages, it is necessary to provide a sample-and-hold circuit so that the input signal voltage does not change and is maintained at a predetermined value during that time, which leads to complicated circuit control. There is a problem that it leads to conversion.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and its object is to not only prevent the increase in power consumption and chip area, but also to eliminate the need to provide a sample and hold circuit, and to make circuit control complicated. An object of the present invention is to provide an A / D conversion circuit capable of preventing the above.

[0015]

In order to achieve the above object, according to the present invention, a series connection is made between two reference potentials.
Fold the reference voltage in the opposite direction for each constant element.
N reference resistance elements repeatedly arranged in a plurality of rows;
Are arranged in a matrix to compare the respective reference voltage and the converter input signal by dividing by n reference resistance element in which Kijika column connection, a plurality of switching blocks which are driven simultaneously in parallel, the switching block A high-order comparator for comparing a coarse quantization level reference voltage applied to a specific position in the row direction with the input signal to be converted to obtain a high-order bit conversion code, and for each column in the column direction of the switching block, A discrimination circuit for discriminating whether the number of switching blocks that have obtained the comparison result that the input signal level to be converted is higher than the reference voltage level is an even number or an odd number, and a conversion code of lower bits according to the discrimination result of the discrimination circuit. The lower encoder to be obtained and the voltage application direction of a predetermined row
Obtained based on the reference voltage by the reference resistance element
The lower conversion code by the lower encoder is
And an inverting gate that outputs as it is or inverted .

In the present invention, the upper encoder obtains a plurality of conversion codes related to upper bits, and the inverting gate performs conversion related to upper bits excluding the most significant bit from the conversion codes of upper bits by the upper encoder. Based on the code, the lower conversion code by the lower encoder is output as an input code or inverted. Preferably, the inverting gate calculates and outputs an exclusive OR of a conversion code relating to an upper bit excluding the most significant bit of a conversion code of an upper bit by the upper encoder and a lower conversion code by the lower encoder. I do.

In the present invention, the inversion gate is provided by the lower encoder obtained based on a reference voltage by a reference resistance element in a row in an application direction opposite to the predetermined direction when a voltage application direction in a predetermined row is used as a reference. The lower conversion code is inverted and output.

According to the present invention, each of the switching blocks has a differential amplifier having a pair of transistors to each of which a base is supplied with an input signal to be converted and a divided reference voltage. For each column, a transistor output to which an input signal is supplied and a transistor output to which a reference voltage is supplied are alternately connected and connected to a load element.

According to the present invention, the discriminating circuit includes means for obtaining an exclusive OR of adjacent switching blocks for each column, and outputting the total to the lower encoder.

In the present invention, the discriminating circuit has a plurality of exclusive OR gates for obtaining exclusive OR of outputs of adjacent switching blocks, and the outputs of the respective exclusive OR gates are connected.

[0021]

According to the present invention, when an analog signal is input, the input signal is compared with the reference voltage applied to a specific position in the row direction of the switching block in the upper comparator, and the comparison result is determined according to the comparison result. The upper bit conversion code is obtained. In parallel with the conversion of the upper bits,
The input analog signal is input to each switching block arranged in a matrix. Each switching block is supplied with each reference voltage obtained by dividing a reference potential by n resistance elements connected in series, and compares the magnitude with an input signal. From each switching block, for example, when a comparison result that the input signal level is higher than the reference voltage level is obtained, a high-level signal is output.
In the case of the opposite result, a low level signal is output to the discriminating circuit provided for each column. The determination circuit determines whether the number of switching blocks that output a high-level signal in each column is an even number, and the determination result of each determination circuit is output to the lower encoder. In the lower encoder, a conversion code of lower bits according to the determination result of the determination circuit is obtained.

According to the present invention, each switching block is controlled, for example, to always operate, and the comparison operation between the input signal and the reference voltage is simultaneously performed in all the switching blocks.

According to the present invention, since the outputs of the transistors of the differential pair differ according to the level of the supply level of the input signal and the reference voltage, the load is different depending on whether the input signal level is higher than the reference voltage level or reverse. A difference occurs in the output current value generated through the element, and this current is output to the lower encoder. In the lower encoder, a conversion code of lower bits is obtained according to the output current value of the discrimination circuit.

According to the present invention, for example, when the matrix is 4
In the case of a row configuration, the output of the switching block in the first row and the output of the switching block in the second row of each column are exclusive-ORed, and the output of the switching block in the third row is calculated. The exclusive OR of the output and the output of the switching block in the fourth row is calculated, and the sum of these is calculated and output to the lower encoder.

According to the present invention, for example, when the matrix is 4
In the case of a row configuration, the exclusive OR of the output of the switching block in the first row and the output of the switching block in the second row of each column is calculated by one exclusive OR gate, The output of the switching block in the third row and the fourth
The exclusive OR with the output of the switching block in the row is taken by another exclusive OR gate, and the outputs of these gates are so-called wired-OR and output to the lower encoder.

According to the present invention, the lower conversion code obtained based on the reference voltage by the reference resistance element in the row in the direction opposite to the row to which the reference voltage is applied is inverted by the inversion gate. Is output.

[0027]

FIG. 1 is a block diagram showing a first embodiment of an A / D conversion circuit according to the present invention. The same components as those in FIG. 7 showing a conventional example are denoted by the same reference numerals. That is, R ₁
R ₁₆ to the reference resistance element, C _{U1 to} C _U3 are the upper comparators, A _{U1 to} A _U3 are the upper AND gates, E _U1 is the upper encoder, S _{B1 to} S _B12 are the switching blocks, EOD
_{1 ~EOD 3} the even / odd determination circuit, B _D1 .about.B _D3 is complementary output buffer, A _D1 to A _D3 is lower AND gate, E _D1
Denotes a lower encoder, RV ₁ denotes an inverting gate, V _IN denotes an input analog signal, and V _RT and V _RB denote reference voltages set with a predetermined difference.

The reference resistance elements R _{1 to} R ₁₆ are connected to a reference voltage V _RT
To V _RB (0 to −2 V) in series, and generates reference voltages V _{1 to} V ₁₅ by dividing the reference voltage between adjacent resistance elements.

Upper comparator C_U1Is one input terminal
Is the analog signal V to be converted_INConnected to the input line
And the other input terminal is a reference resistance element R₁~ R₁₆With partial pressure
Reference voltage V at the coarse quantization level_FourThe resistance element that generates
Child R_FourAnd R_FiveIs connected to the midpoint of connection with
2-input AND gate A_U1Connected to one of the input terminals
I have. This upper comparator C_U1Is the analog input
Signal V_INAnd reference voltage V_FourAnd show the result of the comparison.
The analog signal V_INIs the reference voltage V_FourYo
High level ("1") if the analog signal V_IN
Is the reference voltage V _FourLow level if below
("0") and AND gate A from positive output terminal_U1Output to
I do.

The upper comparator C _U2 has one input terminal connected to the input line of the analog signal V _IN to be converted and the other input terminal having a coarse quantization level divided by the reference resistance elements R _{1 to} R _16. Is connected to the connection point between the resistance elements R ₈ and R ₉ where the reference voltage V ₈ is generated, and the positive output terminal is connected to one input terminal of a two-input AND gate A _U2 ,
The negative output terminal is connected to the other input terminal of the two-input AND gate A _U1 . The upper comparator _CU2 compares the input analog signal V _IN with the reference voltage V _8, and outputs a signal indicating the comparison result at a high level if the level of the analog signal V _IN is higher than the reference voltage V _8. If the level of the signal V _IN is equal to or lower than the reference voltage V _{8, a} low level signal is output from the positive output terminal to the AND gate A _U2 , and a signal obtained by inverting the level of the positive output from the negative output terminal is output to the AND gate A _U1. Output to the other input terminal.

The upper comparator _CU3 has one input terminal connected to the input line of the analog signal V _IN to be converted, and the other input terminal having a coarse quantization level divided by the reference resistance elements R _{1 to} R _16. reference voltage V ₁₂ is connected to the connection point between the resistor element R ₁₂ and R ₁₃ that occur in the positive side output terminal connected to both the input terminals of 2-input aND gates a _U3,
The negative output terminal is connected to the other input terminal of the two-input AND gate A _U2 . The upper comparator _CU3 compares the input analog signal V _IN with the reference voltage V _12, and outputs a signal indicating the comparison result at a high level when the level of the analog signal V _IN is higher than the reference voltage V _12. If the level of the signal V _IN is equal to or lower than the reference voltage V _{12, a} low level is output from the positive output terminal to the AND gate A _U3 , and a signal obtained by inverting the level of the positive output from the negative output terminal is output to the AND gate A _U2. Output to the other input terminal.

AND gate A_U1Is the upper comparator C
_U1Positive side output and upper comparator C _U2With the negative output of
The logical product is taken and the result is written to the upper encoder E_U1Output to
You. AND gate A_U2Is the upper comparator C_U2Positive side of
Output and upper comparator C _U3AND with the negative output of
And the result is referred to_U1Output to and
Gate A_U3Is the upper comparator C_U32 positive outputs of
The logical product is taken as the force and the result is_U1
Output to

The upper encoder _EU1 is connected to each AND gate A
The output signal of _U1 to A _U3 encoded in accordance with these output levels is converted into 2-bit binary code, and outputs as the conversion code D _0, D ₁ of the upper 2 bits. Specifically, when the output levels of the AND gates A _{U1 to} A _U3 are all “0”, the conversion codes D ₀ and D ₁ are [0, 0].
And output when the output level of the AND gate A _U1 is "1". When the output level of the AND gate A _U2 is "1", the output is set to [0, 1]. 1,0]
And when the output level of the AND gate A _U3 is “1”, the output is set to [1, 1].

Switching block S_B1~ S_B12Is 4
They are arranged in a matrix with three rows and three columns.
Each of which is constituted by a differential amplifier and has a reference resistance element R₁
~ R ₁₆Reference voltage V divided by₁~ V_Fifteen(However, V_Four,
V₈, V₁₂Excluding the reference voltage and the input analog
Signal V_INAnd compare the input analog to the reference voltage.
Signal V_INSpecifically, depending on the magnitude of (V_IN> Reference
Pressure V), "1" (level V_IN≤ Reference voltage V)
If the signal S at the "0" level₁~ S₁₂The rows are arranged according to
Corresponding even / odd discrimination circuit EOD₁~ EOD_ThreeTo
Output.

More specifically, the switching blocks S _B1 , S _B6 , and S _B arranged in the first column (left side in the figure)
_B7, S _B12 is a reference voltage, respectively _{V 1, V 7, V 9} , V
₁₅ and the analog signal V _IN, and the result is referred to as signals S ₁ , S ₆ , S ₇ , and S ₁₂ as an even / odd discrimination circuit E.
And outputs it to the OD _1. Arranged in the second column the switching block _{S B2, S B5, S B8} , S B11 , respectively compares the reference voltage _{V 2, V 6, V 10} , V 14 and the analog signal V _IN, signal the result _{S 2, S 5, S 8} , and outputs it as S ₁₁ in the even / odd determination circuit EOD _2. Switching blocks S _B3 , S _B4 , S _B9 , S arranged in the third column
_B10 compares the reference voltages V ₃ , V ₅ , V ₁₁ , V ₁₃ with the analog signal V _IN , respectively, and compares the result with the signals S ₃ ,
Even / odd discrimination circuit EOD ₃ as S ₄ , S ₉ and S ₁₀
Output to

An even / odd discrimination circuit EOD₁Is the switch
Block S_B1, S_B6, S_B7, S _B12Output from
The signal S input at the time₁, S₆, S₇, S₁₂Input level
To determine whether there is an even number of "1"
If it is determined that there is, it is at the “0” level and not an even number.
In other words, if it is determined to be an odd number,
Signal S_EO1To buffer B_D1Output to Even and odd
Discrimination circuit EOD_TwoIs the switching block S_B2,
S_B5, S_B8, S _B11Signal that is output from the
S_Two, S_Five, S₈, S₁₁Input level of "1"
When it is determined whether there is an even number and it is determined that the number is even
Is "0" level and if it is determined to be odd
Signal S at "1" level_EO2To buffer B_U2Output to
Even / odd discrimination circuit EOD_ThreeIs a switching block
S_B3, S_B4, S_B9, S _B10Output from the
Signal S_Three, S_Four, S₉, S_TenInput level is “1”
Determines whether there is an even number and determines that it is even.
If it is determined to be an odd number at "0" level
At the "1" level_EO3To buffer B_D3Output to
You.

FIG. 2 shows a switching block for each column.
FIG. 3 is a diagram showing an example of a circuit configuration of an even / odd discrimination circuit.
FIG. 2A shows the switching block S in the first row._B1, S
_B6, S_B7, S_B12And even / odd discrimination circuit EOD₁of
Figure 2 (b) shows a circuit configuration example.
Ku S_B2, S_B5, S_B8, S_B11And even / odd number discrimination circuit
EOD_TwoFigure 3 (c) shows a third row of switches.
Block S_B3, S _B4, S_B9, S_B10And even / odd
Number discrimination circuit EOD_ThreeCircuit configuration examples
You. These circuits differ only in the input reference voltage.
Since the basic configuration and operation are the same for each column,
The configuration of the example shown in FIG.

In FIG. 2A, V _CC is the power supply voltage, LR
₁ and LR ₂ are load resistance elements having a resistance value R, and Q _{1 to} Q ₈ are n
pn-type transistors, I _{C1 to} I _C4, represent constant current sources for supplying the current I, respectively. Constant current to the emitter of the emitter and the transistor Q ₂ of the transistor Q ₁ source I _C1
Are connected to form a switching block S _B1 composed of a differential amplifier. A constant current source I _C2 is connected to the emitter of the transistor Q _{3 and} the emitter of the transistor Q ₄ to form a switching block S _B6 composed of a differential amplifier. , of the transistor Q ₅ emitter and the transistor Q
Switching block S _B7 constant current source I _C3 to the emitter of ₆ consists a connected differential amplifier is configured, is connected to a constant current source I _C4 to the emitter of the emitter and the transistor Q ₈ of the transistor Q ₇ differential amplifier It is configured switching block S _B12 consisting of. Then, the analog signal V _IN is input to each base of the transistors Q ₁ , Q ₃ , Q ₅ and Q ₇ , the reference voltage V ₁ is applied to the base of the transistor Q ₂ , the reference voltage V ₇ is applied to the base of the transistor Q ₄ , Reference voltage V ₉ is applied to the base of transistor Q ₆ ,
Reference voltage V ₁₅ to the base of the transistor Q ₈ is configured to be inputted, respectively.

The even / odd discriminating circuit EOD ₁ is constituted by a combination of connections to the load resistance element LR ₁ and LR ₂ of the collectors of each transistor Q ₁ to Q _8. That is, the transistors Q ₁ , Q ₄ , Q ₅ and Q
Supply voltage V collector ₈ via the load resistance element LR ₂
Connected to _CC , and transistors Q ₂ , Q ₃ , Q ₆ and Q
Supply voltage V collector ₇ via a load resistor element LR ₁
Is connected to the _CC, the output terminal of the signal S _EO1 is configured by the connection point between the collector of the transistor Q ₇ and the load resistance element LR _1.

A basic operation example of the configuration shown in FIG.
Then, for example, V_IN<V₁In the case of
Lock S_B1, S_B6, S_B7, S_B12Input
Analog signal V_INMore reference voltage V₁, V₇, V₉, V_Fifteenof
Transistor Q_Two, Q_Four, Q₆and
Q₈Turns on. As a result, the load resistance element LR₁And
And LR_Two, A current of 2I flows. Accordingly
And the output signal S_EO1Level is (V_CC-2IR)
Become. Also, V₁<V_IN<V₇In the case of Transis
TA Q₁, Q_Four, Q₆And Q ₈Turns on. The result
As a result, the load resistance element LR₁Has a load resistance element LR_TwoTo
Flows a current of 3I. Therefore, the output signal S_EO1
Level is (V_CC−IR). That is, (A
Analog signal V_IN> Reference voltage V) differential pair (switching)
Block) is an even number, the output signal S_EO1The level of
Low level (V_CC-2I · R).
Level (V_CC-IR).

The complementary output buffer B _D1 has an input terminal connected to an output terminal of the even / odd determination circuit EOD _1, positive output terminal is connected to one input terminal of the AND gate A _D1. This buffer _BD1 is provided with an even / odd discrimination circuit EO.
Performing a predetermined level adjustment for the output signal S _EO1 of D ₁ output from the positive-side output terminal to one input terminal of the AND gate A _D1.

The complementary output buffer B _D2 has an input terminal connected to an output terminal of the even / odd determination circuit EOD _2, the positive side output terminal is connected to one input terminal of the AND gate A _D2, the negative-side output terminal It is connected to the other input terminal of AND gate A _D1 . The buffer B _D2 is output from the positive output terminal to one input terminal of the AND gate A _D2 by performing a predetermined level adjustment for even / odd determination circuit EOD ₂ output signal S _EO2, from the negative side output terminal The input level is inverted and output to the other input terminal of the AND gate _AD1 .

The complementary output buffer B _D3 has an input terminal connected to an output terminal of the even / odd determination circuit EOD _3, the positive side output terminal connected to the input terminals of both of the AND gates A _D3, the negative-side output terminal It is connected to the other input terminal of AND gate _AD2 . The buffer B _D3 is output from the positive output terminal to both the input terminals of the AND gates A _D3 performs predetermined level adjustment for the output signal S _EO3 even / odd determination circuit EOD _3, is from the negative-side output terminal The input level is inverted and output to the other input terminal of AND gate _AD2 .

The AND gate A _D1 takes the logical AND of the negative output of the positive output and the buffer B _D2 of the buffer B _D1, and outputs the result to a lower encoder E _D1. AND gate A
_D2 takes the logical AND of the negative output of the positive output and the buffer B _D3 of the buffer B _D2, and outputs the result to a lower encoder E _D1. The AND gate A _D3 takes the logical product of the positive output of the buffer B _D3 as two inputs and outputs the result to the lower encoder E _D1 .

Lower encoder E_D1Is each AND gate A
_D1~ A_D3Output signals according to these output levels.
Code, convert it to a 2-bit binary code,
2-bit conversion code D_Two, D_ThreeOutput code B before
D_Two, BD_ThreeAs inversion gate RV₁Output to Concrete
Specifically, AND gate A_D1~ A_D3Output level is all
If "0", the previous output code BD_Two, BD_ThreeIs
Set to [0,0] and output, AND gate A_D1Output
If the level is "1", set it to [0, 1] and output
And And Gate A _D2When the output level of is "1"
Set to [1,0] and output, AND gate A_D3Output
If the level is "1", set it to [1,1] and output
You.

The inverting gate RV ₁ is composed of, for example, exclusive OR gates EXO ₁ and EXO ₂ arranged in parallel, and outputs the previous output codes BD ₂ and BD ₃ output from the lower encoder E _D1 and the upper encoder E _D1. And exclusive-OR with the output conversion code D _1, and outputs as lower-order 2 bits conversion codes D ₂ and D ₃ . Specifically, an exclusive OR operation with the previous output code BD ₂ and the upper conversion code D ₁ in the exclusive OR gates EXO _1, and outputs the result as the lower order bit conversion code D _2, XOR gates E
Before output code BD ₃ in XO ₂ and the upper conversion code D
Exclusive-ORs the _1, and outputs the result as the lower order bit conversion code D _3.

Next, the operation according to the above configuration will be described in terms of higher-order conversion and
And lower-order conversion, and refer to FIG. 3 and FIG.
Will be described later. FIG. 3 shows the input voltage at the time of higher-order conversion.
(Analog signal) level reference voltage V_Four~ V₁₂Against
Upper comparator C according to size_U1~ C_U3Output level
Le, And Gate A_U1~ A_U3Output level and conversion
Code D₀, D₁Of the output levels of FIG.
FIG. 4 shows the input voltage (analog signal) level at the time of lower-order conversion.
Bell reference voltage V₁~ V_FourSui according to the size of
Pitching block S_B1~ S_B12Output signal S₁~ S₁₂of
Level, even / odd determination circuit EOD₁~ EOD_ThreeOutput
Signal S_EO1~ S _EO3Level, AND gate A_D1~ A_D3
Output level and conversion code D_Two, D _ThreeOutput level
Are shown.

First, the upper-level conversion operation will be described with reference to FIG. A reference resistance element R ₁ to R ₁₆ in the reference voltage divided by rough quantization level V _4, V ₈ and V ₁₂ and the input analog signal V _IN is compared respectively by the upper comparator C _U1 -C _U3. As a result of this comparison, for example, V _IN <
If V _4, as shown in FIG. 3, the upper comparator C
_U1, C _U1, the output of C _U2 is all to the "0" level. As a result, the output levels of the AND gates A _{U1 to} A _U3 all become “0”. As a result, as the upper two bits of conversion codes D _O and D ₁ from the upper encoder _{EU 1}

[00] is output.

As a result of the comparison, if, for example, V ₄ <V _IN <V ₈ , the output of the upper comparator _CU1 becomes “1” level, and the outputs of the upper comparators _CU2 and _CU3 become “0” level. Thus, the output level of the AND gate A _U1 to A _U3, the output of only the output of the AND gate A _u1 is "1", the other AND gates A _U2, A _U3 is "0". As a result, conversion code D _O of the upper 2 bits from the upper encoder E _U1, as D ₁ is [01] it is output.

[0050] Comparison of the results, if for example _{V 8 <V IN <V 12} , the output of the upper comparator C _U1 and C _U2 becomes "1" level, the output of the upper comparator C _U3 becomes "0" level. Thereby, the AND gates A _U1 to
As for the output level of A _U3 , only the output of the AND gate A _U2 is “1”, and the outputs of the other AND gates A _U1 and A _U3 are “0”. As a result, [10] is output from the upper encoder _{EU1 as the} upper two-bit conversion codes D _O and D ₁ .

Further, as a result of the comparison, for example, V₁₂<V_INso
If present, upper comparator C_U1, C _U2And C_U3Output
Are all "1" levels. This allows AND gate
A_U1~ A_U3Output level is AND gate A_u3Output of
Mi becomes “1” and other AND gate A_U1, A_U2Output
Becomes “0”. As a result, the upper encoder E_U1From above
2 bits conversion code D_O, D₁[11] appears as
Is forced.

Next, the lower conversion operation will be described with reference to FIG. During the conversion operation, all the switching blocks S _{B1 to} S _B12 are in the ON state, and the input analog signal V
_IN is, in each of the switching blocks S _{B1 to} S _B12 ,
Reference voltage V ₁ ~V ₃ of the reference resistance element R ₁ min to R ₁₆ tapped-fine quantization level _{corresponding, V 5 ~V 7, V 9} ~
They are respectively compared with V _11, V ₁₃ ~V _15. In each of the switching blocks S _{B1 to} S _B12 , as a result of the comparison, V _IN
If> V, the output signals S _{1 to} S ₁₂ are output at “1” level, and if V _IN ≦ reference voltage V, the output signals S _{1 to} S ₁₂ are output at “0” level.

Therefore, if V _IN <V ₁ , for example, signals S _{1 to} S ₁₂ of “0” level are output from all switching blocks S _{B1 to} S _B12 . That is, the number of "1" level signals in each column is zero. Accordingly, from all of the even / odd discrimination circuit EOD ₁ ~EOD ₃ signal S _EO1 to S _EO3 is output at "0" level, all even output level of the lower AND gate A _D1 to A _D3 "0"
Becomes As a result, the lower-order encoder outputs two lower-order bits as previous output codes BD ₂ and BD _3.

[00] is output. At this time, the conversion code D ₁ by the upper encoder _{EU 1} is also

[0], the previous output codes BD ₂ , B
D ₃ is not subjected to the inversion action at inverting gate RV _1, the same level

At [00], they are output as lower conversion codes D ₂ and D ₃ .

Also, V₁<V_IN<V_TwoIf so, switch
Ching block S_B1Output signal S₁Only at the "1" level
Output and the remaining switching block S_B2~ S_B12of
The output signal is S_Two~ S₁₂Are output at the “0” level. You
That is, the number of "1" level signals in the first column on the left is (1)
And the number of “1” level signals in the second and third columns
Is zero. Therefore, the even / odd discrimination circuit EOD₁
From the signal S_EO1Is output at “1” level, and even / odd
Number discrimination circuit EOD_Two, EOD_ThreeFrom the signal S_EO2, S
_EO3Is output at the “0” level. This allows
Gate A_D1~ A_D3Output level is AND gate A_D1of
Only the output becomes "1" and the other AND gate A_D2, A_D3
Is "0". As a result, the lower encoder E_D1
Output code BD of lower 2 bits from_Two, BD _ThreeAs
[01] is output. In this case, the upper encoder E
_U1Conversion code D₁Also

Because it is [0],
Force code BD_Two, BD_ThreeIs the inversion gate RV₁Invert action
And receive the lower level conversion code at the same level [01]
D_Two, D _ThreeIs output as

Also, V_Two<V_IN<V_ThreeIf so, switch
Ching block S_B1And S_B2Output signal S₁, S_Twoof
Output at the “1” level, and the remaining switching blocks.
Ku S _B3~ S_B12Output signal is S_Three~ S₁₂Is "0" level
Is output. That is, the first and second columns
The number of “1” level signals is (1), and the number of signals in the third column is
The number of "1" level signals is zero. Therefore, even
/ Odd number discrimination circuit EOD₁And EOD_TwoFrom the signal S
_EO1, S_EO2Is output at "1" level, and even / odd
Another circuit EOD_ThreeFrom the signal S_{EO Three}Output at "0" level
Is done. Thereby, AND gate A_D1~ A_D3Output level
Bell, And Gate A_D2Is only "1",
Other AND gate A_U1, A_U3Is "0". So
As a result, the lower encoder E_D1Previous output of lower 2 bits from
Code BD_Two, BD _ThreeIs output as [10]. This
, The upper encoder E_U1Conversion code D₁Also

[0], the previous output code BD_Two, BD_ThreeIs
Inverting gate RV₁With no leveling effect
Lower-order conversion code D_Two, D _ThreeOutput as
You.

Further, V_Three<V_IN<V_FourThen, Sui
Pitching block S_B1, S_B2And S_B3Output signal
S₁, S_Two, S_ThreeOnly output at “1” level,
Switching block S_B4~ S_B12Output signal is S_Four~
S₁₂Are output at the “0” level. That is, the first column
"1" level in all columns of the eye, second and third columns
Are (1). Therefore, even / odd format
Another circuit EOD₁~ EOD_ThreeFrom the signal S_EO1~ S_{EO Three}But
Output at "1" level. This allows AND gate
A_D1~ A_D3Output level is AND gate A_D3Output of
Mi becomes “1” and other AND gate A_U1, A_U2Output
Becomes “0”. As a result, the lower encoder E_D1From below
2-bit previous output code BD_Two, BD _ThreeAs [1
1] is output. In this case, the upper encoder E_U1To
Conversion code D₁Also

[0], so the previous output
Code BD_Two, BD_ThreeIs the inversion gate RV₁Inversion effect
Lower level conversion code at level [11]
D_Two, D _ThreeIs output as

Although the lower conversion code is obtained as described above, the lower conversion operation is similarly performed when the reference voltage V ₄ <V _IN . However, V ₄ <V _IN <V _{8 and} V ₁₂ <V
_In the case of _IN, the direction of application of the reference voltage is opposite to that of the first and third rows of the switching block array from the bottom in FIG. Since the levels of the previous output codes BD ₂ and BD ₃ are inverted, the level is returned to a normal level in the inversion gate RV _{1 and} output as lower conversion codes D ₂ and D _3. You.

As described above, according to the present embodiment,
By simultaneously operating all of the switching blocks S _{B1 to} S _B12 arranged in a matrix of the serial-parallel A / D conversion circuit, the respective reference voltages V _{1 to} V ₁₅ (however, V ₄ , V ₈ , V
₁₂ ) is compared with the input analog signal V _IN, and whether the number of switching blocks from which the comparison result indicating that the analog signal V _IN is larger than the reference voltage is output is an even number or an odd number is determined for each column. Since the determination is made and the lower conversion is performed according to the result of the determination, the upper and lower conversions can be performed simultaneously. Therefore, the conventional serial-parallel type A
There is no need to provide a sample-and-hold circuit as in the / D conversion circuit, and there is no need for complicated circuit control. To obtain an n-bit conversion code, (2 ⁿ -1)
Compared to a parallel A / D conversion circuit requiring a number of comparators, the number of comparators can be significantly reduced, so that the chip area and power consumption can be reduced.

[0059]

Second Embodiment FIG. 5 is a block diagram showing a second embodiment of the A / D conversion circuit according to the present invention. The present embodiment is essentially different from the above-described first embodiment in that instead of performing even / odd discrimination based on the connection combination of the collector outputs of the transistor differential pairs constituting each switching block in the same column, the same is true. A plurality of block sets each including two adjacent switching blocks in a column are provided, and an exclusive OR of the two switching blocks in each set is obtained.
The result is that a so-called wired OR is used to determine even / odd numbers.

In FIG. 5, EX₁~ EX₆Is even / odd
Number discrimination circuit EOD_1a~ EOD_3aExclusive OR that constructs
Gates are shown, and these connections are made as follows:
Have been. That is, the exclusive OR gate EX₁One of
Input terminal is switching block S_B1Output terminal
And the other input terminal is connected to the switching block S_B6of
EXOR gate EX connected to the output terminal₆One of
Input terminal is switching block S_B7Output terminal
And the other input terminal is connected to the switching block S _B12
EXOR gate EX₁And
And EX₆Are connected to each other and the even number /
Odd number discrimination circuit EOD_1aIs configured. This even / odd
Number discrimination circuit EOD_1aIs an exclusive OR gate EX₁And
And EX₆At the midpoint of the connection between the output terminals of
Performs a wired-or operation on the exclusive-or result of
The result shows the result of the even / odd discrimination in the first column.
Signal S_EO1As buffer B_D1Output to

The exclusive OR gate EX_TwoOne of
Input terminal is switching block S _B2Connect to output terminal of
And the other input terminal is connected to the switching block S_B5Out of
EXOR gate EX_FiveOne of
Input terminal is switching block S_B8Connect to output terminal of
And the other input terminal is connected to the switching block S_B11of
EXOR gate EX connected to the output terminal_Twoand
EX_FiveOutput terminals are connected to each other to form an even / odd
Number discrimination circuit EOD_2aIs configured. This even / odd
Discrimination circuit EOD_2aIs an exclusive OR gate EX_Twoand
EX_FiveAt the midpoint of the connection between the output terminals of
Performs a wired OR of the exclusive OR result,
A signal indicating the result of the even / odd determination in the second column
S_EO2As buffer B_D2Output to

Further, one input terminal of the exclusive OR gate EX ₃ is connected to the output terminal of the switching block S _B3 , and the other input terminal is connected to the output terminal of the switching block S _B4. one input terminal of the EX ₄ is connected to the output terminal of the switching block S _B9, the other input terminal of the switching block S _{B1 0}
Of being connected to the output terminal, the exclusive OR gate EX ₃ and EX output terminals of the ₄ is connected to the third row of the even /
An odd number discriminating circuit EOD _3a is configured. The even / odd number discriminating circuit EOD _3a performs a wired OR operation on the exclusive OR result of the exclusive OR gates EX ₃ and EX _{4 at} the midpoint of the connection between the output terminals of the gates. and outputs to the buffer B _D3 as a signal S _EO3 of a third row of the even / odd determination result.

In the configuration shown in FIG. 5, the upper comparators C _{U1 to} C _U3 are not composed of complementary outputs but are composed of ordinary single outputs, and the next stage, that is, AND gates A _{U1 to} A _U1.
U3 complementary output buffer B _U1 .about.B _U3 on the input side is provided for, further AND gates A _U1 to A output and the upper encoder E _U1 of _U3
, The multi-output pin buffers MB _{U1 to} MB _U3 are provided between them, but the upper conversion function has the same function as that of the first embodiment. Similarly,
Although the multi-output pin buffers MB _{D1 to} MB _D3 are provided between the outputs of the AND gates A _{D1 to} A _{D3 and} the input of the lower encoder E _D1 , the lower conversion function is the same as that of the first embodiment. It has the same function as.

Next, the operation of the configuration of FIG. 5 will be described with reference to the timing chart of FIG. Note that the high-order conversion operation is essentially the same as in the first embodiment, and a description thereof will be omitted.

As in the case of the first embodiment, the conversion
When working, all switching blocks S_B1~ S_B12Is
In the ON state, the input analog signal V_INIs each switch
Block S_B1~ S_B12, The reference resistance element R₁
~ R₁₆Corresponding criterion for fine quantization level divided by
Voltage V₁~ V_Three, V_Five~ V₇, V₉~ V₁₁, V₁₃~ V _Fifteen
Is compared to Each switching block S_B1~
S_B12In the comparison, V_IN> Reference voltage V
Output signal S₁~ S₁₂Is "1" level, V_IN≤ criteria
If the voltage is V, the output signal S₁~ S₁₂Appears at the “0” level
Is forced.

Therefore, for example, V_IN<V₁That
If all switching blocks S_B1~ S_B12From
"0" level signal S₁~ S₁₂Is output. others
All exclusive OR gates EX₁~ EX₆Both inputs
The signal level input to the terminal is “0”. Accordingly
And all exclusive OR gates EX₁~ EX₆Output level
Since the bell becomes "0", all the even / odd discrimination times
Road EOD_1a~ EOD_3aFrom the signal S_{EO 1}~ S_EO3But
Output at "0" level, lower AND gate A_D1~ A
_D3Are all "0". As a result,
Encoder E_D1Output code BD of lower 2 bits from_Two,
BD _ThreeAs

[00] is output, and at this time, the conversion code D ₁ by the upper encoder _EU1 is also output.

Be [0]
From the previous output code BD_Two, BD_ThreeIs the inversion gate RV ₁
With no inversion effect

At [00], they are output as lower conversion codes D ₂ and D ₃ .

V₁<V_IN<V_TwoIf so, switching
Block S_B1Output signal S₁Only output at "1" level
And the remaining switching block S_B2~ S_B12Output signal
The number is S_Two~ S₁₂Are output at the “0” level. others
Exclusive OR gate EX in the first column from the left₁
Output level becomes “1” and the other exclusive OR gate
EX_Two~ EX₆Is "0". did
Therefore, the even / odd discrimination circuit EOD₁From the signal S_EO1
Is output at the “1” level, and the even / odd discrimination circuit EOD is output.
_Two, EOD_ThreeFrom the signal S_EO2, S_EO3Is "0" level
Is output. Thereby, AND gate A_D1~ A_D3of
Output level is AND gate A_D1Is only "1"
Becomes another AND gate A_D2, A_D3Output is "0"
You. As a result, the lower encoder E_D1From the lower 2 bits
Previous output code BD_Two, BD _Three[01] is output as
You. In this case, the upper encoder E_U1Conversion code by
D₁Also

[0], the previous output code BD_Two, B
D_ThreeIs the inversion gate RV₁With no inversion effect
Conversion code D at level [01]_Two, D _ThreeOut as
Is forced.

V_Two<V_IN<V_ThreeIf so, switching
Block S_B1And S_B2Output signal S₁, S_Twoonly
Output at "1" level and the remaining switching blocks
S_B3~ S _B12Output signal is S_Three~ S₁₂Is output as "0"
It is. Therefore, the exclusive OR gate EX₁, EX_Twoof
Only the output level becomes “1” and the other exclusive OR
EX_Three~ EX₆Is "0". But
, Even / odd discrimination circuit EOD₁And EOD_TwoFrom
Is the signal S_EO1, S_EO2Is output at the “1” level, and the even number
/ Odd number discrimination circuit EOD_ThreeFrom the signal S_{EO Three}Is “0” level
Is output by default. Thereby, AND gate A_D1~ A_D3
Output level is AND gate A_D2Output is only "1"
And the other AND gate A_U1, A_U3Output is "0"
Become. As a result, the lower encoder E_D1Lower 2 bits from
Output code BD before_Two, BD _Three[10] is output as
It is. In this case, the upper encoder E_U1Conversion code by
Do D₁Also

[0], the previous output code BD_Two,
BD_ThreeIs the inversion gate RV₁Without the reversal effect.
Lower level conversion code D at level [10]_Two, D _ThreeAs
Is output.

V_Three<V_IN<V_FourIf so, switching
Block S_B1, S_B2And S_B3Output signal S₁, S_Two,
S_ThreeOnly output at "1" level and the rest of the switching
Block S_B4~ S_B12Output signal is S_Four~ S₁₂Is "0"
Is output. Therefore, the exclusive OR gate EX₁,
EX_TwoAnd EX_ThreeOnly the output level of becomes “1”,
Other exclusive OR gate EX_Four~ EX₆Output level is
It becomes "0". Therefore, the even / odd discrimination circuit EOD
₁~ EOD_ThreeFrom the signal S_EO1~ S_{EO Three}Is "1" level
Is output. Thereby, AND gate A_D1~ A_D3of
Output level is AND gate A_D3Is only "1"
Becomes another AND gate A_U1, A_U2Output is "0"
You. As a result, the lower encoder E_D1From the lower 2 bits
Previous output code BD_Two, BD _Three[11] is output as
You. In this case, the upper encoder E_U1Conversion code by
D₁Also

[0], the previous output code BD_Two, B
D_ThreeIs the inversion gate RV₁With no inversion effect
At lower level [11]_Two, D _ThreeOut as
Is forced.

When V ₄ <V _IN <V ₅ , V ₃ <
This is the same as the case of V _IN <V ₄ , but in this case, the conversion code D ₁ by the upper encoder _{EU 1} Is [1], the previous output codes BD ₂ and BD ₃ are inverted gates RV ₁
Inverted by the level

At [00], they are output as lower conversion codes D ₂ and D ₃ .

Further, V_Five<V_IN<V₆Then, Sui
Pitching block S_B1~ S_B4Output signal S₁~ S_Fouronly
Output at "1" level and the remaining switching blocks
S_B5~ S_B12Output signal is S_Five~ S₁₂Is output as "0"
It is. Therefore, the exclusive OR gate EX₁And EX
_TwoBecomes only "1" and the other exclusive OR
Gate EX_Three~ EX₆Is "0". I
Therefore, the even / odd discrimination circuit EOD₁And EOD_Two
From the signal S_EO1, S_EO2Is output at the “1” level,
Even / odd discrimination circuit EOD_ThreeFrom the signal S_{EO Three}Is "0"
Output at the level. Thereby, AND gate A_D1~
A_D3Output level is AND gate A_D2Only the output of
"1" and other AND gate A_U1, A_U3The output of
It becomes "0". As a result, the lower encoder E_D1From lower
2-bit previous output code BD_Two, BD _ThreeAs [10]
Is output. In this case, the upper encoder E_U1by
Conversion code D₁Is [1], so the previous output code
BD_Two, BD_ThreeIs the inversion gate RV₁In reverse action,
Lower level conversion code D at level [01]_Two, D_ThreeOutput as
Is done.

V₆<V_IN<V₇If so, switching
Block S_B1~ S_B5Output signal S₁~ S_FiveIs "1" level
And the remaining switching block S_B6~ S
_B12Output signal is S₆~ S₁₂Is output as "0". This
, The exclusive OR gate EX₁Only the output level of
It becomes "1" and the other exclusive OR gate EX_Two~ EX₆
Is "0". Therefore, even / odd
Discrimination circuit EOD₁From the signal S_EO1Comes out at "1" level
, Even / odd discrimination circuit EOD_Two, EOD_ThreeFrom
Signal S_EO2, S_EO3Is output at the “0” level. this
By AND gate A_D1~ A_D3Output level is
Dogate A_D1Is only "1" and other AND
A_U2, A_U3Is "0". As a result,
Encoder E_D1Output code B of lower 2 bits from
D_Two, BD _ThreeIs output as [01]. At this time
Is the upper encoder E_U1Conversion code D₁Is [1]
, The previous output code BD_Two, BD_ThreeIs inverted
Auto RV₁At the level [10].
Exchange code D_Two, D_ThreeIs output as

V₇<V_IN<V₈If so, switching
Block S_B1~ S_B6Output signal S₁~ S₆Is "1" level
And the remaining switching block S_B7~ S
_B12Output signal is S₇~ S₁₂Is output as "0". This
, All exclusive OR gates EX₁~ EX₆Out of
The power level becomes “0”. Therefore, all even /
Odd number discrimination circuit EOD_1a~ EOD_3aFrom the signal S_{EO 1}~ S
_EO3Is output at the “0” level. This allows
Gate A_D1~ A_D3Output level of all AND gates
A _D1~ A_U3Becomes "0". As a result,
Position encoder E_D1Output code BD of lower 2 bits from
_Two, BD _ThreeAs

[00] is output. At this time,
The conversion code D ₁ by the upper encoder E _U1 since it is [1], before the output code BD _2, BD ₃ are subjected to inversion action at inverting gate RV _1, lower conversion code D ₂ level [11], D ₃ Is output as

Thereafter, when V ₈ <V _IN <V ₁₂ , the conversion code D ₁ by the upper encoder _{EU 1} is

[0]
The replacement operation is performed using the V_IN<V_FourIs the same as₁₂
<V _IN, The upper encoder E_U1Conversion code by
Do D_ThreeIs [1], so the conversion operation is
_Four<V_IN<V₈The operation is the same as in the case of.

As described above, also in the second embodiment, the same effects as in the first embodiment can be obtained.

In the first and second embodiments described above, the circuit configuration corresponding to 4-bit conversion has been described as an example. However, the present invention can be applied to the case of multi-bit conversion as well. It goes without saying that the effect of (1) can be obtained.

[0077]

As described above, according to the present invention,
There is an advantage that an increase in power consumption and a chip area can be prevented, and there is no need to provide a sample-and-hold circuit, so that complicated circuit control can be prevented.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a first embodiment of an A / D conversion circuit according to the present invention.

FIG. 2 is a diagram showing a circuit configuration example of a switching block and an even / odd discrimination circuit according to the present invention.

FIG. 3 shows an output level of an upper comparator, an output level of an AND gate, and an upper conversion code of an A / D conversion circuit according to the present invention in accordance with the magnitude of an input voltage (analog signal) level with respect to a reference voltage at the time of upper conversion. FIG. 4 is a diagram illustrating a correspondence relationship between output levels.

FIG. 4 shows the output signal level of the switching block and the output signal level of the even / odd determination circuit according to the magnitude of the input voltage (analog signal) level with respect to the reference voltage at the time of lower conversion of the A / D conversion circuit according to the present invention. FIG. 7 is a diagram showing a correspondence relationship between an output level of an AND gate and an output level of a lower conversion code.

FIG. 5 is a configuration diagram showing a second embodiment of the A / D conversion circuit according to the present invention.

FIG. 6 is a timing chart for explaining the operation of FIG. 5;

FIG. 7 is a configuration diagram showing an outline of a conventional serial-parallel A / D conversion circuit.

FIG. 8 is a timing waveform chart of sampling of the circuit of FIG. 7;

[Explanation of symbols]

R ₁ to R ₁₆ ... reference resistance element C _U1 -C _U3 ... upper comparator A _U1 to A _U3 ... upper AND gate E _U1 ... upper encoder S _B1 to S _B12 ... switching block EOD ₁ ~EOD ₃ ... even / odd discrimination circuit B _D1 .about.B _D3 ... complementary output buffer A _D1 to A _D3 ... lower aND gate E _D1 ... lower encoder RV ₁ ... inverting gate V _IN ... input analog signal V _RT, V _RB ... reference voltage EX ₁ ~EX ₆ ... Exclusive OR gate

Claims (7)

(57) [Claims] 1. A predetermined series connection between two reference potentials,
Fold so that the application direction of the reference voltage is reversed for every number of elements.
They are arranged in a matrix to compare the n reference resistive elements arranged in a plurality of rows, with each reference voltage by dividing by the series connection the n reference resistance element and the object to be converted input signal returns, simultaneous A plurality of switching blocks which are driven in parallel, a reference voltage of a coarse quantization level applied to a specific position in a row direction of the switching blocks, and the converted input signal, and a conversion code of upper bits And a determination circuit that determines whether the number of switching blocks that have obtained a comparison result that the converted input signal level is higher than the reference voltage level is even or odd for each row of the switching blocks in the column direction. , the reference resistance element and the lower encoder to obtain a conversion code of lower bits corresponding to the discrimination result of the discrimination circuit, the voltage application direction of the predetermined row as a reference According
By the lower encoder obtained based on the reference voltage
Lower conversion code as input code or inverted
An analog / digital conversion circuit having an inverting gate for outputting . 2. The high-order encoder obtains a plurality of conversion codes related to high-order bits, and the inverting gate outputs a conversion code related to high-order bits excluding the most significant bit from the high-order conversion codes of the high-order encoder. 2. The analog / digital conversion circuit according to claim 1, wherein the lower-order conversion code by the lower-order encoder is output as it is or as an inverted input code. 3. The inversion gate obtains an exclusive OR of a conversion code relating to an upper bit excluding the most significant bit of a conversion code of an upper bit by the upper encoder and a lower conversion code by the lower encoder. 3. The analog / digital conversion circuit according to claim 2, which outputs. 4. The lower-order conversion by the lower encoder obtained based on a reference voltage by a reference resistance element in a row in an application direction opposite to the inversion gate, based on a voltage application direction in a predetermined row. 4. The analog / digital conversion circuit according to claim 1, wherein the code is inverted and output. 5. Each of the switching blocks includes a differential amplifier having a pair of transistors to each of which a base is supplied with a converted input signal and a divided reference voltage. 5. The analog / digital conversion circuit according to claim 1, wherein a transistor output to which an input signal is supplied and a transistor output to which a reference voltage is supplied are alternately connected to a load element. . 6. The method according to claim 1, wherein said discriminating circuit includes means for obtaining an exclusive OR of adjacent switching blocks for each column, and outputting the sum to a lower encoder.
4. The analog / digital conversion circuit according to 4 or 5. 7. The circuit according to claim 6, wherein the discriminating circuit has a plurality of exclusive OR gates for obtaining exclusive ORs of outputs of adjacent switching blocks, and the outputs of the respective exclusive OR gates are connected. An analog / digital conversion circuit as described in the above.