JP3222566B2 - Multilayer wiring structure of semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring structure for a semiconductor integrated circuit, and more particularly to a multilayer wiring structure in which wiring is performed between different layers using via holes and contact holes. It is.

[0002]

2. Description of the Related Art With respect to a conventional multilayer wiring structure of a semiconductor integrated circuit, a VLSIC (Very Large Scale Integrated Circuit) is used.
cuit) will be described as an example. VLSI
In, the wiring pattern is usually formed in two or three layers.

FIG. 3A is a sectional view schematically showing an example of the layer structure of such a VLSIC. In FIG. 1, an insulating layer 32, a wiring layer 33, an insulating layer 34, and a wiring layer 35 are formed on a semiconductor substrate 31 formed of silicon or the like.
Are sequentially formed. Here, the first wiring layer 33
Are constituted by a plurality of wiring patterns formed on the surface of the insulating layer 32. Similarly, the second wiring layer 35
Are composed of a plurality of wiring patterns formed of a conductive material on the surface of the insulating layer. Each insulating layer 32,
Numeral 34 is provided for insulation between the semiconductor substrate 31 and the wiring layer 32 and for insulation between the wiring layer 32 and the wiring layer 35.

The insulating layers 32 and 34 have holes 41 to 46, respectively.
Is provided. This is provided for connecting the substrate 31 and the wiring pattern and for connecting wiring patterns of different wiring layers. In other words, by embedding a conductive material (for example, aluminum or the like) in these holes 41 to 46 to form the connection portions 41a to 46a, the substrate or the wiring pattern below the holes and the wiring pattern above the holes are formed. An electrical connection can be made.

[0005] Of these holes 41 to 46, the insulating layer 3
The holes 41 to 43 (that is, the holes for connecting the substrate 31 and the wiring pattern) provided in the substrate 2 are generally called contact holes. The holes 44 to 46 provided in the insulating layer 34 (that is, holes for connecting wiring patterns of different wiring layers) are generally called via holes.

When a connection between wiring patterns (or a connection between a substrate and a wiring pattern) is made, usually, as shown in FIG. Contact holes). Hereinafter, the reason for this will be described with reference to FIG. Here, FIG.
FIG. 3B shows the wiring layer 3 from the layer structure shown in FIG.
3 is a conceptual diagram in which only wiring patterns 33a and 35a in 3, 35 and connection portions 44a to 46a in an insulating layer 34 are extracted and shown.

[0007] Connections 44a- of via holes 44-46
46a has inferior electromigration resistance as compared with the wiring patterns of the wiring layers 33 and 35. Here, “electromigration” means that metal atoms constituting a wiring move by a high-density current flowing through the wiring (which indicates the wiring patterns 33 a and 35 a and the connection parts 44 a to 46 a). This electromigration reduces the cross-sectional area of the wiring and causes disconnection.

Since the electromigration becomes more intense as the current density increases, it is necessary to improve the electromigration resistance of the via hole by using the wiring layer 3.
3,35 wiring pattern wiring 33a, 35a in the flowing current I ₀ of the current value A is larger also the connecting portions 44a
It is effective not to increase the current density of .about.46a. This is why a plurality of via holes 44 to 46 are provided for one connection point in a conventional VLSI. Thus, the current I ₀ in the wiring pattern flows is divided into the connecting portions 44A～46a, current i ₁ flowing through the respective connection portions, i _2, i ₃
Can be reduced, and the current density (current value 電流 cross-sectional area of wiring) can be reduced. As a result, the reliability of the multilayer wiring structure as a whole can be improved.

[0009]

Here, in order to make the reliability of the multilayer wiring structure sufficient, each connection portion 44a
It is desirable to equalize the current values of the currents i ₁ , i ₂ , i ₃ flowing through ４６46a. If the current values are not uniform, the current density will not be uniform, and a high-density current will flow through any of the connection portions 44a to 46a. The reliability of the entire wiring structure is impaired.

[0010] However, in the conventional VLSIC, no current I ₀ flowing from the wiring pattern 33a is equally divided into the connecting portions 44A～46a, therefore, significant to the density of the current flowing in these connections 44A～46a There is a difference.

FIG. 4 shows a measurement example of the variation of the current value in the layer structure as shown in FIG. This is Ahsa
n Technical disclosure by Enver and J. Joseph Clement (FINITE ELEMENT NUMERICAL OF CURRENT
IN VLSI INTERCONNECTS, Proceedings of the 7th Int
ernational IEEE VLSI Multilevel InterconnectionCon
ference, pp. 149-155, 1990).

As can be seen from FIG.
current I ₀ flowing from a wiring pattern 33a is not evenly divided into three connecting portions 44a~46a, 60% of the current I ₀ flows in the connection portion 44a. For this reason, disconnection due to electromigration is very likely to occur at the connection portion 44a, which is a cause of deteriorating the reliability of the multilayer wiring structure.

[0013] Such technical problems occur not only in via holes but also in contact holes.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks of the prior art, and is directed to a semiconductor integrated circuit having excellent uniformity of current flowing in a plurality of holes provided for one connection point. An object is to provide a multilayer wiring structure.

[0015]

[Means for Solving the Problems]

(1) The multilayer wiring structure of a semiconductor integrated circuit according to the first invention is a multilayer wiring structure of a semiconductor integrated circuit for electrically connecting a wiring pattern formed on a substrate via an insulating film to the substrate. And the wiring pattern corresponds to the substrate.
The insulating film has a plurality of holes formed at positions facing the annular pattern region, and the insulating film is formed through the plurality of holes. An annular pattern region and the substrate are electrically connected. (2) The multilayer wiring structure of a semiconductor integrated circuit according to the second invention is a semiconductor integrated circuit having a multilayer wiring structure for electrically connecting a first wiring pattern and a second wiring pattern formed via an insulating film. A multilayer wiring structure, wherein the first wiring pattern is in a horizontal plane with respect to the second wiring pattern.
The insulating film has a plurality of holes formed at positions facing the annular pattern region, and the annular pattern is formed through the plurality of holes. The region and the second wiring pattern are electrically connected.

[0016]

According to the present invention , a part of a wiring pattern is replaced with a substrate or other wiring
Annular path formed annularly in the horizontal plane for over emissions
Formed in turn-regions, the annular pattern to form a plurality of holes at a position opposed to the annular pattern region of the insulating film
By making an electrical connection between the region and the substrate or another wiring pattern, current is supplied from two directions to the electrical connection in each hole through the wiring pattern . Thereby, the uniformity of the current flowing in each hole can be improved.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A multilayer wiring structure of a semiconductor integrated circuit according to the present invention will be described below by taking a multilayer wiring structure of a VLSIC as an example. FIG. 1 is a perspective view conceptually showing the multilayer wiring structure of the present embodiment. As shown in FIG.
On 1, a first-layer wiring pattern 12 is formed of a conductive material. The wiring pattern 12
Has a ring-shaped pattern region (hereinafter, ring-shaped pattern region) 12a.

Such a wiring pattern 12 can be formed by depositing a conductive thin film using a known technique, and performing masking and etching on the thin film.

Examples of the conductive material that can be used for forming the wiring pattern 12 include metals such as aluminum and copper, and metal silicides such as tungsten silicide and molybdenum silicide.

The wiring pattern 12 is covered with an insulating film 13. Here, a plurality of (three in FIG. 1) via holes are formed in the insulating film 13. These via holes 13 a to 13 c are respectively formed on the annular pattern region 12 a of the wiring pattern 12.

The via holes 13a to 13c can be formed by performing masking and etching using a known technique. As an etching method, for example, a reactive ion etching (RIE) method is known.

In this embodiment, the distance d from the end of the annular pattern area 12a to the via hole 13a is 5 μm.

In the via holes 13a to 13c, a conductive material is buried so that the connection portions 15a to 15c can be formed.
15c is formed. These connection parts 15a to 15c
Can be formed of tungsten, copper, aluminum, or the like.

On the insulating film 13, a second-layer wiring pattern 14 is formed. The wiring pattern 14 also has an annular pattern area 14a, similarly to the wiring pattern 12 described above.
have. This annular pattern region 14a is formed on via holes 13a to 13c. Further, the wiring pattern 13 can be formed by using the same conductive material as the above-described wiring pattern and by the same method.
Here, the distance d 'from the end of the annular pattern region 14a to the via hole 13c is 5 μm.

In such a multilayer wiring structure, when the current I ₀ flows along the path A in the wiring pattern 14 and reaches the annular pattern area 14a, the current I ₀ becomes equal to the current I ₁ flowing along the path B. Current I ₂ flowing along path C
And divided into

Then, the current I ₁ further includes the currents i _a1 , i
_b1 and i _c1 are divided and flow into the connection parts 15a to 15c,
It flows into the annular pattern area 12a of the wiring pattern 12. Also, the current I ₂ is the same as the current I ₁ , the current i _a2 , i
_b2 and i _c2 are divided and flow into the connection parts 15a to 15c,
It flows into the annular pattern area 12a of the wiring pattern 12. Accordingly, the current flowing in the connecting portion 15a~15c, respectively, the _{i a1 + i a2, i b1} + i b2, i c1 + i c2.

Here, the ratio of the currents i _a1 , i _b1 , i _c1 flowing through the connecting portions 15a to 15c is the same as that of the conventional multilayer wiring structure (see FIG. 3) (see FIG. 4), and FIG. (A)
, The current i _a1 is about 60% of I ₁ and the current i _b1
Is about 25% of I _{1 and} the current i _c1 is about 15% of I ₁ . That is, the value of the current i _a1 is the largest, and the value of the current i _b1 is the smallest.

Further, the ratio of current i _a2, i _b2, i _c2 flow connection portion 15a~15c, as shown in FIG. 2 (b), the current i _a2 is about 15% of I _2, the current i _b2 about 2 of I ₂ is
The 5% current i _c2 is about 60% of I ₂ . That is, the value of the current i _c2 is the largest, and the value of the current i _a2 is the smallest.

Therefore, the ratio of the currents flowing through the connecting portions 15a to 15c, ie, _ia1 + _ia2 , _ib1 + _ib2 , _ic1
The ratio of + i _c2, as shown in FIG. 2 (c), respectively, about 37.5% of the current _{I 0 (= I 1 + I} 2), about 25%, of about 37.5%.

[0030] Each current supplied to the annular pattern area 12a from the connection portion 15a~15c will current I ₄ flowing along the current I ₃ and the route E flows along path D.
Then, the currents I ₃ and I ₄ reach the path F and
_It becomes ₀ and flows through the wiring pattern 12 along this path F.

When a current flows from the wiring pattern 12 side to the wiring pattern 14 side, a path reverse to that described above is followed. In this case, as in the case described above, the connection unit 1
The currents flowing through 5a to 15c can be equalized.

As described above, according to the multilayer wiring structure of the VLSI according to the present embodiment, each of the via holes 13a to 13c
Since current is supplied to the connection portions 15a to 15c formed therein in two directions, the uniformity of the current flowing through the connection portions 15a to 15c can be improved.

Therefore, according to the multilayer wiring structure of the present embodiment, the problem that the current density of the current flowing through any of the connection portions 15a to 15c is large does not easily occur, and electromigration occurs at such connection portion. Possibility is reduced, and the reliability of the entire multilayer wiring structure can be improved.

In this embodiment, the case where both the wiring pattern 12 and the wiring pattern 14 have an annular pattern region has been described. However, when the current flows in only one direction, the current is supplied. The effect of the present invention can be obtained by forming an annular pattern region only on the wiring pattern on the side where the wiring pattern is formed.

In addition, in this embodiment, the case where two wiring patterns are electrically connected via three via holes has been described as an example, but the case where three or more wiring patterns are connected to each other is also described. The same effect can be obtained, and the number of via holes is not particularly limited.

In addition, in this embodiment, the case where the electrical connection between the wiring patterns of the different layers is made is described. However, the present invention can be applied to the case where the electrical connection between the semiconductor substrate and the wiring pattern is made. it can.

[0037]

As described above in detail, according to the present invention, a multilayer wiring structure of a semiconductor integrated circuit having excellent uniformity of current flowing through each hole, that is, a multilayer wiring structure of a highly reliable semiconductor integrated circuit. A wiring structure can be provided.

[Brief description of the drawings]

FIG. 1 is a perspective view conceptually showing a multilayer wiring structure of a semiconductor integrated circuit according to one embodiment of the present invention.

FIGS. 2A to 2C are graphs for explaining a ratio of a current value flowing to each connection portion of the multilayer wiring structure shown in FIG.

3A and 3B are conceptual diagrams illustrating an example of a conventional multilayer wiring structure of a semiconductor integrated circuit, in which FIG. 3A is a cross-sectional view, and FIG. 3B is a perspective view illustrating only a wiring portion.

FIG. 4 is a graph showing a ratio of a current value flowing to each connection portion of the multilayer wiring structure shown in FIG.

[Explanation of symbols]

 11, 13 Insulating film 12, 14 Wiring pattern 12a, 14a Annular pattern area 15a, 15b, 15c Connection

──────────────────────────────────────────────────の Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/3205-21/3213 H01L 21/768

Claims (3)

(57) [Claims] 1. A multilayer wiring structure of a semiconductor integrated circuit for electrically connecting a wiring pattern formed on a substrate via an insulating film to the substrate, wherein the wiring pattern is in a horizontal plane with respect to the substrate.
The insulating film has a plurality of holes formed at positions facing the annular pattern region, and the annular pattern region is formed through the plurality of holes. A multilayer wiring structure for a semiconductor integrated circuit, wherein the wiring is electrically connected to the substrate. 2. A multilayer wiring structure of a semiconductor integrated circuit for electrically connecting a first wiring pattern and a second wiring pattern formed via an insulating film, wherein the first wiring pattern is Are in the second wiring pattern
An annular pattern region formed in an annular shape in a horizontal plane, the insulating film has a plurality of holes formed at positions facing the annular pattern region, and through the plurality of holes, The multilayer wiring structure of a semiconductor integrated circuit, wherein the annular pattern region and the second wiring pattern are electrically connected. 3. A horizontal plane with respect to the first wiring pattern at a position where the second wiring pattern faces the hole.
An annular pattern region formed in an annular shape at the inner, through the plurality of holes, said first and said annular pattern area of said annular pattern region and the second wiring pattern of the wiring pattern is electrically 3. The multilayer wiring structure for a semiconductor integrated circuit according to claim 2, wherein the wiring is connected to the semiconductor device.