JP3225480B2 - Current type sense circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current sensing circuit used for detecting a minute differential input signal in a memory LSI or the like, and more particularly to a current sensing circuit having improved switching characteristics. .

[0002]

2. Description of the Related Art A conventional current-type sensing circuit is described in detail in the literature (Shibata, "Method of configuring current-type sensing circuit in low-voltage memory", IEICE Technical Report ICD).
95-28 May 1995). The prior art will be described below based on the above literature.

FIG. 4 is a circuit diagram of the conventional current-type sensing circuit. T1 and T2 are first and second input terminals for differential input, T3 and T4 are first and second output terminals for differential output, and T5 to T7 are circuit nodes. Q1-Q4 are PchM
OS transistors, Q5 to Q7 are Nch MOS transistors, R1 and R2 are resistors, C1 and C2 are output terminals T3 and T
4 is the load capacity. φ _SAE is the activation of the entire sense circuit /
This is a signal for controlling the inactivation. When the signal is controlled to a high level voltage, the signal is turned on and the sense circuit becomes operable. The resistors R1 and R2 may be replaced by diode-connected MOS transistors or the like. In this circuit, by inputting a differential current signal to the input terminals T1 and T2, a differential voltage signal is obtained at the output terminals T3 and T4.

This circuit comprises a first stage for converting an input current signal into a voltage signal, and an amplification stage for amplifying the output of the first stage. First, the first stage includes a first grounded-gate amplifier circuit including a resistor R1 and a transistor Q1 using the resistor R1 as a load, and a second grounded-gate amplifier circuit including a resistor R2 and a transistor Q2 using the resistor R2 as a load. Consists of The first grounded-gate amplifier circuit is connected between the input terminal T1 and the circuit node T7,
Is connected to the input terminal T2 and the circuit node T7.
Connected between In the original grounded-gate type amplification circuit,
The gate electrodes of the MOS transistors Q1 and Q2 are AC grounded, and this circuit can be connected in such a manner. However, here, the gate electrodes are connected to the output nodes T5 and T6 of the other grounded-gate amplifier circuit. The connection increases the amount of change in the gate-source voltage of the transistors Q1 and Q2, and improves the effective transconductance of the MOS transistors Q1 and Q2.

The amplification stage includes a first CMOS inverter amplification circuit including transistors Q3 and Q5, and a transistor Q3.
4 and a second CMOS inverter amplifier circuit composed of Q6. The first CMOS inverter amplifier circuit is connected between the input terminal T1 and the circuit node T7, inputs and amplifies the voltage signal at the circuit node T6, and outputs the amplified signal to the output terminal T3. Further, the second CMOS inverter amplifier circuit is connected between the input terminal T2 and the circuit node T7, and the circuit node T
5 is input, amplified, and output to the output terminal T3. When the output amplitude of the first stage is small, a through current flows through the amplification stage. However, this is not the essence of the circuit operation.

The operation of the conventional current-type sensing circuit shown in FIG. 4 is as follows. The circuit is assumed to be set symmetrically. That is, transistors Q1 and Q2, Q3 and Q4, Q5 and Q6, resistors R1 and R2, and load capacitors C1 and C2.
2 has the same circuit constant.

First, the equilibrium state will be described. At this time, since the differential input currents flowing through the input terminals T1 and T2 are equal, the input terminals T1 and T2, the output terminals T3 and T4,
The circuit nodes T5 and T6 have the same potential. The potentials of the output terminals T3 and T4 are equal to the potentials of the input terminals T1 and T2 and the node T.
7, the electric charges corresponding to the voltages of the output terminals T3 and T4 are accumulated in the load capacitors C1 and C2.

Consider a case where the current flowing through transistor Q1 increases by ΔI and the current flowing through transistor Q2 decreases by ΔI from the above equilibrium state. At this time, the potential of the node T5 increases by ΔV, and the potential of the node T6 decreases by ΔV. Since the total amount of current flowing from the input terminals T1 and T2 does not change, the potential of the node T7 does not statically change.

However, as the potential at the node T6 decreases, the load capacitance C1 is charged with electric charge via the transistor Q3 in the path indicated by the arrow, and the potential at the output terminal T3 becomes high. Regarding the load capacitance C2, the transistor Q
6, electric charges are discharged in the path indicated by the arrow through Q7, and the potential of the output terminal T4 becomes low. The charging and discharging of electric charges is a dynamic operation.

[0010]

At this time, the transistor Q7 is controlled to be conductive by the activation signal φ _SAE of the sense circuit, but has a finite conduction resistance. For this reason, when there is discharge of electric charge from the load capacitance C2,
This discharge current generates a back electromotive force at both ends of the transistor Q7, and the voltage level of the common node T7 rises. This rise in the voltage level at the node T7 is temporary until the discharge of the load capacitance C2 ends. However, during this period, the voltage level at the node T6 is prevented from lowering, resulting in a delay in the switching time of the sense circuit. Will be. This has been a problem in operating the sense circuit at high speed.

An object of the present invention is to solve the above-mentioned problems,
An object of the present invention is to provide a current-type sensing circuit having improved switching characteristics.

[0012]

A first invention is connected between a first input terminal and a first circuit node, and converts a current signal input to the first input terminal into a voltage signal. A first grounded-type amplifier circuit that outputs a current signal, and is connected between a second input terminal and a second circuit node, converts a current signal input to the second input terminal into a voltage signal, and outputs the voltage signal. A second grounded-amplifier circuit, the first input terminal and the second
A first CMOS inverter amplifier circuit which is connected between the first and second circuit nodes and receives and amplifies an output voltage of the second grounded-gate amplifier circuit and outputs the amplified output voltage to a first output terminal; Connected between the terminal and the first circuit node,
A second CMOS inverter amplifier circuit for receiving and amplifying an output voltage of the first grounded-gate amplifier circuit and outputting the amplified voltage to a second output terminal; and providing the first circuit node and the second
Are separated from each other and each of them is grounded via a predetermined impedance element to constitute a current-type sense circuit.

According to a second aspect of the present invention, in the first aspect,
The first circuit node and the second circuit node are independently grounded via first and second switching elements, or independently grounded via first and second resistors, respectively. As a current-type sensing circuit.

According to a third aspect, in the first aspect,
One end of each of the third and fourth resistors is independently connected to the first circuit node and the second circuit node, and the other end of the third and fourth resistors is connected to the third and fourth resistors. A current sensing circuit is characterized in that it is grounded via a third switching element which is sufficiently smaller than the resistance value of the fourth resistor.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] FIG. 1 is a circuit diagram showing a current-type sensing circuit according to a first embodiment. The same components as those described in FIG. 4 are denoted by the same reference numerals, and detailed description thereof will be omitted. Q71 and Q72 are Nch MOS transistors. The conventional circuit shown in FIG.
Using Q72, the node T7 shown in FIG.
And the transistors Q71 and Q72 are controlled by a common activation signal φ _SAE .

That is, the first grounded-gate amplifier circuit, which comprises a resistor R1 and a transistor Q1 having the resistor R1 as a load, converts a current signal input to the input terminal T1 into a voltage signal and outputs the voltage signal to the node T5, It is connected between the input terminal T1 and the circuit node T71. Further, it is composed of a resistor R2 and a transistor Q2 having the resistor R2 as a load.
The second gate-grounded amplifier circuit that outputs the signal to the input terminal T
2 and a circuit node T72. Node T6
Is connected between the input terminal T1 and the node T72. The first CMOS inverter amplifying circuit including the transistors Q3 and Q5 which inputs and amplifies the voltage signal and outputs it to the output terminal T1. Further, a second CMOS inverter amplifier circuit including transistors Q3 and Q5 that inputs and amplifies the voltage signal at the node T5 and outputs it to the output terminal T2 is connected between the input terminal T2 and the node T71. The gate electrode of the transistor Q1 of the first grounded-gate amplifier circuit is connected to the node T6, but may be grounded in an AC manner. In addition, the first
The gate electrode of the transistor Q2 of the common-gate amplifier circuit is connected to the node T5.

In this sense circuit, it is assumed that the circuit is designed symmetrically. That is, the transistor Q1
And Q2, Q3 and Q4, Q5 and Q6, Q71 and Q72, resistors R1 and Q2, and load capacitors C1 and C2 have the same circuit constants.

Next, the operation will be described. In a balanced state, the differential input currents flowing through the input terminals T1 and T2 are equal, so that the input terminals T1 and T2, the output terminals T3 and T4, the circuit nodes T5 and T6, and T71 and T72 have the same potential. The potential of the output terminals T3 and T4 is an intermediate potential between the potential of the input terminals T1 and T2 and the potential of the node T71 or T72 (substantially the ground potential), and the load capacitors C1 and C2 correspond to the voltages of the output terminals T3 and T4. Charge is accumulated.

Consider a case where the current flowing through the transistor Q1 increases by ΔI and the current flowing through the transistor Q2 decreases by ΔI from the above equilibrium state. At this time,
The potential at the node T5 increases by ΔV, and the potential at the node T6 increases by ΔV.
V.

When the potential at the node T6 decreases, the load capacitance C1 is charged with electric charge via the transistor Q3 in the path indicated by the arrow, and the output terminal T3 becomes a high-level voltage. With respect to the load capacitance C2, electric charge is discharged through the transistors Q6 and Q71 in the path indicated by the arrow, and the output terminal T4 becomes a low level voltage. Since the discharge current of the load capacitance C2 does not flow into the transistor Q72, the potential of the node T72 does not rise. Therefore, the discharge of the load capacitance C2 does not prevent the voltage level of the node T6 from decreasing.

Further, since the discharge current of the load capacitance C2 flows into the transistor Q71, a back electromotive force is generated at both ends thereof, and the voltage level of the node T71 rises. this is,
This is a temporary operation until the discharge of the load capacitance C2 is completed, but this period is a factor for increasing the voltage level of the node T5. However, since the node T5 is inherently a voltage increasing operation, the discharge current from the load capacitance C2 promotes this change.

Thus, the switching operation of the sense circuit is accelerated by preventing the discharge current of the load capacitor C2 from hindering the voltage level drop at the node T6 and promoting the voltage level rise at the node T5.

[Second Embodiment] FIG. 2 shows a second embodiment of the present invention.
FIG. 3 is a circuit diagram of a current-type sensing circuit showing the embodiment.
The circuit shown in FIG. 1 corresponds to MOS transistors Q71, Q71
72, the resistors R3 and R4 are used to connect the circuit node T
71 and T72 are different. It is similar to the circuit shown in FIG. 1 in that the switching operation is accelerated.

In the circuit of FIG. 2, the activation /
Since no switching element is used to control inactivity,
The circuit configuration is simplified. However, input terminals T1, T2
May be connected to a switching element for controlling activation / inactivation.

[Third Embodiment] FIG. 3 is a circuit diagram of a current-type sensing circuit according to a third embodiment. This circuit differs from the circuit of FIG. 2 in that resistors R3 and R4 are replaced by resistors R5 and R5.
Instead of R6, the ground side is commonly connected to a circuit node T8, and a switching transistor Q8 for controlling the activation / inactivation of the sense circuit is connected between the node T8 and the ground.

In the circuit shown in FIG. 2, when a switching element for controlling activation / inactivation is not used on the side of the input terminals T1 and T2, there is a problem that current consumption is increased. However, the circuit shown in FIG. In this case, since the activation / inactivation is controlled by the transistor 8, the problem is solved. Further, the circuit configuration is simplified as compared with the circuit of FIG.

In the circuit shown in FIG.
The addition of 8 reproduces the disadvantage of the prior art in that the discharge current of the load capacitance C2 prevents the voltage level at the node T6 from lowering, but the conduction resistance of the transistor Q8 is smaller than the resistance values of the resistors R5 and R6. Is set sufficiently low, the effect can be suppressed sufficiently low.

[Other Embodiments] In each of the above-described embodiments, Q1 to Q4 are PchMO for convenience of explanation.
Although the S transistors and Q5 to Q7, Q71, Q72, and Q8 are Nch MOS transistors, the present invention can be applied to a relative circuit in which the conductivity types (Nch, Pch) of the MOS transistors are exchanged, and the same effect is exerted. I do.
However, in the relative circuits, the direction of the input current and the polarity (low level voltage / high level voltage) of the activation signal φ _SAE of the sense circuit are different.

[0029]

As described above, according to the first aspect of the present invention, it is possible not only to prevent the switching operation from being hindered by the discharge current of the load capacitance of the output terminal, but also to accelerate the operation. Therefore, it is applied as a circuit for detecting a small signal from a memory cell in a memory LSI or the like,
There is an excellent effect that data can be read at high speed. Further, according to the second aspect, in the case of grounding via a switching element, activation / inactivation can be controlled at the same portion as in the related art, and in the case of grounding via a resistor, the circuit configuration is simplified. Further, according to the third aspect, simplification of the circuit configuration can be achieved together with active / inactive control.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a current-type sensing circuit according to a first embodiment.

FIG. 2 is a circuit diagram of a current-type sensing circuit according to a second embodiment.

FIG. 3 is a circuit diagram of a current-type sensing circuit according to a third embodiment.

FIG. 4 is a circuit diagram of a conventional current-type sensing circuit.

[Explanation of symbols]

Q1 to Q4: Pch MOS transistors, Q5 to Q7, Q
71, Q72, Q8: Nch MOS transistors, R1 to
R6: resistance, T1, T2: input terminal, T3, T4: output terminal, T5 to T8, T71, T72: circuit node, C1,
C2: load capacitance, φ _SAE : activation signal, ΔI: increase in current, −ΔI: decrease in current, ΔV: increase in potential, −
ΔV: drop in potential.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-7-230694 (JP, A) JP-A-8-63976 (JP, A) JP-A-6-84377 (JP, A) Shintaro Shibata, “Low Configuration Method of Current Sense Circuit in Voltage Memory ”, IEICE Technical Report, IEICE, May 1995, Vol. 95, No. 71, p. 39-46 (58) Field surveyed (Int.Cl. ⁷ , DB name) G11C 11/40-11/4099 G11C 17/00

Claims (3)

(57) [Claims] 1. A first grounded-gate amplifier connected between a first input terminal and a first circuit node for converting a current signal input to the first input terminal into a voltage signal and outputting the voltage signal. A second grounded-amplifier circuit connected between the circuit and a second input terminal and the second circuit node, for converting a current signal input to the second input terminal into a voltage signal and outputting the voltage signal; A first input terminal connected between the first input terminal and the second circuit node, for inputting and amplifying an output voltage of the second grounded-gate amplifier circuit and outputting the amplified voltage to a first output terminal; CMOS
An inverter amplifier circuit, connected between the second input terminal and the first circuit node, for inputting and amplifying an output voltage of the first grounded-gate amplifier circuit and outputting the amplified voltage to a second output terminal; Second CMOS
A current-type sense circuit comprising an inverter amplifier circuit, wherein the first circuit node and the second circuit node are separated from each other, and each of them is grounded via a predetermined impedance element. 2. The first circuit node and the second circuit node are independently grounded via first and second switching elements, respectively, or independently via first and second resistors, respectively. 2. The current-type sensing circuit according to claim 1, wherein the current-type sensing circuit is grounded. 3. One end of each of the third and fourth resistors is connected independently to the first circuit node and the second circuit node, and the other end of the third and fourth resistors is connected to the conductive resistor. 2. The current-type sensing circuit according to claim 1, wherein the second element is grounded via a third switching element which is sufficiently smaller than the resistance values of the third and fourth resistors.