JP3226166B2 - Ferroelectric capacitor, method of manufacturing the same, and ferroelectric memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to an electrode material comprising P
The present invention relates to a dielectric capacitor having a structure suitable for using a material that is difficult to finely process, such as t (platinum), a method of manufacturing the same, and a dielectric memory using the same.

[0002]

2. Description of the Related Art In recent years, with the progress of film forming technology, non-volatile ferroelectric memories using ferroelectric thin films have been actively developed. This ferroelectric memory is a non-volatile random access memory (Ferroelectric Random Access Memories; FeRA) capable of high-speed rewriting by utilizing high-speed polarization inversion of a ferroelectric thin film and its dielectric polarization.
M), which is advantageous in that the written contents are not erased, unlike a volatile memory in which the information written therein is erased when the power is turned off.

[0003] By the way, currently 64M
In a ferroelectric memory of a high level, Pt (platinum) is used as an electrode material in order to obtain stable dielectric characteristics.
This is because Pt is not easily oxidized and an oxide layer having a high electric resistance value is hardly formed at the interface between the Pt and the dielectric film.
FIG. 13 shows a sectional configuration of a conventional ferroelectric memory 100 using Pt as an electrode material.

The ferroelectric memory 100 includes a transistor 100A and a ferroelectric capacitor 100B. The transistor 100A includes impurity regions 103A and 103B serving as source / drain regions formed in a region surrounded by a field insulating film 102 on the surface of a substrate 101 such as silicon, and these impurity regions 103A and 103B.
A gate electrode (word line) 105 is formed on the substrate 101 between 103B via the gate insulating film 104. The ferroelectric capacitor 100B includes a lower electrode layer 108, a ferroelectric film 109, and an upper electrode layer 11
0 are stacked in this order. Lower electrode layer 1
08 and the upper electrode layer 110 are each made of Pt. The lower electrode layer 108 is formed on a titanium laminated film (TiN / Ti) 107 formed on the interlayer insulating film 106. Ti (titanium) in the titanium laminated film 107
The film functions as an adhesion layer, and the TiN (titanium nitride) film functions as a diffusion preventing layer. The titanium laminated film 107 is provided with a contact hole (contact hole) provided in the interlayer insulating film 106.
Is electrically connected to the impurity region 103A via the polycrystalline silicon plug layer 111 embedded in the substrate.

[0005] The titanium laminated film 107, the lower electrode layer 108 and the ferroelectric film 109 are made of T for preventing diffusion of oxygen.
The upper electrode layer 110 is covered with a laminated film of the iO ₂ film 112 and the CVD SiO ₂ film 113, and is connected to the ferroelectric film 109 through a connection hole provided in the laminated film. The ferroelectric capacitor 100B has an interlayer insulating film 11
4. A connection hole 115 is provided in the interlayer insulating film 114 and the interlayer insulating film 106.
Bit line 116 is electrically connected to impurity region 103B via line 15.

In this dielectric memory 100, when a predetermined voltage is applied to the gate electrode 105 of the transistor 100A, the transistor 100A is turned on, and a current flows between the impurity regions 103A and 103B. Thereby, the dielectric capacitor 1 is connected via the contact plug layer 111.
00B, the upper electrode layer 110 and the lower electrode layer 1
08 is applied to the ferroelectric film 10 as a result.
At 9, polarization occurs. Since this voltage-polarization characteristic has a hysteresis, data of "1" or "0" is stored or read using this hysteresis.

[0007]

The ferroelectric memory 100 has the following problems when processing Pt as an electrode material of the ferroelectric capacitor 100B. In other words, Pt is a substance that is difficult to be oxidized and is stable as an electrode material, so its processing must rely on a physical etching method close to ion milling, but in this ion milling etching method, a mixture of a resist and platinum is used. There is a problem that dusts and sediments that are difficult to remove are generated.

FIGS. 14A and 14B are diagrams for explaining a specific example thereof. FIG. 14A shows a resist film of an electrode pattern on a platinum film 202 provided on a base film 201. This shows a state after a platinum film 203 is formed and the platinum film 202 is selectively removed by milling etching using the resist film 203 as a mask. At this time, the resist film 2
A scattered substance 202a, such as platinum, scattered at the time of etching adheres to the side wall surface of 03. FIG. 14B shows a state after the resist film 203 is removed from this state, and the scattered matter 202 a remains on the processed platinum film 202. Such a situation in which the scattered matter 202a remains is not preferable for fine processing, and this is a factor that hinders high integration of the ferroelectric memory.

The present invention has been made in view of such a problem, and an object thereof is to facilitate processing even when a stable substance such as platinum is used as an electrode material, and to simplify a manufacturing process. An object of the present invention is to provide a dielectric capacitor that can be manufactured, a method for manufacturing the same, and a dielectric memory using the same.

[0010]

According to the ferroelectric capacitor of the present invention, a groove is formed and a first groove is formed in the groove.
An electrode layer, a ferroelectric film and a second electrode layer are laminated in this order.
A first interlayer insulating film in which the laminated structure is buried,
Formed on the first interlayer insulating film, and formed on the second electrode layer in the groove.
Having connection holes facing each other and insulating material on the wall surfaces of the connection holes
Interlayer insulation with sidewall film made of
And a film formed on the second interlayer insulating film.
And electrically connected to the second electrode layer through the space between the sidewall films.
And a continuous wiring layer.

According to the first ferroelectric capacitor of the present invention ,
The manufacturing method is displayed on the substrate on which the switching elements are formed.
Forming an interlayer insulating film having a planarized surface;
Is selectively processed by anisotropic etching
Rectangular or square cross section facing the switching element
Forming a groove having a shape, and heating the interlayer insulating film to form the groove.
Process to smooth the edge of the part by reflow
And a first electrode in a groove having a gentle edge.
Layer, ferroelectric film and second electrode layer were laminated in this order
After that, the surface of the groove is flattened to the surface of the interlayer insulating film.
And the step of forming

According to the second ferroelectric capacitor of the present invention ,
The manufacturing method, on the substrate on which the switching element is formed,
The surface is flattened and the contact plug is buried.
An interlayer insulating film, and anisotropically etch this interlayer insulating film.
The contact plug is processed by
A rectangular or square groove section is
Forming process and isotropic etching after forming groove
A process to increase the volume of the groove by increasing the surface area,
A first electrode layer, a ferroelectric film, and a second electrode layer in the groove;
After stacking in this order, the surface of the groove is
And flattening in accordance with the above.

The third ferroelectric capacitor according to the present invention
The manufacturing method is displayed on the substrate on which the switching elements are formed.
Forming an interlayer insulating film having a planarized surface;
Is processed by anisotropic etching,
Forming a groove facing the switching element;
The first electrode layer, the ferroelectric film and the second electrode layer
After stacking in the order of
Flattening the surface according to the surface of the interlayer insulating film;
After polishing the surface of the part, selectively apply a resist film to the flat area
And the polishing process is performed to form the interlayer insulating film and the groove.
A step of removing convex portions generated on the surface by etching;
Is included.

According to the fourth ferroelectric capacitor of the present invention ,
The manufacturing method is displayed on the substrate on which the switching elements are formed.
Forming an interlayer insulating film having a planarized surface;
Is selectively processed by anisotropic etching
Forming a groove facing the switching element;
A first electrode layer, a ferroelectric film, and a second electrode layer
In this order, and the surface of the interlayer insulating film outside the groove is inside the groove.
Laminated so as to be higher than the surface of the second electrode layer in
After that, the surface of the groove is flattened by chemical mechanical polishing
And the step of performing.

A ferroelectric memory according to the present invention comprises a switching element formed on a surface of a substrate, a first interlayer insulating film provided on the switching element and having a groove, and a first interlayer insulating film having a groove. A ferroelectric capacitor having a structure in which a first electrode layer, a ferroelectric film, and a second electrode layer, which are embedded in the groove and electrically connected to the switching element, are stacked in this order; A second interlayer insulating film formed on the first interlayer insulating film, having a connection hole facing the second electrode layer in the groove, and having a sidewall film made of an insulating material formed on the wall surface of the connection hole; And a wiring layer formed on the second interlayer insulating film and electrically connected to the second electrode layer via a side wall film.

The ferroelectric capacitor and the ferroelectric capacitor according to the present invention
In the dielectric memory, the groove portions of the first interlayer insulating film are respectively provided.
Within the first electrode layer, the ferroelectric film and the second electrode layer
While the laminated structure laminated in this order is buried,
Having a sidewall film (sidewall) on the first interlayer insulating film
Since the second interlayer insulating film is formed,
Together with the connection hole between the wiring layers
The width can be substantially reduced, and the second electrode layer and the wiring
A first electrode layer and a second electrode layer
Are not electrically short-circuited.

According to the first ferroelectric capacitor of the present invention,
In the manufacturing method, a stable material such as platinum is used as the electrode material.
It is easy to process even when using a high quality
Is heated, the cross section is rectangular or square.
Edge of groove-shaped groove becomes smooth by reflow
Therefore, the electric field does not concentrate on the edge portion, so that
Suppresses fluctuations in characteristics of ferroelectric capacitors formed in grooves
Is done. Further, in the second method for manufacturing a ferroelectric capacitor,
Performs isotropic etching followed by isotropic etching
To increase the volume of the groove and increase the surface area.
As a result, the storage capacity further increases.

According to the third ferroelectric capacitor of the present invention,
In the manufacturing method, after polishing the surface of the groove,
Gist film is selectively formed, and interlayer insulation film is formed by polishing.
And the protrusions on the surface of the groove are removed by etching.
Between the first electrode layer and the second electrode layer.
Alternatively, a short circuit between adjacent capacitors is prevented. Ma
Further, in the fourth method of manufacturing a ferroelectric capacitor,
The first electrode layer, the ferroelectric film and the second electrode layer
And the surface of the interlayer insulating film is different from the surface of the second electrode layer.
Layer, so that the chemical mechanical polishing method
When flattened by
Even when stress is concentrated in the groove of the insulating film,
Effectively prevents the breaking of brittle and brittle ferroelectric films
You.

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention.
10 illustrates a cross-sectional configuration of a dielectric memory 10 according to the embodiment. The dielectric memory 10 includes a plurality of (here, two) transistors 10A formed on a substrate 11 such as silicon and a dielectric capacitor 10B paired with each of the transistors 10A.

In a region surrounded by the field insulating film 12 on the surface of the substrate 11, an LDD (Light
ly Doped Drain) structure impurity regions 13A, 13B, 1
3C are respectively formed. These impurity regions 13
Word lines (also serving as gate electrodes) 15A and 15B are formed on the substrate 11 between A and 13C with a gate insulating film 14 interposed therebetween. Two adjacent transistors 10A, 10A are constituted by these impurity regions 13A to 13C and word lines 15A, 15B. The other word lines 15C and 15D are also formed on the field insulating film 12. Each line width of the word lines 15A to 15D is, for example, 0.25 μm.

The transistor 10A is, for example, a BPSG
(Boro-Phospho-Silicate Glass), PSG (Phospho-S
ilicate Glass), NSG (Non-Silicate Glass), SO
0.75μm thickness formed by G (Spin on glass) etc.
m of the interlayer insulating film 16. Interlayer insulating film 1
Reference numeral 6 denotes, for example, a film thickness of 0.4 which is also formed by PSG or the like.
In the present embodiment, each transistor 10A is covered with the interlayer insulating film 17.
, Dielectric capacitors 10B, 10B having a laminated structure
Are buried respectively. That is, the interlayer insulating film 17
Are formed with two grooves 17a and 17b, and a dielectric capacitor 10B having a structure in which a lower electrode layer 18, a dielectric film 19 and an upper electrode layer 20 are laminated in this order in the grooves 17a and 17b is formed. I have. The lower electrode layer 18 corresponds to the first electrode layer of the present invention, the dielectric film 19 corresponds to the dielectric film, and the upper electrode layer 20 corresponds to the second electrode layer. The grooves 17a and 17b have arcuate curved portions from the bottom surface to the side surfaces, and both ends of the lower electrode layer 18 and the dielectric film 19 are curved in accordance with the curved portions of the grooves 17a and 17b. I have.

N ₂ (nitrogen) is introduced into the respective surface regions of the grooves 17a and 17b, thereby forming a mutual diffusion preventing region 17A due to N ₂ . This mutual diffusion preventing area 17A
Accordingly, mutual diffusion between the interlayer insulating film 17 and the lower electrode layer 18 is prevented, and an electrical short circuit between the adjacent lower electrode layers 18 is prevented.

In the present embodiment, each of the lower electrode layer 18 and the upper electrode layer 20 is formed of Pt (platinum). Other than Pt, for example, Ir (iridium), Ru (ruthenium), Rh (rhodium), Pd
(Palladium) or other metal materials.

The dielectric film 19 is formed of a ferroelectric material or a material having a high dielectric constant (ie, high dielectric constant) (hereinafter, referred to as a high dielectric material). The dielectric capacitor 10B becomes a ferroelectric capacitor when using a ferroelectric material, and becomes a high dielectric capacitor when using a high dielectric material. SBT as ferroelectric material
(The general formula is Bi ₂ SrTa ₂ O ₉ ), SBTN (the general formula is Bi ₂ SrTa _2−x Nb _X O ₉ ), PZT (the general formula is Pb (Zr, Ti) O ₃ ), and PLZT (the general formula is The formula is tantalum oxide (V) (a general formula is Ta) as a high dielectric material such as (Pb, La) (Zr, Ti) O _3.
2 O ₅ ), BST (general formula is (Ba, Sr) Ti
O ₃ ) and STO (the general formula is SrTiO ₃ ).

Both ends of the lower electrode layer 18 and the dielectric film 19 are respectively flush with the surface of the upper electrode layer 20 and form a flat surface together with the interlayer insulating film 17.

The interlayer insulating film 16 is provided with contact holes (contact holes) 16a and 16b.
A contact plug layer 21 made of conductive polycrystalline silicon is embedded in each of a and 16b. The lower electrode layers 18 of the dielectric capacitors 10B, 10B are connected to the impurity regions 13A, 13A through the contact plug layers 21.
C are electrically connected to each other. Impurity region 13
A bit line 22 made of, for example, W (tungsten) is electrically connected to B through a connection hole (contact hole) 16 c provided in the interlayer insulating film 16.

On the interlayer insulating film 17, for example, PSG,
An interlayer insulating film 23 made of BPSG, NSG, SOG or the like is provided, and a wiring layer 24a made of, for example, Al (aluminum) is formed through connection holes 23a, 23b formed in the interlayer insulating film 23. 24b is electrically connected to each upper electrode layer 20. These wiring layers 24a and 24b constitute a plate line.

In the dielectric memory 10, when a predetermined voltage is applied to the gate electrode (eg, word line 15A) of the transistor 10A, the transistor 10A turns "on" and a current flows between the impurity regions 13A and 13B. As a result, a current flows through the dielectric capacitor 10B via the contact plug layer 21, and a voltage is applied between the upper electrode layer 20 and the lower electrode layer 18, and as a result, the dielectric film 1
At 9, polarization occurs. Since this voltage-polarization characteristic has a hysteresis, data of "1" or "0" is stored or read using this hysteresis.

In this dielectric memory 10, the dielectric capacitor 10B is embedded in the grooves 17a and 17b of the interlayer insulating film 17, and the lower electrode layer 18 and the dielectric film 19 are formed.
Has a curved configuration at the bottom corners according to the shapes of the grooves 17a and 17b, so that the characteristic variation is small and the contact area of each layer is large and the storage capacitance is large as compared with the conventional dielectric capacitor.

Next, a method of manufacturing the dielectric memory 10 will be described with reference to FIGS.

First, as shown in FIG. 2A, for example, a known DRAM (Dynami
c Random Access Memory) By the same process as the transistor process, the field insulating film 12, the impurity regions 13A to 13C serving as the source / drain, and the word line 15
After forming the A to 15D and the bit line 22, for example, C
An interlayer insulating film 16 made of, for example, BPSG is formed by VD (Chemical Vapor Deposition). Subsequently, the connection holes 16a, 16
Then, polycrystalline silicon is buried in these connection holes 16a and 16b by, for example, a CVD method, and phosphorus (P) is added (doped) in the polycrystalline silicon.
Thus, a contact plug layer 21 is formed. Thereafter, the surface of the interlayer insulating film 16 is formed, for example, by CMP (Chemical and Mecha).
nical Polishing: chemical mechanical polishing), and the BP is formed on the interlayer insulating film 16 by, eg, CVD.
An interlayer insulating film 17 made of SG is formed.

Next, as shown in FIG. 2B, a photoresist film 32 'having a capacitor pattern is formed on the interlayer insulating film 17, and isotropic etching is performed using the photoresist film 32' as a mask. Then, grooves 17a and 17b reaching contact plug layer 21 are formed. As the isotropic etching, for example, wet etching using dilute hydrofluoric acid (HF) as an etchant is performed to obtain a minimum line width (F) (for example, 0.25 μm) between adjacent grooves 17a and 17b.
m) or several minutes until it is less (eg 30 minutes)
Do it for a while.

If the coverage of the lower electrode layer 18, the dielectric film 19 and the upper electrode layer 20 is not good, FIG.
As shown by the dotted line 17c in FIG.
In order to smooth the end (edge) of the opening b, it is preferable to perform reflow (reflow). Specifically, when the interlayer insulating film 17 is formed by BPSG, for example, a heat treatment at 850 ° C. is performed for 10 minutes. Then, the groove 1
Ion implantation or NH ₃ (ammonia) and N ₂ O are applied to the surface of the interlayer insulating film 17 on which the layers 7a and 17b are formed.
RTA (Rapid Thermal Anneal) using (Nitrous oxide)
ing) to inject nitrogen to form a mutual diffusion preventing region 17A.

Next, as shown in FIG. 2C, the lower electrode layer 1 made of, for example, platinum (Pt) and having a thickness of 100 nm is formed.
8, a film thickness 10 of a ferroelectric material such as SBT
A 0 nm dielectric film 19 and an upper electrode layer 20 made of, for example, platinum (Pt) and having a thickness of, for example, 0.5 μm are sequentially formed by, for example, a sputtering method or a CVD method. At this time, if the coefficient of thermal expansion between the interlayer insulating film 17 and the lower electrode layer 18 is greatly different and easily peeled, a buffer layer made of Ta (tantalum) or an oxide thereof is provided, and the lower electrode layer 18 is formed. It is desirable to prevent peeling off.

Next, as shown in FIG. 3A, the grooves 17a, 17a of the lower electrode layer 18, the dielectric film layer 19, and the upper electrode layer 20 are formed by using the interlayer insulating film 17 as an end point detection layer.
Regions other than b are selectively removed by the CMP method and the surface is flattened. Thereby, dielectric capacitors 10B in which both ends of lower electrode layer 18 and dielectric film 19 form a flat surface together with the surface of upper electrode layer 20 are formed in grooves 17a and 17b of interlayer insulating film 17, respectively.

Next, as shown in FIG. 3B, the dielectric capacitor 10B and the interlayer insulating film 17, for example,
The interlayer insulating film 23 made of PSG is formed by the VD method. Subsequently, after forming connection holes 23a and 23b in the interlayer insulating film 23 by a photolithography technique, for example, Al (aluminum) is deposited on the interlayer insulating film 23 and patterned to form wiring layers 24a and 24b. In addition, if necessary, W
(Tungsten) or the like may be filled. Thereafter, the dielectric memory 10 shown in FIG. 1 is completed through a normal metal wiring process.

As described above, in the present embodiment, the interlayer insulating film 17 is formed on the transistors 10A, 10A and the grooves 17a, 17b are provided in the interlayer insulating film 17, and the interlayer insulating film 17 including these grooves 17a, 17b is provided. The lower electrode layer 18, the dielectric film 19, and the upper electrode layer 20 are sequentially stacked on top of each other, and then unnecessary portions are collectively removed by a CMP method to flatten the surface.
The dielectric capacitors 10B and 10B can be easily manufactured even if a material which is difficult to finely process such as t is used. Further, since a fine processing process by the conventional ion milling method is not required, the process is simplified.

Further, in the present embodiment, the interlayer insulating film 17
The region near the lower electrode layer 18 since so as to form a mutual diffusion prevention region 17A by N _2, the interlayer insulating film 17
And the lower electrode layer 18 can be prevented from interdiffusion. Therefore, it is possible to prevent an electric short circuit between the adjacent lower electrode layers 18. Further, in this embodiment, by providing a buffer layer made of Ta (tantalum) or its oxide between the interlayer insulating film 17 and the lower electrode layer 18, peeling of the lower electrode layer 18 can be prevented. it can.

[Second Embodiment] FIG. 4 shows a second embodiment of the present invention.
14 shows a configuration of a dielectric memory 30 according to the embodiment. This dielectric memory 30 includes a dielectric capacitor 3
The cross-sectional shape of OB is different from that of the first embodiment, and the other configuration is the same as that of the first embodiment. Hereinafter, only differences from the first embodiment will be described, and other description will be omitted.

In the present embodiment, each of the grooves 31a and 31b formed in the interlayer insulating film 17 has a tapered portion on its side surface, and has a trapezoidal cross section. Therefore, the lower electrode layer 18, the dielectric film 19, and the upper electrode layer 20 also have tapered portions at both ends according to the shapes of the grooves 31a, 31b. Thus, the grooves 31a,
By providing the tapered portion 31b, the coverage at both ends of each layer can be improved, and the characteristics of the dielectric capacitor 30B are stabilized.

The grooves 31a and 31b can be formed by utilizing the recess of the photoresist film. That is, as shown in FIG. 5, for example, after the interlayer insulating film 17 is formed,
A photoresist film 32 having a groove pattern is formed on the interlayer insulating film 17, and then, for example, at 250 ° C.
By heating at the temperature described above, a tapered portion 32 a is formed at a corner of the photoresist film 32. In this state, when anisotropic etching is performed under a condition that the selectivity with the photoresist is small, grooves 31a and 31b having tapered portions are formed due to the receding photoresist. Thereafter, as in the first embodiment, the lower electrode layer 18, the dielectric film 19, and the upper electrode layer 20 are sequentially stacked, and then the unnecessary portions are collectively removed by a CMP method to planarize the surface. do it.

[Third Embodiment] FIG. 6 shows a third embodiment of the present invention.
9 shows a configuration of a dielectric memory 40 according to the embodiment. In this dielectric memory 40, the thickness of the interlayer insulating film 17 is made larger than that of
a, 41b are deepened, and the cross-sectional shape is rectangular (rectangular)
Alternatively, it has a square shape to increase the capacitor area, that is, to increase the capacity, and is effective in the case where a sufficient signal amount cannot be obtained in the first and second embodiments. Other configurations are the same as those of the first embodiment.

In general, when the shape of the capacitor is rectangular or square, the electric field is concentrated on the corners of each layer, and the amount of characteristic variation increases. However, as in the present embodiment, when the capacitor area in the height direction increases, the characteristic fluctuation amount in the corner portion relatively decreases. Therefore, as in the first and second embodiments, the necessity of curving the corner portion at the bottom of the groove and providing a tapered portion is reduced. Therefore, in the present embodiment, after the interlayer insulating film 17 is anisotropically etched by RIE to form the grooves 41a and 41b having a rectangular cross section, the ends (edges) of the openings are made gentle by reflow, and then As in the first embodiment, the lower electrode layer 18, the dielectric film 1
9 and the upper electrode layer 20 are sequentially laminated, and thereafter, unnecessary portions are collectively removed by a CMP method, whereby a dielectric capacitor having good characteristics can be produced.

Also in the second and third embodiments,
The effects such as that the dielectric capacitor can be easily formed and the process is simplified are the same as those of the first embodiment.

[Fourth Embodiment] FIG. 7 shows a fourth embodiment of the present invention.
1 shows a configuration of a dielectric memory 50 according to the embodiment. In this dielectric memory 50, the groove 51 is formed on the interlayer insulating film 17 by using a resist mask as in the third embodiment.
After the formation of a and 51b, the volume of the trenches 51a and 51b is increased by performing isotropic etching with the resist mask removed or with the resist mask left, thereby increasing the capacitor surface area. It is. In the present embodiment, at the time of this etching, the etching rate of interlayer insulating film 17 is set to be equal to that of contact plug layer 21 made of polycrystalline silicon. As the etching gas, for example, a (CF ₄ + O ₂ ) gas is used.

In this embodiment, the distance W between the grooves 51a and 51b of adjacent capacitors can be set smaller than the minimum line width F by such a method.

Incidentally, the cell structure of the dielectric memory is similar to that of the conventional DRAM, and the development tendency is also the same. Therefore, the ultimate cell area is 4F × 2F (F; minimum line width), and the capacitor plane area is expressed as 3F × F as shown in FIG. On the other hand, the structure of the dielectric memory is greatly different from that of the DRAM in that the upper electrode of each capacitor is electrically connected to a wiring layer (plate line) via a connection hole in the dielectric memory. . Since this connection hole is usually designed with the minimum line width,
When the lithography is taken into consideration, it protrudes from the upper electrode.

In particular, the above-described dielectric memories 10, 30, 4
At 0 and 50, both the lower electrode layer 18 and the upper electrode layer 20 are exposed on the surface of the interlayer insulating film 17 together with the dielectric film 19 as shown in FIG. If the position of the connection hole 23a is shifted as shown, there is a possibility that the lower electrode layer 18 and the upper electrode layer 20 are electrically short-circuited. Hereinafter, a dielectric memory having such a short-circuit prevention structure between electrodes will be described as a fifth embodiment of the present invention.

[Fifth Embodiment] FIGS. 9 and 10 show a process of manufacturing a dielectric memory 60 according to a fifth embodiment. The steps up to FIG. 3B are the same except for the shape of the dielectric capacitor, and the other configurations are substantially the same. Therefore, the description thereof is omitted, and the subsequent steps will be described.

In FIG. 9, similar to the above embodiment,
After forming a dielectric capacitor including the lower electrode layer 62, the dielectric film 63 and the upper electrode layer 64 in the grooves 61a and 61b of the interlayer insulating film 17, respectively, the NSG is formed on the dielectric capacitor and the interlayer insulating film 17 by, for example, NSG. An interlayer insulating film 65 is formed. After the connection holes 65a and 65b having the minimum line width F are formed in the interlayer insulating film 65, an insulating film 66 made of SiO ₂ (silicon oxide film) is formed on the interlayer insulating film 65 by, for example, a CVD method. Then, RIE
Then, as shown in FIGS. 10A and 10B, sidewall films 66 are respectively formed on the inner walls of the connection holes 65a and 65b.
A, 66B are formed. Thereby, the connection holes 67a and 67b having a width substantially smaller than the minimum line width F are formed.

Thereafter, similarly to the first embodiment, for example, Al (aluminum) is deposited on the interlayer insulating film 65,
By patterning, wiring layers 68a and 68b (plate lines) are formed. Thereafter, the dielectric memory 60 of the present embodiment is completed through a normal metal wiring process.

In this embodiment, the wiring layers 68a, 68b
Since the sidewall film 66A is formed at the electrical connection between each of them and the upper electrode layer 64 of the dielectric capacitor 60B, the connection holes 6 having a width substantially smaller than the minimum line width F are formed.
7a and 67b can be formed. Therefore, in the step of connecting the upper electrode layer 64 and the wiring layers 68a and 68b, there is no possibility that the lower electrode layer 62 and the upper electrode layer 64 are electrically short-circuited.

[Sixth Embodiment] In the present embodiment,
After laminating the lower electrode layer, the dielectric film and the upper electrode layer in each of the above embodiments, when the unnecessary portion is removed by the CMP method, plastic strain mainly occurs in the constituent materials of the lower electrode layer and the upper electrode layer. And extra convex portions (burrs) (FIG. 11)
(B) will be described. Here, the dielectric memory 1 according to the first embodiment is described.
A description will be given using 0 as an example. Hereinafter, only the differences from the first embodiment will be described, and the other components are denoted by the same reference numerals as those in the first embodiment, and the description thereof will be omitted.

FIGS. 11A and 11B show main manufacturing steps of the dielectric memory 10 according to the present embodiment. In the present embodiment, first, FIG.
By the same process up to (B), for example, a depth of 400 n
The grooves 17a and 17b having a size of m and a width of 1500 nm are formed.

Next, as shown in FIG. 11A, a 20 nm-thick Ti film and a 120 nm-thick Pt film are sequentially laminated by, for example, a sputtering method to form the lower electrode layer 1.
8 'is formed. After that, for example, SB
A T film is formed, and the SBT film is subjected to a heat treatment to a thickness of 15 mm.
A dielectric film 19 made of 0 nm polycrystalline SBT is formed. Further, an upper electrode layer 20 made of Pt having a thickness of 150 nm is formed on the dielectric film 19 by, for example, a sputtering method.

Next, as shown in FIG. 11B, unnecessary portions of the lower electrode layer 18 ′, the dielectric film 19 and the upper electrode layer 20 are removed, for example, by using the interlayer insulating film 17 as a final inspection layer.
It is removed all at once by the MP method. At this time, since the Pt forming the lower electrode layer 18 ′ and the upper electrode layer 20 is more ductile than the SBT forming the dielectric film 19, the burrs of Pt protrude to the dielectric film 19 side. . That is, on the surfaces of the dielectric film 19 and the interlayer insulating film 17, a projection 18'a of Pt on the lower electrode layer 18 'side and a projection 20a of Pt on the upper electrode layer 20 side are formed. These convex portions 1
Depending on the occurrence of 8′a and 20a, lower electrode layer 1
An electrical short circuit occurs between 8 'and the upper electrode layer 20 or between the adjacent lower electrode layers 18'.

Therefore, in the present embodiment, the substrate 11 is then formed using, for example, an RIE device (RIE-10NL) manufactured by Sacom.
Is mixed with Ar (argon) gas and Cl ₂ (chlorine) gas at a flow rate of, for example, Ar: Cl ₂ = 3: 7.
Etching pressure (gas pressure) while supplying so that
RIE under conditions of 5 mTorr and plasma generation power of 90 W
To remove the projections 18'a and 20a. At this time,
A resist film (not shown) or the like may be formed on a flat region other than the region where the convex portions 18'a and 20a are formed to protect the surface. Under these conditions, the etching rate of Pt is about 13.8 nm / min, and the etching rate of SBT is about 5.7 nm / min. Therefore, the convex portions 18'a and 20a can be efficiently removed. Thereby, the lower electrode layer 18 'as shown in FIG.
A dielectric capacitor in which both ends of dielectric film 19 form a flat surface together with the surface of upper electrode layer 20 is formed in trenches 17a and 17b of interlayer insulating film 17, respectively.

When the lower electrode layer 18 'and the upper electrode layer 20 are formed by using Ir instead of Pt,
When RIE is performed under the conditions described above, the etching rate of Ir is about 4.9 nm / min, and the etching rate of SBT is about 5.7 nm / min, as described above. Therefore, also in this case, the protrusions 18'a and 20a can be removed. Further, even when the lower electrode layer 18 'is made of Ti and Pt and the upper electrode layer 20 is made of Ir, the protrusions 18'a and 20a can be removed.

As described above, in the present embodiment, unnecessary portions of the lower electrode layer 18 ′, the dielectric film 19 and the upper electrode layer 20 are removed by the CMP method and once flattened.
When 8'a and 20a are derived and irregularities occur on the surface,
Since the projections 18'a and 20a are removed by RIE to completely flatten the surface, the lower electrode layer 18 'and the upper electrode layer 20, or the adjacent lower electrode layers 18' are electrically short-circuited. There is no danger of doing so.

[Seventh Embodiment] In the seventh embodiment, even when stress is concentrated in the groove of the interlayer insulating film due to pressure applied from above during CMP, the SB
The present invention relates to a method of manufacturing a dielectric capacitor in which a portion formed in a groove of a hard and brittle dielectric film 19 such as T is not broken, and a dielectric capacitor manufactured by the method.

FIGS. 12A and 12B show main manufacturing steps of the dielectric memory 70 according to the present embodiment. In this embodiment, FIG. 2B of the first embodiment is used.
By the same process as above, for example, a depth of 330 to 350 n
After forming the grooves 17a, 17b, etc. of FIG.
As shown in FIG. 2, a 100 nm-thick lower electrode layer 71 made of, for example, Pt, a 100 nm-thick dielectric film 72 made of, for example, a ferroelectric material such as SBT, and Pt, for example.
Upper electrode layer 73 of, for example, 80 to 100 nm in thickness
Are sequentially formed by, for example, a CVD method or a sputtering method. Here, since the thickness of the upper electrode layer 73 is about 80 to 100 nm, the surface height of the interlayer insulating film 17 is, for example, 5 times larger than the surface height of the upper electrode layer 73.
It is higher in the range of 0 nm or less. In addition, the average value of the particle size of the abrasive such as Al ₂ O ₃ (alumina) used for the CMP is, for example, about 50 nm or less, and in the present embodiment, the height difference is about the average particle size value. It is desirable to be.

Next, as shown in FIG. 12B, the groove portions 17a, 1a of the lower electrode layer 71, the dielectric film layer 72 and the upper electrode layer 73 are formed by using the interlayer insulating film 17 as an end point detection layer.
Regions other than 7b are selectively removed by a CMP method and the surface is flattened. Taking into account that the electrode constituting material such as Pt has ductility as described above, the surface of the upper electrode
The dielectric capacitor 70B, which is slightly recessed from each end of the dielectric film 72 or forms a flat surface together with both ends of the lower electrode layer 71 and the dielectric film 72, is formed by the grooves 17a, 17b of the interlayer insulating film 17. Are formed respectively.

As described above, in the present embodiment, when performing the CMP, the dielectric capacitor 70B having a depression approximately equal to or larger than the average particle size of the abrasive such as Al ₂ O ₃ used for the CMP is used. Since the dielectric film 72 is provided in the grooves 17a and 17b,
Is effectively prevented.

As described above, the present invention has been described with reference to some embodiments. However, the present invention is not limited to the above embodiments, and can be variously modified. For example, in each of the above embodiments, the lower electrode layer, the dielectric film, the upper electrode layer,
Although examples of formation by the D method and the like have been described, these are described in MOCVD (Metal Organic Chemical Vapor Depositio).
n: metalorganic chemical vapor deposition) or other methods such as a sputtering method.

In each of the above embodiments, an example has been described in which the lower electrode layer, the dielectric film, and the upper electrode layer constituting the dielectric capacitor are collectively processed by the CMP method. It may be processed.

Further, in the sixth embodiment, the RIE
Although the example in which the protruding portions 18'a and 20a are removed by the method described above, it can be removed by sputter etching.

Further, in each of the above-described embodiments, an example in which Pt, Ir, or the like is used as a constituent material of the lower electrode layer and the upper electrode layer has been described. However, as the constituent material, Pt, Ir, Ru, Rh, or A transition metal oxygen-containing noble metal containing a noble metal element such as Pd and a transition metal element such as Hf (hafnium) or Zr (zirconium) or Ti and oxygen can also be used. Further, each electrode layer may have not only a single-layer structure but also a multilayer structure made of these materials.

Further, in the seventh embodiment, the method of manufacturing the dielectric capacitor having the shape of the first embodiment has been described. However, the dielectric capacitor having the shape of the second to fifth embodiments may be used. It can be applied to the case of manufacturing.

[0070]

As described above, the ferroelectric capacitor according to any one of claims 1 to 9 and the ferroelectric capacitor according to claim 17
According to the ferroelectric memory described in No. 19 to 19, the first interlayer insulation
The first electrode layer, the ferroelectric film, and the second
Embedding a laminated structure in which electrode layers are laminated in this order
Then, a sidewall film (sidewall) is formed on the first interlayer insulating film.
The second interlayer insulating film having
In addition to increasing the capacitance, minimize the connection hole between wiring layers.
The second electrode can be substantially narrower than the width.
In the step of connecting the layer and the wiring layer, the first electrode layer and the second
Is not electrically short-circuited.

The ferroelectric capacitor according to claim 10
According to the method of manufacturing the sita, the cross section is rectangular or square.
Edge of groove-shaped groove becomes smooth by reflow
Because the electric field does not concentrate on the edge of the groove,
Therefore, the characteristic fluctuation of the ferroelectric capacitor formed in the groove
Is suppressed.

Further, according to the method of manufacturing a ferroelectric capacitor according to any one of claims 11 to 13,
I decided to do isotropic etching after etching
, The groove volume increases, the surface area increases, and the storage capacity increases.
Is further increased.

[0073]

[0074]

[0075]

The ferroelectric capacitor according to claim 14
According to the method for manufacturing the sita, after polishing the surface of the groove,
A resist film is selectively formed on the carrier region and is polished.
Etching of protrusions on the surface of interlayer insulating film and trench
The surface of the groove and interlayer insulation.
The surface of the rim is completely planarized. Therefore, the first
Between or adjacent to the electrode layer and the second electrode layer
The short circuit between capacitors is prevented, and the insulation characteristics of ferroelectric capacitors
To improve the reliability of ferroelectric capacitors
be able to.

[0077] Further, according to the manufacturing method of the strong induction <br/> collector capacitor according to claim 15 or 16, in the groove, the first
The electrode layer, the ferroelectric film and the second electrode layer are arranged in this order.
The surface of the interlayer insulating film is higher than the surface of the second electrode layer.
So that it can be used for chemical mechanical polishing.
Therefore, when flattening, pressure is applied from above and interlayer
Even when stress is concentrated in the groove of the insulating film, it is hard
It is possible to effectively prevent the brittle ferroelectric film from being destroyed.

[Brief description of the drawings]

FIG. 1 is a sectional configuration diagram of a dielectric memory according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of the dielectric memory shown in FIG. 1 for each manufacturing process.

FIG. 3 is a cross-sectional view of each step following the step of FIG. 2;

FIG. 4 is a sectional configuration diagram of a dielectric memory according to a second embodiment of the present invention.

FIG. 5 is a cross-sectional view for explaining a manufacturing process of the dielectric memory shown in FIG.

FIG. 6 is a sectional configuration diagram of a dielectric memory according to a third embodiment of the present invention.

FIG. 7 is a sectional configuration diagram of a dielectric memory according to a fourth embodiment of the present invention.

FIG. 8 is a plan view for describing a short circuit between an upper electrode layer and a lower electrode layer in a dielectric capacitor.

FIG. 9 is a sectional configuration diagram of a dielectric memory according to a fifth embodiment of the present invention.

10 is a cross-sectional view for explaining a manufacturing process of the dielectric memory shown in FIG.

FIG. 11 is a cross-sectional view for explaining a manufacturing process of the dielectric memory according to the sixth embodiment of the present invention.

FIG. 12 is a cross-sectional view for explaining a manufacturing step of the dielectric memory according to the seventh embodiment of the present invention.

FIG. 13 is a cross-sectional view of a conventional ferroelectric memory.

FIG. 14 is a cross-sectional view for explaining a problem of a conventional ferroelectric memory.

[Explanation of symbols]

10, 30, 40, 50, 60, 70 ... dielectric memory,
10A: Transistor, 10B, 70B: Dielectric capacitor, 18, 18 ', 62, 71 ... Lower electrode layer, 18'
a, 20a: convex portion, 19, 63, 72: dielectric film, 2
0, 64, 73: upper electrode layer, 17, 23: interlayer insulating film, 17a, 17b: groove, 23a, 23b: connection hole,
24a, 24b ... wiring layer

────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Katsuyuki Hironaka 6-7-35 Kita Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (56) References JP-A-3-167874 (JP, A) JP-A Heisei JP-A-8-139293 (JP, A) JP-A-8-340092 (JP, A) JP-A-9-148537 (JP, A) JP-A-7-183278 (JP, A) JP-A-4-82262 (JP, A A) JP-A-7-297187 (JP, A) JP-A-8-17829 (JP, A) JP-A-11-251550 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) ) H01L 27/105 H01L 21/822 H01L 27/04

Claims (19)

(57) [Claims] A first interlayer insulating film in which a groove is formed and a laminated structure in which a first electrode layer, a ferroelectric film, and a second electrode layer are laminated in this order in the groove is buried. Formed on the first interlayer insulating film, and the second
A second interlayer insulating film having a connection hole facing the electrode layer and a sidewall film made of an insulating material formed on a wall surface of the connection hole; and formed on the second interlayer insulating film. ferroelectric capacitor, characterized in that a wiring electrically connected to layer on the second electrode layer through between the sidewall films with. 2. The semiconductor device according to claim 1, wherein both end portions of the first electrode layer and the ferroelectric film form a substantially flat surface together with the surfaces of the second electrode layer and the first interlayer insulating film. the ferroelectric capacitor of claim 1 wherein the. 3. The groove portion has a curved portion from a bottom surface to a side surface, and both ends of the first electrode layer and the ferroelectric film have a curved shape in accordance with the curved portion of the groove portion. the ferroelectric capacitor of claim 2 wherein. 4. A tapered portion on a side surface of the groove, and both ends of the first electrode layer and the ferroelectric film are tapered in accordance with the tapered portion of the groove. the ferroelectric capacitor of claim 2 wherein. 5. The cross-sectional shape of the groove portion is rectangular or square, and each of the first electrode layer and the ferroelectric film has a concave shape.
The ferroelectric capacitor according. 6. The method according to claim 1, wherein a mutual diffusion preventing region subjected to a nitriding treatment is provided in the vicinity of the groove.
The ferroelectric capacitor according. Wherein said groove and a ferroelectric capacitor according to claim 1, wherein a buffer layer is provided between the first electrode layer. 8. The ferroelectric film is made of SBT (Bi ₂ SrT).
a ₂ O ₉ ), SBTN (Bi ₂ SrTa _2-X Nb _X O
₉ ), PZT (Pb (Zr, Ti) O ₃ ), PLZT
((Pb, La) (Zr , Ti) O 3) a ferroelectric capacitor according to claim 1, characterized in that it is formed by either. 9. The ferroelectric film is made of Ta ₂ O ₅ , BST
((Ba, Sr) TiO ₃ ), STO (SrTiO ₃ )
2. The method according to claim 1, wherein the first member is formed by any one of the following.
The ferroelectric capacitor according. 10. An interlayer insulating film having a flattened surface is formed on a substrate on which a switching element is formed, and the interlayer insulating film is selectively processed by anisotropic etching to face the switching element. The cross section is rectangular
Or forming a square-shaped groove, and heating the interlayer insulating film to reflow the edge of the groove.
After the first electrode layer, the ferroelectric film and the second electrode layer are laminated in this order in the groove having the gentle edge , the surface of the groove is subjected to the interlayer insulation. method for manufacturing a ferroelectric capacitor which comprises a step of flattening in accordance with the surface of the membrane. 11. A substrate on which switching elements are formed, the surface embed both contact plug that is flattened
Forming a Mareta interlayer insulating film, by processing the interlayer insulating film by anisotropic etching, the contact
Forming a groove having a rectangular or square cross section facing the plug layer ; and forming the groove, and then forming the groove by isotropic etching.
Enlarging the volume of the portion and increasing the surface area, and laminating a first electrode layer, a ferroelectric film and a second electrode layer in this order in the trench, and then, the surface of the trench is contacted with the interlayer insulating film. method for manufacturing a ferroelectric capacitor which comprises a step of flattening fit of the surfaces. 12. The method according to claim 11, wherein the isotropic etching includes the step of:
Between the etching rate of the interlayer insulating film and the contact plug layer.
Wherein the etching rate is equalized.
12. The method for manufacturing a ferroelectric capacitor according to item 11. 13. The method of manufacturing a ferroelectric capacitor according to claim 11, characterized in that to the distance between the grooves of the capacitor adjoining the formation of the groove by the etching becomes the minimum line width or less. 14. An interlayer insulating film having a planarized surface is formed on a substrate on which a switching element is formed, and the interlayer insulating film is processed by anisotropic etching.
Forming a groove facing the switching element, and laminating a first electrode layer, a ferroelectric film and a second electrode layer in this order in the groove, and then performing a chemical mechanical polishing method. A step of flattening the surface of the groove in accordance with the surface of the interlayer insulating film; and polishing the surface of the groove, and then coating a resist film on a flat region.
Selectively formed and, by the polishing treatment, the interlayer insulating film and
And the protrusions on the surface of the groove are removed by etching
Method for manufacturing a ferroelectric capacitor which comprises a step of. 15. An interlayer insulating film whose surface is flattened is formed on a substrate on which a switching element is formed, and the interlayer insulating film is selectively processed by anisotropic etching to face the switching element. Forming a groove in the groove, a first electrode layer, a ferroelectric film, and a second electrode layer in the groove in this order, and the interlayer insulating film outside the groove.
Is closer to the surface of the second electrode layer in the groove.
After stacking so remote higher method of manufacturing a ferroelectric capacitor which comprises a step of flattening the surface of the groove by chemical mechanical polishing. 16. The first electrode layer, the ferroelectric film, and the second electrode layer in this order such that the surface of the interlayer insulating film is higher than the surface of the second electrode layer by 50 nm or less. a ferroelectric capacitor manufacturing method as claimed in claim 15, wherein the laminating. 17. A switching element formed on a surface of a substrate, a first interlayer insulating film provided on the switching element and having a groove, and embedded in the groove of the first interlayer insulating film. said first electrode layer electrically connected to the switching element, the ferroelectric film and the second electrode layer and the ferroelectric capacitor having a laminated in this order, the first interlayer insulating film Formed in the groove, the second in the groove
A second interlayer insulating film having a connection hole facing the electrode layer and a sidewall film made of an insulating material formed on a wall surface of the connection hole; and formed on the second interlayer insulating film. ferroelectric memory is characterized in that a wiring electrically connected to layer on the second electrode layer through between the sidewall films with. 18. The thickness of the first electrode layer is 30 to 15
18. The method according to claim 17, wherein the distance is in a range of 0 nm.
Ferroelectric memory. 19. The ferroelectric film has a thickness of 50 to 120.
strong <br/> ferroelectric memory according to claim 17, wherein a is in the range of nm.