JP3226456B2 - Inverter device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter device, and more particularly, to a vehicle-mounted DC-AC inverter for extracting AC 100 V from a DC power supply, when a load having a large inrush current such as a motor or a light bulb is driven, a current limiter is provided. The present invention relates to an inverter device that operates.

[0002]

2. Description of the Related Art In an in-vehicle inverter, it is desirable that a load can operate as long as the output current is within a rated current in a steady operation after startup even if a large current flows at startup. However, in practice, even if the rated current of the inverter is 5 A, if the inrush current of the load is 40 A, it tends to be impossible to start even at 4 A in the steady state. Normally,
To cover this starting current, the setting of the current limiter of the overcurrent protection circuit is set to several times the rated current.

[0003]

However, in the conventional inverter device, the current limiter cannot be determined unnecessarily in consideration of the initial starting circuit stress. In order to increase the setting of the current limiter, it is necessary to increase the circuit capacity inevitably, and there is a disadvantage that the cost and the size are increased.

Therefore, a main object of the present invention is to reduce the output voltage of a load having a large starting current at the time of starting, before the overcurrent protection circuit operates, and then raise the output voltage to a predetermined voltage. It is an object of the present invention to provide an inverter device that can be initially started with a current smaller than a starting current at the time of normal startup.

[0005]

SUMMARY OF THE INVENTION The present invention relates to an inverter device for performing PWM control of an output voltage, comprising an oscillation circuit for generating a pulse signal, and a pulse signal having a different polarity according to the pulse signal output from the oscillation circuit. and 2-phase waveform generating circuit for generating a switching according to the polarity of different pulse signals output from the 2-phase waveform generator circuit, and a switching circuit for generating an AC voltage, is connected to the switching circuit, first the predetermined Detects voltage according to inrush current of value
Output a detection signal for a first time in response to
A first voltage detection circuit, connected to a switching circuit,
Inrush current of the second value larger than the inrush current of the first value
In response to detecting the corresponding voltage,
A second voltage that outputs a detection signal after a long second time has elapsed
A detection circuit, and a detection signal output from the first voltage detection circuit.
A buffer circuit for reducing the AC voltage output from the switching circuit by reducing the width of the pulse signal output from the oscillation circuit in accordance with the signal, and gradually increasing the width of the pulse signal over a first time. Output from the second voltage detection circuit.
And an overcurrent protection circuit for stopping generation of a pulse signal by the oscillation circuit in accordance with the detected signal .

[0006]

[0007]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

In FIG. 1, a 555 series of pulse generating ICs is used as the oscillation circuit 1, for example. The oscillation circuit 1 generates a square wave pulse signal by oscillating, and supplies the pulse signal to the two-phase waveform generation circuit 2. Two-phase waveform generation circuit 2
Generates square wave pulse signals having different polarities.
The pulse signal of one polarity is applied to the gate of the FET 3 and inverted by the inverter 7 and applied to the gate of the FET 5. The pulse signal of the other polarity is applied to the gate of the FET 4 and inverted by the inverter 8 and applied to the gate of the FET 6. DC voltages are applied to the drains of the FETs 3 and 4. The FETs 3 to 6 constitute a bridge circuit, and the FETs 3 and 6 and the FETs 4 and 5 alternately conduct according to pulse signals having different polarities.
Outputs AC100V. The sources of the FETs 5 and 6 are grounded via the resistor 9, and a voltage is generated across the resistor 9 in accordance with the current flowing to the load, and this voltage is supplied to the buffer circuit 10 and the overcurrent protection circuit 11.

In the buffer circuit 10, a voltage across the resistor 9 is supplied to a comparison input terminal of a comparator 102 via a time constant circuit 101 including a resistor and a capacitor. The time constant circuit 101 is for determining the response speed at which the buffer circuit 10 operates, and delays the input voltage by, for example, 0.1 sec. The comparator 102 compares a predetermined reference voltage with a comparison input, and when the comparison input exceeds the reference voltage,
An "H" level signal is output. Here, the reference voltage is selected, for example, to a value of a voltage generated across the resistor 9 when a current of 20 A flows through the load.

An "H" level signal output from the comparator 102 is applied to the anode of the diode 103, and a capacitor 104 is connected between the cathode of the diode 103 and the ground.
And the resistor 105 are connected. And comparator 1
When 02 outputs the “H” level signal, the signal charges the capacitor 104 via the diode 103.
The capacitor 104 and the resistor 105 are provided for determining a time during which the buffer circuit 10 is operating, and a time constant is determined so as to be, for example, 0.5 sec. The voltage charged in the capacitor 104 is supplied to a comparison input terminal of a comparator 106, and is compared with a predetermined reference voltage. When the comparison input becomes higher than the reference voltage, comparator 106 provides an “H” level signal to the base of transistor 107. The collector of the transistor 107 is connected to the CVB terminal of the oscillation circuit 1 via a time constant circuit of the capacitor 108 and the resistor 109. The capacitor 108 and the resistor 109 detect the inrush current by the buffer circuit 10, and
After the output voltage is lowered for a certain period of time, a time period for gradually returning to 100 VAC is set. When the inrush current is detected by the buffer circuit 10, the CVB terminal of the oscillation circuit 1
In order to reduce the output voltage, the pulse width of the generated pulse signal is reduced.

In the overcurrent protection circuit 11, a voltage across the resistor 9 is supplied to a comparison input terminal of a comparator 112 via a time constant circuit 111 including a capacitor and a resistor.
The time constant circuit 111 is for determining the response speed at which the overcurrent protection circuit 11 operates, but is selected to be larger than the time constant of the time constant circuit 101 because the buffer circuit 10 needs to operate quickly. Comparator 112 compares a predetermined reference voltage with a comparison input, and outputs an “H” level signal when the comparison input exceeds the reference voltage. Here, the reference voltage is selected, for example, to a value of a voltage generated across the resistor 9 when a current of 30 A flows through the load. The “H” level signal output from the comparator 112 is applied to the anode of the diode 113, and a capacitor 114 and a resistor 115 are connected in parallel between the cathode of the diode 113 and the ground. Diode 113, capacitor 114, resistor 11
Reference numeral 5 is for holding the detection state for a certain period of time when the overcurrent protection circuit 11 detects an overcurrent.
The held voltage is applied to a comparison input terminal of a comparator 116, is compared with a predetermined reference voltage, and the output is applied to the base of a transistor 117. When the AC output is short-circuited continuously,
This is to make a time difference between on and off of the output so that the transistor is not destroyed. The collector of the transistor 117 is provided to the RES terminal of the oscillation circuit 1. R of oscillation circuit 1
The ES terminal is for resetting the oscillation circuit 1 and stopping the oscillation output when the overcurrent protection circuit 11 detects an overcurrent.

FIG. 2 is a diagram showing a voltage waveform at the time of startup in the inverter device shown in FIG. 1, and FIG. 3 is a diagram showing a voltage waveform after startup.

Next, a specific operation of the inverter device shown in FIG. 1 will be described with reference to FIGS. When the power is turned on, the oscillating circuit 1 starts oscillating and supplies a pulse signal to the two-phase waveform generating circuit 2. The two-phase waveform generation circuit 2 generates rectangular wave signals having different polarities based on the pulse signal. The FETs 3 to 6 perform switching based on the rectangular wave signal and output AC100V. This AC100V is applied to a load (not shown),
At this time, an inrush current flows. Then, a voltage corresponding to the rush current is generated across the resistor 9.

This voltage is applied to the time constant circuit 10 of the buffer circuit 10.
1 and to the comparison input terminal of the comparator 102 via the time constant circuit 111 of the overcurrent protection circuit 11 as well as to the comparison input terminal of the comparator 102.
When the inrush current is small, the voltage generated at both ends of the resistor 9 is also small. Therefore, the comparators 102 and 112 each determine that the voltage is smaller than the reference voltage, the buffer circuit 10 and the overcurrent protection circuit 11 do not operate, and the AC 100 V continues. And output. However, when the inrush current exceeds the set current, the comparison input of the comparator 102 becomes higher than the reference voltage, so that the comparator 102 outputs an “H” level signal and charges the capacitor 104 via the diode 103. The charged voltage is compared with a reference voltage by a comparator 106. When the comparison input exceeds the reference voltage, an "H" level signal is output, and the transistor 107 is turned on. Thereby, CVB is controlled by the voltage set by the resistor 109, and the pulse width is reduced. afterwards,
The time set by the time constant of the resistor 109 and the capacitor 108, for example, 0.5 seconds, takes a predetermined AC 100
Return to V. As described above, by narrowing the pulse width, the width of the AC voltage switched by the FETs 3 to 6 is narrowed as shown in FIG. 2, so that the effective value is reduced to, for example, 60V. As a result, since the load is not a rush current with respect to AC 100 V but a set low voltage, the rush current is also small.

This voltage drop takes a time determined by the time constant of the capacitor 104 and the resistor 105, for example, 0.5 sec.
Only lasts. When the starting load is large even after 0.5 sec, the buffer circuit 10 operates again, so that the electric charge charged in the capacitor 104 is not discharged, the buffer circuit 10 continues to operate, and the output AC The voltage remains low. If 0.5 second elapses, the buffer circuit 10
If the load current drops to such an extent that does not operate, the comparator 106 determines that the comparison input has become lower than the reference voltage, and sets its output to the “L” level. As a result, the transistor 107 becomes non-conductive, the CVB terminal goes to the “H” level after a time determined by the time constant of the capacitor 108 and the resistor 109, the pulse width of the pulse signal output from the oscillation circuit 1 increases, and the FET 3 The width of the AC voltage generated by the switching of Nos. To 6 becomes wide as shown in FIG. 3, and its effective value becomes 100V.

If the inrush current exceeds 40 A, for example, the comparator 112 detects that the comparison input has become larger than the reference voltage, and charges the capacitor 114 with the "H" level signal to hold the protection operation. . The charging voltage of the capacitor 114 is
Is compared with the reference voltage, and when the output goes to the “H” level, the transistor 117 is turned on and the R
The EC terminal becomes “L” level, and the oscillation circuit 1 stops the oscillation operation. As a result, the switching operation of the FETs 3 to 6 is stopped, and the output of 100 V AC is stopped.

As described above, the inrush current is, for example, 35 A
Above, the buffer circuit 10 narrows the pulse width of the pulse signal output from the oscillation circuit 1, reduces the output AC voltage, reduces the inrush current, and further reduces the inrush even if the pulse width is reduced. If the current is, for example, a starting load of 40 A or more, the oscillation circuit 1
Is stopped, so that when an inrush current of a level at which the overcurrent protection circuit 11 operates flows,
The inrush current can be suppressed by lowering the AC voltage.

Since the setting of the AC voltage and the operation time in the buffering operation can be determined only by the resistance constant, it can be easily changed according to the load. Further, the switching may be performed by a switch.

The above-described example is not limited to the AC 100 V, vehicle-mounted inverter.
The present invention can be applied to a power supply device and the like.

[0020]

As described above, according to the present invention, starting
The overcurrent protection circuit operates for a load with a large starting current.
Before the operation, the width of the pulse signal is reduced by the buffer circuit to reduce the AC voltage output from the switching circuit, and then the AC voltage gradually rises over a certain period of time.
If the starting current is larger than that, the overcurrent protection circuit
As a result, the output voltage can be reduced, so that a load having a large starting current at the time of starting can be initially started with a current smaller than the starting current.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a voltage waveform at the time of startup.

FIG. 3 is a diagram showing a voltage waveform after startup.

[Explanation of symbols]

 Reference Signs List 1 oscillation circuit 2 two-phase waveform generation circuit 3 to 6 FET 7, 8 inverter 10 buffer circuit 11 overcurrent protection circuit 101, 111 time constant circuit 102, 106, 112, 116 comparator 103, 113 diode 104, 108, 114 capacitor 105 , 109, 115 Resistance 107, 117 Transistor

Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H02M 7/48 H02H 3/08 H02H 9/02 H02M 7/5387

Claims (1)

(57) [Claims] 1. An inverter device for performing PWM control of an output voltage, comprising: an oscillation circuit for generating a pulse signal; and a two-phase waveform generation for generating a pulse signal having a different polarity in accordance with the pulse signal output from the oscillation circuit. circuit, wherein the switching according to the polarity of different pulse signals output from the 2-phase waveform generating circuit, a switching circuit for generating an AC voltage, wherein the connection to the switching circuit, a first value predetermined
In response to the detected voltage corresponding to the inrush current, the first
A first voltage detection circuit that outputs a detection signal during a period of time, the first voltage detection circuit is connected to the switching circuit, and outputs a current of the first value.
A voltage corresponding to the inrush current of the second value larger than
A second time longer than said first time,
A second voltage detection circuit that outputs a detection signal after a lapse of time , according to a detection signal output from the first voltage detection circuit;
Te, said narrowed width of a pulse signal output from the oscillation circuit reduces the AC voltage outputted from the switching circuit, said first buffer circuit over time to gradually widen the width of said pulse signal And the second voltage detection
An inverter device comprising an overcurrent protection circuit for stopping generation of a pulse signal by the oscillation circuit in response to a detection signal output from a circuit.