JP3226498B2 - Semiconductor device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art With the increase in the degree of integration of semiconductor devices, the distance between adjacent wiring layers has been reduced, and the increase in capacitance between wiring layers cannot be ignored. When the capacitance between wiring layers increases, the operation speed of the semiconductor device decreases due to wiring delay. In order to prevent this, a technique of forming a low-resistance wiring layer using copper (Cu) has been actively studied in recent years.

Hereinafter, referring to FIGS. 15 to 19,
A conventional technique of a semiconductor device in which a wiring layer is formed using Cu will be described.

[0004] As shown in FIG.
The semiconductor device includes a semiconductor substrate 1, a lower wiring layer 2 formed on the surface of the semiconductor substrate 1, and a silicon dioxide (SiO ₂ ) film 3 deposited on the semiconductor substrate 1 so as to cover the lower wiring layer 2. Tri-silicon tetranitride (Si ₃ N ₄ ) on the SiO ₂ film 3
A film 4 is deposited, and an SiO ₂ film 5 is deposited on the Si ₃ N ₄ film 4. An interlayer insulating film is formed by the SiO ₂ film 3, the Si ₃ N ₄ film 4, and the SiO ₂ film 5.
In this interlayer insulating film, a through hole 6 reaching the lower wiring layer 2 and a groove-shaped concave portion (wiring groove) connected to the through hole 6 are formed.
7 are formed, and a through hole 6 is formed in the wiring groove 7.
Upper wiring layer 12 electrically contacting the lower wiring layer through
Is provided.

[0005] The upper wiring layer 12 is formed of a titanium (Ti) film 8 covering the inner side wall and the bottom surface of the through hole 6 and the wiring groove 7.
And a tantalum nitride (TaN) film 9 deposited on the Ti film 8, a Cu film 10 deposited on the TaN film 9, and a Cu film 11 deposited on the Cu film 10.

A method for manufacturing such a semiconductor device is as follows.

First, as shown in FIG.
Is formed on the surface of the lower wiring layer 2. Next, as shown in FIG. 16, the SiO2 film 3, the Si3N4 film 4, the SiO2 film 5
Are sequentially deposited, and then the lithography method and the dry etching method are alternately applied twice, so that S
A through hole 6 is formed inside the iO2 film 3 and the Si3N4 film 4, and a wiring groove 7 is formed inside the SiO2 film 5. Next, as shown in FIG. 17, after performing the cleaning of the bottom of the through hole 6 by dry etching, physical vapor
A Ti film 8 is deposited by a phase growth method, and a TaN film 9 is subsequently deposited by a chemical vapor deposition method. Next, as shown in FIG. 18, a Cu film 10 is deposited on the surface of the TaN film 9 by physical vapor deposition. Next, sulfuric acid (H2
After cleaning with SO4), the Cu film 1 is formed by electrolytic plating.
A Cu film 11 is deposited on the surface of the “0”. Finally, the Ti film 8, TaN film 9, Cu film 10, and Cu film on the SiO2 film 5
By removing the film 11 by a chemical mechanical polishing method,
A semiconductor device as shown in FIG. 19 is created.

[0008]

When a semiconductor device is manufactured by the above method, the following problems occur.

First, since the specific resistance of the TaN film 9 deposited by the chemical vapor deposition method is high, the connection resistance between the lower wiring layer 2 and the upper wiring layer 12 increases. This causes a reduction in the operation speed of the semiconductor device .

The TaN film 9 is made of Cu film 10 and Cu film.
Since the ability to prevent the diffusion of Cu atoms contained in the film 11 is not sufficient, Cu atoms are converted to SiO2 through the TaN film 9.
The point is that it reaches the film 3 and the SiO 2 film 5. S
Cu atoms reaching the iO 2 film 3 and the SiO 2 film 5
Mobile ions are formed inside the SiO 2 film 3 and the SiO 2 film 5 to increase leakage current between the through holes 6 and between the upper wiring layers 12. This causes a malfunction of the semiconductor device.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device which does not cause a reduction in operation speed or a malfunction, and a method for manufacturing the same.

[0012]

In order to achieve the above object,
First, the method for manufacturing a semiconductor device according to the present invention
A step of forming a first conductor film, and a step of covering the first conductor film.
Depositing an edge film on the substrate;
Forming a recess connected to the first conductor film,
Forming a second conductor film inside the substrate.
Assuming a method for manufacturing a conductor device, forming a second conductor film
The metal nitriding step covers the inner wall and the bottom of the recess.
Depositing a nitride film by chemical vapor deposition and gold
Exposing the surface of the group nitride film to plasma,
Perpendicular to the surface of the metal nitride film formed
By irradiating on, formed on the bottom surface of the recess
The step of densifying the metal nitride film and the surface of the metal nitride film
Metal silicidation by exposing silicon to silicon compounds
Forming an oxide film and depositing gold on the surface of the metal silicide nitride film.
Depositing a metal film.
Tantalum film, tungsten nitride film or molybdenum nitride film
It is.

In the method of manufacturing a semiconductor device according to the present invention,
Work to densify the metal nitride film formed on the bottom of the recess
In the process, cations contained in the plasma are dropped toward the substrate.
Accelerates in the vertical direction to irradiate cations on the surface of the metal nitride film
The metal nitride formed on the bottom of the recess
Including the step of densifying the oxide film by bombardment with cations.
Is preferred.

In the method for manufacturing a semiconductor device according to the present invention,
Depositing a metal nitride film and forming
Densifying the deposited metal nitride film, and
Exposing the surface to the silicon compound and the same vacuum
It is preferably performed continuously in the chamber.

In the method for manufacturing a semiconductor device according to the present invention,
In the step of depositing the metal nitride film, the thickness of the metal nitride film is reduced.
It is preferable that the thickness be 1 nm or more and 50 nm or less.

In the method for manufacturing a semiconductor device according to the present invention,
The metal film is preferably made of copper.

In the method for manufacturing a semiconductor device according to the present invention,
The thickness of the portion of the metal nitride film formed on the bottom of the recess
Was formed on the inner wall of the concave portion of the metal nitride film.
Preferably, it is thinner than the thickness of the part.

In order to achieve the above object, the present invention relates to
A semiconductor device includes a substrate and a first conductor supported by the substrate.
A film formed on the substrate so as to cover the first conductive film.
Formed on the edge film and the insulating film, and a part of the bottom is the first conductive film.
A concave portion connected to the conductor film, and a second conductive member formed in the concave portion
A second conductive film, based on the assumption that the semiconductor device comprises
Is formed so as to cover the inner wall and bottom of the recess.
A metal nitride film whose surface has been exposed to plasma and a metal nitride film
A metal silicide nitride film formed on the film and a metal silicide nitride film.
A metal film deposited on a silicide film;
The thickness of the part of the material film formed on the bottom of the concave
A portion formed on the inner wall of the concave portion of the silicide nitride film
Metal silicide nitride film,
Tantalum silicide film, tungsten silicide nitride film or silicide
This is a molybdenum nitride film.

In the semiconductor device of the present invention, the metal nitride
The part of the film formed on the bottom surface of the recess is made of metal nitride
The film is denser than the portion formed on the inner wall of the concave
Preferably, there is.

In the semiconductor device of the present invention, the metal film is made of copper.
Preferably.

[0021]

[0022]

[0023]

[0024]

[0025]

[0026]

[0027]

[0028]

[0029]

[0030]

[0031]

[0032]

[0033]

[0034]

[0035]

[0036]

[0037]

[0038]

[0039]

[0040]

[0041]

[0042]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor device according to the present invention will be described with reference to FIGS. As shown in FIG. 6, the semiconductor device of this embodiment includes a semiconductor substrate 1 on which an integrated circuit element such as a transistor (not shown) is formed.
01, a lower wiring layer 102 formed on the surface of the semiconductor substrate 101, and a silicon dioxide (SiO ₂ ) film 103 deposited on the semiconductor substrate 101 so as to cover the lower wiring layer (first conductive film) 102. It has. In the present specification, the “semiconductor substrate 101” refers to a single crystal silicon substrate, an integrated circuit element such as a transistor formed on the surface thereof, an insulating film formed on the surface of the single crystal silicon substrate so as to cover the integrated circuit element, or the like. Are expressed in a lump. The lower wiring layer 102 is formed using a conductive material such as tungsten (W), aluminum (Al), and copper (Cu).

[0043] A four nitriding three silicon on the SiO ₂ film 103 (Si ₃ N ₄₎ film 104 is deposited, Si ₃ N ₄ film 1
_{On the} substrate 04, an SiO ₂ film 5 is deposited. SiO ₂ film 1
03, an interlayer insulating film is formed by the Si ₃ N ₄ film 104 and the SiO ₂ film 105. In this interlayer insulating film,
A recess is formed. This recess is formed in the lower wiring layer 102.
, And a groove-like concave portion (wiring groove) 107 connected to the through hole 106. The wiring groove 107 is in electrical contact with the lower wiring layer 102 via the through hole 106. An upper wiring layer 112 is provided. The groove width of the wiring groove 107 is, for example, about 10
0 to 2000 nm, and the depth is, for example, about 100 to 10 nm.
00 nm. In the present embodiment, the inner diameter of the through hole 106 is set equal to the groove width of the wiring groove 107. The plurality of through holes 106 are, for example, 0.1 to 2
It is formed in each wiring groove 107 at intervals of about μm.

The upper wiring layer 112 is formed in the through hole 106.
And a titanium (Ti) film 108 to cover the inner side wall and the bottom surface of the wiring groove 107, a tantalum nitride (TaN) film 109 deposited on the surface of the Ti film 108, and a TaN film 109.
It includes a Cu film 110 formed thereon and a Cu film 111 deposited on the Cu film 110.

The TiN film 109 has a vertical portion (a portion formed on a surface substantially perpendicular to the semiconductor substrate 101) 109 a formed on the inner side wall of the through hole 106 and the wiring groove 107, Wiring groove 10
And a horizontal portion (portion formed on a plane substantially parallel to the semiconductor substrate 101) 109b formed on the bottom surface of the semiconductor device 101 as necessary. Horizontal portion 109 of TiN film 109
The concentration of C in b is lower than the concentration of C in the vertical portion 109a.

Note that the lower wiring layer is not limited to the first-level wiring, and may be at the i-th level (i is an integer of 1 ≦ i <N) of the N-level wiring (N is an integer of 3 or more). I just want it. At this time, the upper wiring is at the j-th layer level (j is i <j ≦
(An integer of N).

With the above configuration, the lower wiring layer 10
The connection resistance between the second wiring layer 112 and the upper wiring layer 112 can be reduced as compared with the related art. The reason is as follows.

The connection resistance between the lower wiring layer 102 and the upper wiring layer 112 is actually determined by the specific resistance of the TaN film deposited on the bottom of the through hole 106. In the present embodiment, the horizontal portion 109b of the TaN film exists at the bottom of the through hole 106, the vertical portion 109a of the TaN film 109 exists on the side wall of the through hole 106, and the concentration of C contained in the horizontal portion 109b. Is lower than the concentration of C contained in the vertical portion 109a. The lower the concentration of C contained in the film, the lower the specific resistance of the TaN film. Therefore, by decreasing the amount of C contained in the TaN film 109b, the lower wiring layer 102 and the upper wiring layer 112 are reduced.
And the connection resistance between them can be made lower than in the prior art.

The method of manufacturing the semiconductor device according to the present embodiment is as follows.

First, as shown in FIG.
The lower wiring layer 102 is formed on the surface of the substrate 1. Lower wiring layer 1
02 is formed by depositing an Al film on the surface of the semiconductor substrate 101 by a sputtering method, and then processing the Al film into a predetermined shape by a lithography method and a dry etching method.

Next, as shown in FIG. 2, by a chemical vapor deposition method of the plasma excitation type SiO2 film (thickness: about 10
0 to 2000 nm) 103, Si3N4 film (film thickness: about 5
), SiO2 film (film thickness: about 100-1)
000 nm) 105 are sequentially deposited, and a lithography method and a dry etching method are alternately applied twice each so that a through hole 106 is formed inside the SiO 2 film 103 and the Si 3 N 4 film 104 to form the SiO 2 film 10.
5, a wiring groove 107 is formed.

Next, as shown in FIG.
r) and hydrogen (H2) after performing the cleaning of the bottom of the via hole 106 by a dry etching method using such, Ti film (thickness by physical vapor deposition: about 0.5
10 nm) 108, and then a TaN film 109 having a thickness of 20 nm is deposited by chemical vapor deposition. Deposition of the TaN film 109 by chemical vapor deposition <br/> length method is performed as follows. The semiconductor substrate 101 on which the Ti film 108 has been deposited is heated to 400 ° C. in a vacuum chamber. Semiconductor substrate 10
When 1 reaches the steady-state temperature, pentakisdimethylamide tantalum (Ta (NMe2) 5) is placed inside the vacuum chamber.
Is introduced together with ammonia (NH3). The introduced Ta (NMe2) 5 and NH3 react on the surface of the Ti film 108, and a TaN film 109 is deposited.

Next, as shown in FIG.
Is exposed to a plasma generated in ammonia (NH3). The plasma contains cations such as NH 2 ions. The plasma generation conditions are adjusted such that these cations are accelerated in the vertical direction toward the semiconductor substrate 101. Thus, the TaN film 109b deposited on a plane parallel to the semiconductor substrate 101
Is densified due to the impact of cations, and accordingly, C contained in the TaN film 109b is desorbed into the gas phase. On the other hand, the vertical portion 109a of the TaN film 109 deposited on a plane perpendicular to the semiconductor substrate 101 is not densified because it is not impacted by cations. as a result,
The TaN film 109b is thinner than the TaN film 109a,
The carbon concentration of the TaN film 109b is
Lower than the carbon concentration. The plasma exposure uses, for example, a parallel plate type plasma generation device or the like, and the pressure of NH 3 gas is set to about 10 to 1000 Pa in the chamber.
Plasma generated by applying power of 200 to 2000 W can be used.

Next, as shown in FIG.
A Cu film 110 is deposited on the surface of the substrate by a physical vapor deposition method. After cleaning the surface of the Cu film 110 with sulfuric acid (H 2 SO 4), the surface of the Cu film
A film 111 is deposited.

Finally, the Ti film 10 on the SiO 2 film 105
8. By removing the TaN film 109, the Cu film 110, and the Cu film 111 by a chemical mechanical polishing method, a semiconductor device as shown in FIG. 6 is manufactured.

Embodiment 2 Another embodiment of the semiconductor device according to the present invention will be described with reference to FIGS. 7 to 13, the same components as those shown in FIGS. 1 to 6 are denoted by the same reference numerals, and description thereof is omitted.

As shown in FIG. 13, the semiconductor device of this embodiment includes a semiconductor substrate 101 on which an integrated circuit element such as a transistor (not shown) is formed, and a lower wiring layer 102 formed on the surface of the semiconductor substrate 101. And a silicon dioxide (SiO ₂ ) film 103 deposited on the semiconductor substrate 101 so as to cover the lower wiring layer 102. Lower wiring layer 1
02 is tungsten (W), aluminum (Al),
It is formed using a conductive material such as copper (Cu).

[0058] A four nitriding three silicon on the SiO ₂ film 103 (Si ₃ N ₄₎ film 104 is deposited, Si ₃ N ₄ film 1
_{On the} substrate 04, an SiO ₂ film 5 is deposited. SiO ₂ film 1
03, an interlayer insulating film is formed by the Si ₃ N ₄ film 104 and the SiO ₂ film 105. In this interlayer insulating film,
A through-hole 106 reaching the lower wiring layer 102 and a groove-like concave portion (wiring groove) 107 connected to the through-hole 106 are formed.
An upper wiring layer 112 that is in electrical contact with the lower wiring layer 102 via the reference numeral 06 is provided. The upper wiring layer 112
A titanium (Ti) film 108 and a Ti film 10 so as to cover the inner side wall and the bottom surface of the through hole 106 and the wiring groove 107;
8, a tantalum nitride (TaN) film 109 deposited on the surface
And a tantalum silicide nitride (TaSiN) film 113 formed on the TaN film 109, a Cu film 110 formed on the TaSiN film 113, and a Cu film 111 deposited on the Cu film 110. .

The TaN film 109 includes a vertical portion (a portion formed on a surface substantially perpendicular to the semiconductor substrate 101) 109 a formed on the inner side wall of the through hole 106 and the wiring groove 107, Wiring groove 10
And a horizontal portion (portion formed on a plane substantially parallel to the semiconductor substrate 101) 109b formed on the bottom surface of the semiconductor device 101 as necessary. Similarly, the TaSiN film 113 is
A vertical portion (a portion formed on a surface substantially perpendicular to the semiconductor substrate 101) 113a formed on the inner wall of the through hole 106 and the wiring groove 107;
6 and a horizontal part (part formed on a plane substantially parallel to the semiconductor substrate 101) 113b formed on the bottom surface of the wiring groove 107, if necessary.

The configuration of the semiconductor device in this embodiment is
The difference from the structure of the first embodiment is that the TaSiN film 113 is formed on the surface of the TaN film 109 as shown in FIG.
Is formed. TaSiN film is TaN
Since the ability to prevent the diffusion of Cu atoms is higher than that of the film, the configuration according to the present embodiment reduces the leakage current between the through holes 106 and between the upper wiring layers 112 according to the first embodiment. Can be reduced.

Here, the thickness of the TaSiN film 113b will be described. The resistivity of the TaSiN film 113b is NH
3 is higher than the resistivity of the TaN film 109b after exposure to the plasma. Therefore, if the thickness of the TaSiN film 113b is too large, the lower wiring layer 102 and the upper wiring layer 112
, The connection resistance increases, and the operating speed of the semiconductor device decreases. For the above reasons, it is desirable that the thickness of the TaSiN film 113b be smaller than the thickness of the TaSiN film 113a.

The method of manufacturing the semiconductor device according to the present embodiment is as follows.

First, as shown in FIG.
The lower wiring layer 102 is formed on the surface of the substrate 1. Next, as shown in FIG. 8, the SiO2 film (thickness: about 100 to 2000 n)
m) 103, Si3N4 film (thickness: about 5 to 50 nm) 1
04 and a SiO2 film (thickness: about 100 to 1000 n)
m) After depositing 105 in order, a lithography method and a dry etching method are alternately applied twice each so that a through hole 106 is formed inside the SiO2 film 103 and the Si3N4 film 104, and a wiring groove 107 is formed inside the SiO2 film 105. To form Next, as shown in FIG.
After cleaning the bottom of the through hole 106 by dry etching, a Ti film 108 is formed by physical vapor deposition, and a TaN film (thickness: about 1 to 50 nm) 109 is formed by chemical vapor deposition. Is deposited. Next, FIG.
As shown in FIG. 7, the surface of the TaN film 109 is exposed to NH3 plasma. As a result, the TaN film 109b deposited on a plane parallel to the semiconductor substrate 101 is densified to receive the impact of cations.
C contained in 09b is desorbed into the gas phase. On the other hand, a TaN film 1 deposited on a plane perpendicular to the semiconductor substrate 101
The 09 vertical portion 109a is not densified because it is not impacted by cations. As a result, the TaN film 109b becomes thinner than the TaN film 109a.
The carbon concentration of 9b is lower than the carbon concentration of the TaN film 109a.

Next, as shown in FIG.
The surface of No. 9 is exposed to disilane (Si2H8). This processing is performed on the semiconductor substrate 1 that has been exposed to the NH3 plasma.
01 is heated to 400 ° C. in a vacuum chamber, and Si 2 H 6 is introduced into the vacuum chamber. Thereby, the TaSiN film 1 is formed on the surface of the TaN film 109a.
13a is a TaSiN film 1 on the surface of the TaN film 109b.
13b is formed, but the thickness of the TaSiN film 113b is smaller than the thickness of the TaSiN film 113a. This is because the TaN film 109b is densified by exposure to NH ₃ plasma, and thus the Si2H6 is
This is due to the fact that it is difficult to diffuse into the inside.

Next, as shown in FIG. 12, Cu film (film thickness by physical vapor deposition on the surface of the TaSiN film 113:
(About 5 to 200 nm) 110 is deposited. After depositing the Cu film 110, the surface of the Cu film 110 is washed with H2SO4, and then the Cu film (film thickness: about 100
(~ 1000 nm) 111 is deposited. Finally, SiO2
Ti film 108, TaN film 109, Cu film 1 on film 105
By removing 10 and Cu film 111 by a chemical mechanical polishing method, a semiconductor device as shown in FIG. 13 is realized.

The semiconductor device of this embodiment can be manufactured using a manufacturing apparatus as shown in FIG. The apparatus includes a vacuum chamber 114 and a vacuum chamber 114.
Susceptor 115 installed inside the susceptor 115
, A heating mechanism 116 such as a heater installed inside the vacuum chamber 114, an exhaust port 117 installed in the vacuum chamber 114, and a Ta (NMe 2) 5 inlet 11 installed in the vacuum chamber 114.
8 and the NH3 inlet 1 installed in the vacuum chamber 114
19, a Si2H6 inlet 120 installed in the vacuum chamber 114, an upper electrode 121 installed inside the vacuum chamber 114 so as to face the susceptor 115, and a high-frequency power supply 122 connected to the sceptor 115 and the upper electrode 121. It has.

The operation of the semiconductor device manufacturing apparatus is as follows. First, the inside of the vacuum chamber 114 is opened to the atmosphere, the semiconductor substrate 101 on which the Ti film 108 has been deposited is set on the susceptor 115, and then the inside of the vacuum chamber 114 is exhausted through the exhaust port 117. When the evacuation is completed, the heating mechanism 116 is operated to heat the semiconductor substrate 101 through the susceptor 115. Semiconductor substrate 101
Heating mechanism 1 such that the steady temperature of
Adjust the 16 outputs. When the temperature of the semiconductor substrate 101 reaches the steady temperature, Ta (NMe2) 5 is introduced from the Ta (NMe2) 5 inlet 118 and NH3 is introduced from the NH3 inlet 119.
3 is introduced. As a result, Ta (NMe2) 5 and NH3
Reacts on the surface of the Ti film 108, and a TaN film 109 is deposited. After a predetermined time has elapsed, Ta (NMe2) 5
Stop introducing. When the partial pressure of Ta (NMe 2) 5 remaining in the vacuum chamber 114 becomes sufficiently small, high frequency power is supplied to the susceptor 115 and the upper electrode 121 by the high frequency power supply 122, and NH 3 plasma is generated inside the vacuum chamber 114. Generate. Thus, the TaN film 109 deposited on a plane parallel to the semiconductor substrate 101
a is densified to receive cation bombardment. When a predetermined time has elapsed, the high-frequency power supply 122 is stopped,
Stop the introduction of NH3. Next, the Si2H6 inlet 12
From 0, Si2H6 is introduced. Thereby, the TaN film 10 is formed.
9, a TaSiN film 113 is formed. Finally,
The operation of the heating mechanism 116 is stopped, and the vacuum chamber 114 is stopped.
Is released to the atmosphere, and then the semiconductor substrate 101 is discharged.

Although the present invention has been described with respect to two embodiments, the present invention is not limited to these embodiments. For example, in the above-described embodiment, the “dual damascene method” in which the through hole 106 and the wiring groove 107 are continuously formed and then the inside thereof is filled with a metal material such as the Cu film 111 is applied. A “single damascene method” in which either the wiring 106 or the wiring groove 107 is formed and then the inside thereof is filled with a metal material such as the Cu film 111 can be applied instead. In the above-described embodiment, SiO2 and Si3N4 are used as materials for insulating between wiring layers, but other materials can be used instead of these. Examples of such a material include SiO2 containing impurities such as fluorine (F) and an organic compound having an insulating property. Further, in the above embodiment, S
Although the Ti film 108 is deposited on the surface of the iO2 film 105 and inside the through hole 106, the deposition of the Ti film 108 becomes unnecessary depending on the type of conductive material forming the lower wiring layer 102. Further, in the above-described embodiment, tantalum nitride is used as a metal for preventing diffusion of Cu atoms, but any metal nitride can be used instead. Examples of such metal nitrides include tungsten nitride (WN) and molybdenum nitride (MoN). WN can be synthesized by using a tungsten amino complex or imide complex instead of Ta (NMe2) 5 as a raw material. An example of such a complex is bis (tertiary butyl imide) bis (tertiary butyl amide) tungsten. WN can be synthesized by using a molybdenum amino complex or imide complex instead of Ta (NMe2) 5 as a raw material. An example of such a complex is bis (dimethylamido) bis (tert-butylimido) molybdenum. In the above embodiment, the TaN film 10
9 was exposed to plasma generated in NH3,
If it is a nitrogen compound, it can be used instead. Examples of such gases include nitrogen (N2) and hydrazine (N2H4). Further, in the above-described embodiment, Si2H6 is used for forming the TaSiN film 113, but a silicon compound can be used instead. Examples of such compounds include silane (S
iH4) and trisilane (Si3H8). Also, in the above-described embodiment, the physical
Although the vapor deposition method is used, the Cu film 110 can be deposited by, for example, a chemical vapor deposition method. Further, in the above-described embodiment, the electrolytic plating method is used for depositing the Cu film 111, but any other depositing method that can fill the through hole 106 and the wiring groove 107 can be used. An example of such a deposition method is an electroless plating method.

Further, as a method of applying ion bombardment to the thin film, plasma irradiation is performed on the thin film, but another method, for example, an ion implantation method may be used.

[0070]

According to the semiconductor device of the present invention, the concentration of carbon contained in the metal nitride film deposited on the bottom of the recess is lower than the concentration of carbon contained in the metal nitride film deposited on the sidewall of the recess of the insulating film. Concentration is lower. The lower the concentration of carbon contained, the lower the specific resistance of the metal nitride,
By adjusting the amount of carbon contained in the metal nitride film deposited at the bottom of the recess such as a through hole, the connection resistance between the lower wiring layer and the upper wiring layer can be reduced as compared with the conventional technology. it can.

According to another semiconductor device of the present invention, the side wall of the through hole and the side wall of the upper wiring layer are covered with the metal silicide nitride film. Since the metal silicide nitride film has a higher ability to prevent the diffusion of copper atoms than the metal nitride, the above structure reduces the concentration of copper atoms contained in the insulating film. Can be.
For this reason, the leak current between the through holes and between the upper wiring layer (second conductive film) can be reduced as compared with the related art.

[Brief description of the drawings]

FIG. 1 is a process sectional view for describing a first embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a process cross-sectional view for explaining a first embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 3 is a process sectional view for describing the first embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 4 is a process sectional view for describing the first embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 5 is a process sectional view for describing the first embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 6 is a sectional view of the first embodiment of the semiconductor device according to the present invention;

FIG. 7 is a process sectional view for describing the second embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 8 is a process sectional view for explaining the second embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 9 is a process sectional view for describing the second embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 10 is a process sectional view for describing the second embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 11 is a process cross-sectional view for explaining the second embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 12 is a process sectional view for describing the second embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 13 is a cross-sectional view for explaining a second embodiment of the semiconductor device according to the present invention.

FIG. 14 is a cross-sectional view of an example of an apparatus for manufacturing a semiconductor device used in the present invention.

FIG. 15 is a process sectional view showing a conventional method for manufacturing a semiconductor device.

FIG. 16 is a process sectional view illustrating a method for manufacturing a conventional semiconductor device.

FIG. 17 is a process cross-sectional view showing a conventional method for manufacturing a semiconductor device.

FIG. 18 is a process sectional view illustrating the method for manufacturing the conventional semiconductor device.

FIG. 19 is a sectional view showing a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Lower wiring layer 3 Silicon dioxide film 4 Trisilicon tetranitride film 5 Silicon dioxide film 6 Through hole 7 Wiring groove 8 Titanium film 9 Tantalum nitride film 10 Copper film 11 Copper film 12 Upper wiring layer 101 Semiconductor substrate 102 Lower wiring Layer 103 Silicon dioxide film 104 Trisilicon tetranitride film 105 Silicon dioxide film 106 Through hole 107 Wiring groove 108 Titanium film 109 Tantalum nitride film 109a Tantalum nitride film 109b Tantalum nitride film 110 Copper film 111 Copper film 112 Upper wiring layer 113 Silicide nitride Tantalum film 113a Tantalum silicide nitride film 113b Tantalum silicide nitride film 114 Vacuum chamber 115 Susceptor 116 Heating mechanism 117 Exhaust port 118 Pentakisdimethylamidantalum tantalum inlet 119 Ammonia inlet 120 Disilane inlet 1 1 upper electrode 122 high frequency power source

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/28-21/288 H01L 21/3205-21/3213 H01L 21/768

Claims (9)

(57) [Claims] And 1. A process of forming a first conductive film on a substrate, wherein the steps of the first conductive film to cover the insulating film deposited on said substrate, said insulating layer, said part of the bottom Connect to the first conductor film
That forming a recess, and forming a second conductive film on the inside of the recess, a process for the preparation of encompassing the semiconductor device, the step of forming the second conductive film, said recess Depositing a metal nitride film by a chemical vapor deposition method so as to cover an inner wall and a bottom surface of the metal nitride film, and exposing a surface of the metal nitride film to plasma to form the concave portion.
Against the surface of the metal nitride film formed on the bottom surface of the part
Irradiation of ions in the vertical direction ,
Densifying the metal nitride film formed on the bottom surface; forming a metal silicide nitride film by exposing the surface of the metal nitride film to a silicon compound; Depositing a metal film on the surface of the nitride film , wherein the metal nitride film is a tantalum nitride film, a tungsten nitride film,
A method of manufacturing a semiconductor device, wherein the method is a silicon film or a molybdenum nitride film . 2. The metal formed on a bottom surface of the recess.
The step of densifying the nitride film is included in the plasma.
The cations are accelerated vertically toward the substrate and
Irradiating the surface of the metal nitride film with cations
Therefore, the metal nitride formed on the bottom surface of the concave portion
A step of densifying the membrane by the impact of the cations.
2. The method of manufacturing a semiconductor device according to claim 1, wherein
Law. 3. A step of depositing said metal nitride film, before
Densification of the metal nitride film formed on the bottom surface of the concave portion
Process and method of manufacturing a semiconductor device according to claim 1 or 2 wherein the step of exposing the surface to a silicon compound of a metal nitride film, which comprises carrying out successively in the same vacuum chamber to . The step of wherein depositing said metal nitride film, according to any one of claims 1 to 3, characterized in that below the metal nitride thickness and more 1nm to 50nm in film A method for manufacturing a semiconductor device. 5. The method according to claim 1, wherein the metal film is made of copper.
A method for manufacturing the semiconductor device according to claim 1.
Construction method. 6. A thickness of a portion of the metal nitride film formed on a bottom surface of the recess is smaller than a thickness of a portion of the metal nitride film formed on an inner wall of the recess. The method of manufacturing a semiconductor device according to claim 1, wherein: 7. A substrate, a first conductive film supported by the substrate, an insulating film formed on the substrate so as to cover the first conductive film, and formed on the insulating film. A concave part in which a part of the bottom is connected to the first conductive film; and a second conductive film formed in the concave part, wherein the second conductive film is A metal nitride film formed so as to cover an inner wall and a bottom surface of the concave portion and having a surface exposed to plasma, a metal silicide nitride film formed on the metal nitride film, and the metal silicide nitride A metal film deposited on the film, wherein a thickness of a portion of the metal silicide nitride film formed on the bottom surface of the concave portion is inside the concave portion of the metal silicide nitride film. The metal silicide nitride film is thinner than the thickness of the portion formed on the wall; Wherein a le film, a tungsten silicide film or a silicide nitride molybdenum nitride film. 8. The bottom of the recess in the metal nitride film.
The part formed on the surface is the metal nitride film
More dense than the part formed on the inner wall of the recess
The semiconductor device according to claim 7, wherein: 9. The semiconductor device according to claim 7, wherein said metal film is made of copper.